clk/exynos5420: add clocks for hdmi subsystem
v3 cover clk/exynos5420: add clocks for hdmi subsystem
Add clock changes for hdmi subsystem for exynos5250 SoC. These include addition of new clocks like mout_hdmi and smmu_tv, associating ID to clk_hdmiphy and some essential corrections.
V3:
1) Assign new ID to divider clock keeping sclk_pixel gate same.
V2:
1) Rebase to Mike's Tree.
2) Change smmu_tv to smmu_mixer.
This set is based on Mike's clk-next branch at
https://git.linaro.org/gitweb?p=people/mturquette/linux.git
Rahul Sharma (5):
clk/exynos5420: add sclk_hdmiphy to the list of special clocks clk/exynos5420: add gate clock for mixer sysmmu clk/exynos5420: fix the order of parents of hdmi mux clk/exynos5420: add hdmi mux to change parents in hdmi driver clk/exynos5420: assign dout_pixel id to pixel clock divider
.../devicetree/bindings/clock/exynos5420-clock.txt | 12 ++++++++++++ drivers/clk/samsung/clk-exynos5420.c | 19 +++++++++++++------ 2 files changed, 25 insertions(+), 6 deletions(-)
Signature · 1 line
1.7.10.4
PATCH v3 1/5 clk/exynos5420: add sclk_hdmiphy to the list of special clocks
Add sclk_hdmiphy to the list of exposed clocks. This is required by hdmi driver to change the parent of hdmi clock.
--- Documentation/devicetree/bindings/clock/exynos5420-clock.txt | 1 + drivers/clk/samsung/clk-exynos5420.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/clock/exynos5420-clock.txt +1 -0
@@ -59,6 +59,7 @@ clock which they consume. sclk_pwm 155 sclk_gscl_wa 156 sclk_gscl_wb 157 + sclk_hdmiphy 158 [Peripheral Clock Gates]
drivers/clk/samsung/clk-exynos5420.c +2 -2
@@ -120,7 +120,7 @@ enum exynos5420_clks { sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel, sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0, sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro, - sclk_pwm, sclk_gscl_wa, sclk_gscl_wb, + sclk_pwm, sclk_gscl_wa, sclk_gscl_wb, sclk_hdmiphy,/* gate clocks */ aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3,
@@ -297,7 +297,7 @@ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initda/* fixed rate clocks generated inside the soc */ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[]__initdata = { -FRATE (none,"sclk_hdmiphy" ,NULL ,CLK_IS_ROOT ,24000000 ), +FRATE (sclk_hdmiphy,"sclk_hdmiphy" ,NULL ,CLK_IS_ROOT ,24000000 ),FRATE (none,"sclk_pwi" ,NULL ,CLK_IS_ROOT ,24000000 ),FRATE (none,"sclk_usbh20" ,NULL ,CLK_IS_ROOT ,48000000 ),FRATE (none,"mphy_refclk_ixtal24" ,NULL ,CLK_IS_ROOT ,48000000 ),
Signature · 1 line
1.7.10.4
PATCH v3 2/5 clk/exynos5420: add gate clock for mixer sysmmu
In reply to Rahul SharmaAdding sysmmu clock for mixer for exynos5420.
--- Documentation/devicetree/bindings/clock/exynos5420-clock.txt | 1 + drivers/clk/samsung/clk-exynos5420.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/clock/exynos5420-clock.txt +1 -0
@@ -180,6 +180,7 @@ clock which they consume. fimc_lite3 495 aclk_g3d 500 g3d 501 + smmu_mixer 502 Example 1: An example of a clock controller node is listed below.
drivers/clk/samsung/clk-exynos5420.c +2 -1
@@ -138,7 +138,7 @@ enum exynos5420_clks { aclk300_gscl =460 , smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0, gscl1, clk_3aa, aclk266_g2d =470 , sss, slim_sss, mdma0, aclk333_g2d =480 , g2d, aclk333_432_gscl =490 , smmu_3aa, smmu_fimcl0, - smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d =500 , g3d, + smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d =500 , g3d, smmu_mixer, nr_clks, };
@@ -725,6 +725,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {GATE (smmu_mscl0,"smmu_mscl0" ,"aclk400_mscl" ,GATE_IP_MSCL ,8 ,0 ,0 ),GATE (smmu_mscl1,"smmu_mscl1" ,"aclk400_mscl" ,GATE_IP_MSCL ,9 ,0 ,0 ),GATE (smmu_mscl2,"smmu_mscl2" ,"aclk400_mscl" ,GATE_IP_MSCL ,10 ,0 ,0 ), + GATE(smmu_mixer, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 0), }; static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
Signature · 1 line
1.7.10.4
PATCH v3 3/5 clk/exynos5420: fix the order of parents of hdmi mux
In reply to Rahul SharmaListing sclk_hdmiphy at 0th position in the list of parents is causing wrong configuration in reg SRC_DISP10.
--- drivers/clk/samsung/clk-exynos5420.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/samsung/clk-exynos5420.c +1 -1
@@ -286,7 +286,7 @@ PNAME(audio2_p) = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll", "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };PNAME (spdif_p) = {"fin_pll" ,"dout_audio0" ,"dout_audio1" ,"dout_audio2" ,"spdif_extclk" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" }; -PNAME (hdmi_p) = {"sclk_hdmiphy" ,"dout_hdmi_pixel" }; +PNAME (hdmi_p) = {"dout_hdmi_pixel" ,"sclk_hdmiphy" };PNAME (maudio0_p) = {"fin_pll" ,"maudio_clk" ,"sclk_dpll" ,"sclk_mpll" ,"sclk_spll" ,"sclk_ipll" ,"sclk_epll" ,"sclk_rpll" };
Signature · 1 line
1.7.10.4
PATCH v3 4/5 clk/exynos5420: add hdmi mux to change parents in hdmi driver
In reply to Rahul Sharmahdmi driver needs to change the parent of hdmi clock to pixel clock or hdmiphy clock, based on the stability of hdmiphy. This patch is exposing the mux for changing the parent.
--- Documentation/devicetree/bindings/clock/exynos5420-clock.txt | 5 +++++ drivers/clk/samsung/clk-exynos5420.c | 5 ++++- 2 files changed, 9 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/clock/exynos5420-clock.txt +5 -0
@@ -182,6 +182,11 @@ clock which they consume. g3d 501 smmu_mixer 502 + Mux ID + ---------------------------- + + mout_hdmi 1024 + Example 1: An example of a clock controller node is listed below. clock: clock-controller@0x10010000 {
drivers/clk/samsung/clk-exynos5420.c +4 -1
@@ -140,6 +140,9 @@ enum exynos5420_clks { aclk333_g2d =480 , g2d, aclk333_432_gscl =490 , smmu_3aa, smmu_fimcl0, smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d =500 , g3d, smmu_mixer, +/* mux clocks */ + mout_hdmi =1024 , + nr_clks, };
@@ -400,7 +403,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {MUX (none,"mout_mipi1" , group2_p,SRC_DISP10 ,16 ,3 ),MUX (none,"mout_dp1" , group2_p,SRC_DISP10 ,20 ,3 ),MUX (none,"mout_pixel" , group2_p,SRC_DISP10 ,24 ,3 ), -MUX (none,"mout_hdmi" , hdmi_p,SRC_DISP10 ,28 ,1 ), +MUX (mout_hdmi,"mout_hdmi" , hdmi_p,SRC_DISP10 ,28 ,1 ),/* MAU Block */ MUX(none, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3),
Signature · 1 line
1.7.10.4
PATCH v3 4/5 clk/exynos5420: add hdmi mux to change parents in hdmi driver
Hi Rahul,
Quoted 18 lines · On Monday 26 of August 2013 14:43:02 Rahul Sharma wrote:
hdmi driver needs to change the parent of hdmi clock to pixel clock or hdmiphy clock, based on the stability of hdmiphy. This patch is exposing the mux for changing the parent.
Signed-off-by Rahul Sharma <[email protected]>--- Documentation/devicetree/bindings/clock/exynos5420-clock.txt | 5+++++
drivers/clk/samsung/clk-exynos5420.c|
5 ++++- 2 files changed, 9 insertions(+), 1 deletion(-)diff --git
a/Documentation/devicetree/bindings/clock/exynos5420-clock.txtb/Documentation/devicetree/bindings/clock/exynos5420-clock.txtindex 5758a69..6f16aa8 100644
Documentation/devicetree/bindings/clock/exynos5420-clock.txt clock which they consume. · line 188
Quoted 7 lines
Documentation/devicetree/bindings/clock/exynos5420-clock.txt +4
-0@@ -182,6 +182,11 @@ clock which they consume. g3d 501 smmu_mixer 502 + Mux ID + ---------------------------- + + mout_hdmi 1024
Is there a need for such big hole between smm_mixer and this clock? I believe that based on the documentation, the total amount of clocks that can be defined may be approximated and some extra margin added, so you don't waste so much of numbering space and memory used for lookup array.
Best regards,
Tomasz
PATCH v3 4/5 clk/exynos5420: add hdmi mux to change parents in hdmi driver
Quoted 24 lines · Tomasz Figa
Hi Rahul,
Quoted 21 lines · On Monday 26 of August 2013 14:43:02 Rahul Sharma wrote:
hdmi driver needs to change the parent of hdmi clock to pixel clock or hdmiphy clock, based on the stability of hdmiphy. This patch is exposing the mux for changing the parent.
Signed-off-by Rahul Sharma <[email protected]>--- Documentation/devicetree/bindings/clock/exynos5420-clock.txt | 5+++++
drivers/clk/samsung/clk-exynos5420.c|
5 ++++- 2 files changed, 9 insertions(+), 1 deletion(-)diff --git
a/Documentation/devicetree/bindings/clock/exynos5420-clock.txtb/Documentation/devicetree/bindings/clock/exynos5420-clock.txtindex 5758a69..6f16aa8 100644Documentation/devicetree/bindings/clock/exynos5420-clock.txt +0
-0@@ -182,6 +182,11 @@ clock which they consume. g3d 501 smmu_mixer 502
Quoted 10 lines
Documentation/devicetree/bindings/clock/exynos5420-clock.txt clock which they consume. · line 188
Quoted 4 lines
Documentation/devicetree/bindings/clock/exynos5420-clock.txt +4
-0+ Mux ID + ---------------------------- + + mout_hdmi 1024Is there a need for such big hole between
smm_mixerand this clock? I believe that based on the documentation, the total amount of clocks that can be defined may be approximated and some extra margin added, so you don't waste so much of numbering space and memory used for lookup array.
Total number of Gates are coming upto the enum value 540. I can leave gap of 64 in between for first mux. Similarly, total muxes in system are 118. Optimum gab would be between 128~150. What you say about these values?
regards,
Rahul Sharma.
Quoted 3 lines
Best regards,
Tomasz
PATCH v3 4/5 clk/exynos5420: add hdmi mux to change parents in hdmi driver
Quoted 40 lines · On Tuesday 27 of August 2013 10:14:01 Rahul Sharma wrote:
Quoted 27 lines · Tomasz Figa
Hi Rahul,
Quoted 24 lines · On Monday 26 of August 2013 14:43:02 Rahul Sharma wrote:
hdmi driver needs to change the parent of hdmi clock to pixel clock or hdmiphy clock, based on the stability of hdmiphy. This patch is exposing the mux for changing the parent.
Signed-off-by Rahul Sharma <[email protected]>---
Documentation/devicetree/bindings/clock/exynos5420-clock.txt | 5+++++
drivers/clk/samsung/clk-exynos5420.c|
5 ++++- 2 files changed, 9 insertions(+), 1 deletion(-)diff --git
a/Documentation/devicetree/bindings/clock/exynos5420-clock.txtb/Documentation/devicetree/bindings/clock/exynos5420-clock.txtindex 5758a69..6f16aa8 100644Documentation/devicetree/bindings/clock/exynos5420-clock.txt +0
-0@@ -182,6 +182,11 @@ clock which they consume. g3d 501 smmu_mixer 502Quoted 11 lines
Documentation/devicetree/bindings/clock/exynos5420-clock.txt clock which they consume. · line 188
Quoted 4 lines
Documentation/devicetree/bindings/clock/exynos5420-clock.txt +4
-0+ Mux ID + ---------------------------- + + mout_hdmi 1024Is there a need for such big hole between
smm_mixerand this clock? I believe that based on the documentation, the total amount of clocks that
can be defined may be approximated and some extra margin added, so you don't waste so much of numbering space and memory used for lookup array.
Quoted 4 lines
Total number of Gates are coming upto the enum value 540. I can leave gap of 64 in between for first mux. Similarly, total muxes in system are
118. Optimum gab would be between 128~150. What you say about these values?
OK, so let's say that muxes should start at 640 and dividers at 768.
Anyway, ideally, we should break from this idea of grouping and convert this way of definition to normal preprocessor macros that could be used inside dts files as well. Then we could detach ourselves from referring to clocks by numbers, because those macros would do that for us, without the need to group clocks together for better readability. See clock driver for S3C64xx [1].
This is an idea for further work, though. For now the values I proposed should be more than enough.
[1] http://thread.gmane.org/gmane.linux.usb.general/90493/focus=21090
Best regards,
Tomasz
PATCH v3 4/5 clk/exynos5420: add hdmi mux to change parents in hdmi driver
Thanks Tomasz,
I will post the reworked patches with above change.
regards,
Rahul Sharma
Quoted 63 lines · Tomasz Figa
Quoted 40 lines · On Tuesday 27 of August 2013 10:14:01 Rahul Sharma wrote:
Quoted 27 lines · Tomasz Figa
Hi Rahul,
Quoted 24 lines · On Monday 26 of August 2013 14:43:02 Rahul Sharma wrote:
hdmi driver needs to change the parent of hdmi clock to pixel clock or hdmiphy clock, based on the stability of hdmiphy. This patch is exposing the mux for changing the parent.
Signed-off-by Rahul Sharma <[email protected]>---
Documentation/devicetree/bindings/clock/exynos5420-clock.txt | 5+++++
drivers/clk/samsung/clk-exynos5420.c|
5 ++++- 2 files changed, 9 insertions(+), 1 deletion(-)diff --git
a/Documentation/devicetree/bindings/clock/exynos5420-clock.txtb/Documentation/devicetree/bindings/clock/exynos5420-clock.txtindex 5758a69..6f16aa8 100644Documentation/devicetree/bindings/clock/exynos5420-clock.txt +0
-0@@ -182,6 +182,11 @@ clock which they consume. g3d 501 smmu_mixer 502Quoted 11 lines
Documentation/devicetree/bindings/clock/exynos5420-clock.txt clock which they consume. · line 188
Quoted 4 lines
Documentation/devicetree/bindings/clock/exynos5420-clock.txt +4
-0+ Mux ID + ---------------------------- + + mout_hdmi 1024Is there a need for such big hole between
smm_mixerand this clock? I believe that based on the documentation, the total amount of clocks that
can be defined may be approximated and some extra margin added, so you don't waste so much of numbering space and memory used for lookup array.Quoted 4 lines
Total number of Gates are coming upto the enum value 540. I can leave gap of 64 in between for first mux. Similarly, total muxes in system are
118. Optimum gab would be between 128~150. What you say about these values?OK, so let's say that muxes should start at 640 and dividers at 768.
Anyway, ideally, we should break from this idea of grouping and convert this way of definition to normal preprocessor macros that could be used inside dts files as well. Then we could detach ourselves from referring to clocks by numbers, because those macros would do that for us, without the need to group clocks together for better readability. See clock driver for S3C64xx [1].
This is an idea for further work, though. For now the values I proposed should be more than enough.
[1] http://thread.gmane.org/gmane.linux.usb.general/90493/focus=21090
Best regards,
Tomasz
PATCH v3 5/5 clk/exynos5420: assign dout_pixel id to pixel clock divider
In reply to Rahul Sharmadout_pixel is a new ID allocated for pixel clock divider. It is queried in the driver to pass as the parent to hdmi clock while switching between parents.
--- Documentation/devicetree/bindings/clock/exynos5420-clock.txt | 5 +++++ drivers/clk/samsung/clk-exynos5420.c | 5 ++++- 2 files changed, 9 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/clock/exynos5420-clock.txt +5 -0
@@ -187,6 +187,11 @@ clock which they consume. mout_hdmi 1024 + Divider ID + ---------------------------- + + dout_pixel 2048 + Example 1: An example of a clock controller node is listed below. clock: clock-controller@0x10010000 {
drivers/clk/samsung/clk-exynos5420.c +4 -1
@@ -143,6 +143,9 @@ enum exynos5420_clks {/* mux clocks */ mout_hdmi =1024 , +/* divider clocks */ + dout_pixel =2048 , + nr_clks, };
@@ -463,7 +466,7 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {DIV (none,"dout_fimd1" ,"mout_fimd1" ,DIV_DISP10 ,0 ,4 ),DIV (none,"dout_mipi1" ,"mout_mipi1" ,DIV_DISP10 ,16 ,8 ),DIV (none,"dout_dp1" ,"mout_dp1" ,DIV_DISP10 ,24 ,4 ), -DIV (none,"dout_hdmi_pixel" ,"mout_pixel" ,DIV_DISP10 ,28 ,4 ), +DIV (dout_pixel,"dout_hdmi_pixel" ,"mout_pixel" ,DIV_DISP10 ,28 ,4 ),/* Audio Block */ DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
Signature · 1 line
1.7.10.4
PATCH v3 5/5 clk/exynos5420: assign dout_pixel id to pixel clock divider
Hi Rahul,
Quoted 17 lines · On Monday 26 of August 2013 14:43:03 Rahul Sharma wrote:
dout_pixelis a new ID allocated for pixel clock divider. It is queried in the driver to pass as the parent to hdmi clock while switching between parents.Signed-off-by Rahul Sharma <[email protected]>--- Documentation/devicetree/bindings/clock/exynos5420-clock.txt | 5+++++
drivers/clk/samsung/clk-exynos5420.c|
5 ++++- 2 files changed, 9 insertions(+), 1 deletion(-)diff --git
a/Documentation/devicetree/bindings/clock/exynos5420-clock.txtb/Documentation/devicetree/bindings/clock/exynos5420-clock.txtindex 6f16aa8..4c069bd 100644
Documentation/devicetree/bindings/clock/exynos5420-clock.txt clock which they consume. · line 193
Quoted 7 lines
Documentation/devicetree/bindings/clock/exynos5420-clock.txt +4
-0@@ -187,6 +187,11 @@ clock which they consume. mout_hdmi 1024 + Divider ID + ---------------------------- + + dout_pixel 2048
That's an even bigger hole.
Could you check in the documentation how many muxes are present in the clock controller of Exynos5420, add some margin (presumably rounding up to some nice value, not necessarily to a power of two) and calculate a more reasonable start value for dividers?
Best regards,
Tomasz'