ARM: dts: Add initial support for Alpine platform
PATCH 4/4 ARM: dts: Add initial support for Alpine platform
This patch introduces an initial device-tree for the Alpine platform.
--- .../bindings/arm/annapurna-labs,alpine.txt | 96 +++++++++++ .../cpu-enable-method/annapurna-labs,alpine-smp | 64 ++++++++ .../devicetree/bindings/vendor-prefixes.txt | 1 + arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/alpine.dts | 181 +++++++++++++++++++++ 5 files changed, 344 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/annapurna-labs,alpine.txt create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/annapurna-labs,alpine-smp create mode 100644 arch/arm/boot/dts/alpine.dts
Documentation/devicetree/bindings/arm/annapurna-labs,alpine.txt new file +96 -0
@@ -0,0 +1,96 @@ +Annapurna Labs Alpine Platform Device Tree Bindings +--------------------------------------------------------------- + +Boards in the Alpine family shall have the following properties: + +* Required root node properties: +compatible: must contain "annapurna-labs,alpine" + +* Example: + +/ { + model = "Annapurna Labs Alpine Dev Board"; + compatible = "annapurna-labs,alpine"; + + ... +} + +* CPU node: + +The Alpine platform includes cortex-a15 cores. +enable-method: must be "annapurna-labs,alpine-smp" to allow smp [1] + +Example: + +cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "annapurna-labs,alpine-smp"; + + cpu at 0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + clocks = <&cpuclk>; + clock-names = "cpu"; + }; + + cpu at 1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + clocks = <&cpuclk>; + clock-names = "cpu"; + }; + + cpu at 2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + clocks = <&cpuclk>; + clock-names = "cpu"; + }; + + cpu at 3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + clocks = <&cpuclk>; + clock-names = "cpu"; + }; +}; + + +* Alpine CPU resume registers + +The CPU resume register are used to define required resume address after +reset. + +Properties: +- compatible : Should contain "annapurna-labs,al-cpu-resume". +- reg : Offset and length of the register set for the device + +Example: + +cpu_resume { + compatible = "annapurna-labs,al-cpu-resume"; + reg = <0xfbff5ed0 0x30>; +}; + +* Alpine System-Fabric Service Registers + +The System-Fabric Service Registers allow various operation on CPU and +system fabric, like powering CPUs off. + +Properties: +- compatible : Should contain "annapurna-labs,al-sysfabric-service". +- reg : Offset and length of the register set for the device + +Example: + +nb_service { + compatible = "annapurna-labs,al-sysfabric-service"; + reg = <0xfb070000 0x10000>; +}; + +[1] arm/cpu-enable-method/annapurna-labs,alpine-smp
Documentation/devicetree/bindings/arm/cpu-enable-method/annapurna-labs,alpine-smp new file +64 -0
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Documentation/devicetree/bindings/vendor-prefixes.txt +1 -0
@@ -17,6 +17,7 @@ amd Advanced Micro Devices (AMD), Inc. amlogic Amlogic, Inc. ams AMS AG amstaos AMS-Taos Inc. +annapurna-labs Annapurna Labs apm Applied Micro Circuits Corporation (APM) arm ARM Ltd. armadeus ARMadeus Systems SARL
arch/arm/boot/dts/Makefile +2 -0
@@ -1,5 +1,7 @@ ifeq ($(CONFIG_OF),y) +dtb-$(CONFIG_ARCH_ALPINE) += alpine_db.dtb + # Keep at91 dtb files sorted alphabetically for each SoC # rm9200 dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb
arch/arm/boot/dts/alpine.dts new file +181 -0
181 lines not on this page · raw message
Signature · 1 line
1.9.1
Arnd Bergmann
maintainerPATCH 4/4 ARM: dts: Add initial support for Alpine platform
Quoted 11 lines · On Sunday 25 January 2015 20:30:59 Tsahee Zidenberg wrote:
This patch introduces an initial device-tree for the Alpine platform.
Signed-off-by Barak Wasserstrom <[email protected]>Signed-off-by Tsahee Zidenberg <[email protected]>--- .../bindings/arm/annapurna-labs,alpine.txt | 96 +++++++++++ .../cpu-enable-method/annapurna-labs,alpine-smp | 64 ++++++++ .../devicetree/bindings/vendor-prefixes.txt | 1 + arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/alpine.dts | 181 +++++++++++++++++++++ 5 files changed, 344 insertions(+)
I'd suggest splitting this into two patches.
Quoted 14 lines
Documentation/devicetree/bindings/arm/annapurna-labs,alpine.txt new file +11
-0@@ -0,0 +1,96 @@ +Annapurna Labs Alpine Platform Device Tree Bindings +--------------------------------------------------------------- + +Boards in the Alpine family shall have the following properties: + +* Required root node properties: +compatible: must contain "annapurna-labs,alpine" + +* Example: + +/ {
Documentation/devicetree/bindings/arm/annapurna-labs,alpine.txt line 21
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Documentation/devicetree/bindings/arm/annapurna-labs,alpine.txt new file +10
-0+ model = "Annapurna Labs Alpine Dev Board"; + compatible = "annapurna-labs,alpine"; + + ... +} + +* CPU node: + +The Alpine platform includes cortex-a15 cores. +enable-method: must be "annapurna-labs,alpine-smp" to allow smp [1]
Any reason for not using PSCI on this platform?
arch/arm/boot/dts/alpine.dts
Quoted 5 lines
arch/arm/boot/dts/alpine.dts new file +0
-0
Most people split this into one .dtsi file for the SoC and one .dts file for a specific machine, to reduce the amount of duplication when there are multiple machines that use the same chip.
Quoted 6 lines
arch/arm/boot/dts/alpine.dts new file +5
-0@@ -0,0 +1,181 @@ +/* + * Copyright 2015 Annapurna Labs Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License,
arch/arm/boot/dts/alpine.dts line 15
Quoted 10 lines
arch/arm/boot/dts/alpine.dts new file +10
-0+ * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */
If you don't mind, please use a dual license for the dts file, to allow distributing the file with other OSs that might to run on the same hardware.
arch/arm/boot/dts/alpine.dts line 23
Quoted 7 lines
arch/arm/boot/dts/alpine.dts new file +7
-0+/dts-v1/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "skeleton64.dtsi" + +/ { + version = "2.4";
This is not documented anywhere.
arch/arm/boot/dts/alpine.dts line 27
Quoted 4 lines
arch/arm/boot/dts/alpine.dts new file +4
-0+ compatible = "annapurna-labs,alpine"; + #address-cells = <2>; + #size-cells = <2>; + clock-ranges;
No "model" property?
arch/arm/boot/dts/alpine.dts line 111
Quoted 5 lines
arch/arm/boot/dts/alpine.dts new file +5
-0+ /* North Bridge Service Registers */ + nb_service { + compatible = "annapurna-labs,al-sysfabric-service"; + reg = <0x0 0xfb070000 0x0 0x10000>; + };
What kinds of other registers are there in this device? Should it be marked as "syscon" so you can use it through a regmap?
Arnd
A message that is not in the archive (sent off-list or not yet received): CABM=7kn8CMGZDPECfEru11O9gkbYFOTSkzHJF+Ku-oMJoFg6sQ@mail.gmail.com
Arnd Bergmann
maintainerPATCH 4/4 ARM: dts: Add initial support for Alpine platform
Quoted 11 lines · On Monday 26 January 2015 16:14:11 Tsahee Zidenberg wrote:
On 26 January 2015 at 13:15, Arnd Bergmann <[email protected]> wrote:> +* CPU node:
Quoted 7 lines
Documentation/devicetree/bindings/arm/annapurna-labs,alpine.txt line 21
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Documentation/devicetree/bindings/arm/annapurna-labs,alpine.txt new file +3
-0+ +The Alpine platform includes cortex-a15 cores. +enable-method: must be "annapurna-labs,alpine-smp" to allow smp [1]Any reason for not using PSCI on this platform?
PSCI is in the roadmap, but not supported by current firmware.
As your initial submission is very minimal regarding driver support, would it be sensible to wait for the firmware to catch up then?
That way you lose SMP support for the moment but could still work on adding the device drivers while testing in uniprocessor mode and then we will see if your firmware is ready once there are more drivers upstream. Once the firmware has PSCI working, it will all just work without the need for extra devices in DT or the custom SMP operations.
Ard
PATCH 4/4 ARM: dts: Add initial support for Alpine platform
Quoted 11 lines · Arnd Bergmann
Quoted 10 lines · On Monday 26 January 2015 16:14:11 Tsahee Zidenberg wrote:
On 26 January 2015 at 13:15, Arnd Bergmann <[email protected]> wrote:> +* CPU node:
Quoted 7 lines
Documentation/devicetree/bindings/arm/annapurna-labs,alpine.txt line 21
Quoted 3 lines
Documentation/devicetree/bindings/arm/annapurna-labs,alpine.txt new file +3
-0+ +The Alpine platform includes cortex-a15 cores. +enable-method: must be "annapurna-labs,alpine-smp" to allow smp [1]Any reason for not using PSCI on this platform?
Quoted 4 lines
Quoted 1 line
PSCI is in the roadmap, but not supported by current firmware.
As your initial submission is very minimal regarding driver support, would it be sensible to wait for the firmware to catch up then?
Arnd,
there are already systems with this soc that shipped without PSCI firmware. and we still would like to support mainline kernel on those systems without forcing firmware upgrade.
saeed
Quoted 9 lines
That way you lose SMP support for the moment but could still work on adding the device drivers while testing in uniprocessor mode and then we will see if your firmware is ready once there are more drivers upstream. Once the firmware has PSCI working, it will all just work without the need for extra devices in DT or the custom SMP operations.
Ard
PATCH 4/4 ARM: dts: Add initial support for Alpine platform
In reply to Tsahee ZidenbergQuoted 14 lines · Tsahee Zidenberg
This patch introduces an initial device-tree for the Alpine platform.
Signed-off-by Barak Wasserstrom <[email protected]>Signed-off-by Tsahee Zidenberg <[email protected]>--- .../bindings/arm/annapurna-labs,alpine.txt | 96 +++++++++++ .../cpu-enable-method/annapurna-labs,alpine-smp | 64 ++++++++ .../devicetree/bindings/vendor-prefixes.txt | 1 + arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/alpine.dts | 181 +++++++++++++++++++++ 5 files changed, 344 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/annapurna-labs,alpine.txt create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/annapurna-labs,alpine-smp create mode 100644 arch/arm/boot/dts/alpine.dts
[...]
Quoted 9 lines
Documentation/devicetree/bindings/arm/cpu-enable-method/annapurna-labs,alpine-smp new file +3
-0@@ -0,0 +1,64 @@ +======================================================== +Secondary CPU enable-method "annapurna-labs,alpine-smp" binding +========================================================
Documentation/devicetree/bindings/arm/cpu-enable-method/annapurna-labs,alpine-smp line 13
Quoted 10 lines
Documentation/devicetree/bindings/arm/cpu-enable-method/annapurna-labs,alpine-smp new file +10
-0+ +This document describes the "annapurna-labs,alpine-smp" method for +enabling secondary CPUs. To apply to all CPUs, a single +"annapurna-labs,alpine-smp" enable method should be defined in the +"cpus" node. + +Enable method name: "annapurna-labs,alpine-smp" +Compatible machines: "annapurna-labs,alpine" +Compatible CPUs: "arm,cortex-a15" +Related properties: (none)
Please describe what the contract of the method is? What's expected of the system, FW, and kernel?
Otherwise the documentation is practically useless.
[...]
Quoted 19 lines
arch/arm/boot/dts/alpine.dts new file +13
-0@@ -0,0 +1,181 @@ +/* + * Copyright 2015 Annapurna Labs Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with
arch/arm/boot/dts/alpine.dts line 23
Quoted 10 lines
arch/arm/boot/dts/alpine.dts new file +10
-0+ * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "skeleton64.dtsi" + +/ { + version = "2.4";
What's this for?
arch/arm/boot/dts/alpine.dts line 27
Quoted 4 lines
arch/arm/boot/dts/alpine.dts new file +4
-0+ compatible = "annapurna-labs,alpine"; + #address-cells = <2>; + #size-cells = <2>; + clock-ranges;
Surely this doesn't mean anything at the root node?
[...]
Quoted 7 lines
arch/arm/boot/dts/alpine.dts new file +7
-0+ soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic_main>; + ranges; +
arch/arm/boot/dts/alpine.dts line 84
Quoted 10 lines
arch/arm/boot/dts/alpine.dts new file +10
-0+ arch-timer { + compatible = "arm,cortex-a15-timer", + "arm,armv7-timer"; + interrupts = + <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <0>; /* Filled by loader */ + };
Please fix your bootloader/FW to configure CNTFRQ on all CPUs whenever they are brought up.
Are CPUs booted at Hyp? If not, is CNTVOFF configured uniformly across CPUs by the bootloader/FW?
If the answer to both those questions is no, timekeeping will not work on this platform.
Quoted 26 lines
arch/arm/boot/dts/alpine.dts new file +26
-0+ + /* Interrupt Controller */ + gic_main: gic_main { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfb001000 0x0 0x1000>, + <0x0 0xfb002000 0x0 0x2000>, + <0x0 0xfb004000 0x0 0x1000>, + <0x0 0xfb006000 0x0 0x2000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + /* CPU Resume registers */ + cpu_resume { + compatible = "annapurna-labs,al-cpu-resume"; + reg = <0x0 0xfbff5ec0 0x0 0x30>; + }; + + /* North Bridge Service Registers */ + nb_service { + compatible = "annapurna-labs,al-sysfabric-service"; + reg = <0x0 0xfb070000 0x0 0x10000>;
arch/arm/boot/dts/alpine.dts line 120
Quoted 10 lines
arch/arm/boot/dts/alpine.dts new file +10
-0+ }; + + /* Performance Monitor Unit */ + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + };
Nit: please bracket list entries individually, as you have done elsewhere.
[...]
arch/arm/boot/dts/alpine.dts line 150
Quoted 3 lines
arch/arm/boot/dts/alpine.dts new file +3
-0+ clocks { + #address-cells = <1>; + #size-cells = <0>;
There is absolutely no need for a clock container node. Please get rid of it, and just place the clocks here without it.
Thanks,
Mark.
PATCH 4/4 ARM: dts: Add initial support for Alpine platform
Quoted 23 lines · Mark Rutland
Quoted 9 lines
Documentation/devicetree/bindings/arm/cpu-enable-method/annapurna-labs,alpine-smp new file +3
-0@@ -0,0 +1,64 @@ +======================================================== +Secondary CPU enable-method "annapurna-labs,alpine-smp" binding +========================================================Documentation/devicetree/bindings/arm/cpu-enable-method/annapurna-labs,alpine-smp line 13
Quoted 10 lines
Documentation/devicetree/bindings/arm/cpu-enable-method/annapurna-labs,alpine-smp new file +10
-0+ +This document describes the "annapurna-labs,alpine-smp" method for +enabling secondary CPUs. To apply to all CPUs, a single +"annapurna-labs,alpine-smp" enable method should be defined in the +"cpus" node. + +Enable method name: "annapurna-labs,alpine-smp" +Compatible machines: "annapurna-labs,alpine" +Compatible CPUs: "arm,cortex-a15" +Related properties: (none)Please describe what the contract of the method is? What's expected of the system, FW, and kernel?
Quoted 1 line
Otherwise the documentation is practically useless.
I'm not sure I understand exactly what you ask.
This is simply documenting the device-tree binding, not much more or less informational than the existing documentation for "berlin-smp". The method is implemented in the previous patch. I will add a little more detail to the implementation itself on the next patchset. The node
Basically: the FW contract is pretty straight forward and tries to keep up with arm/linux requirements. All CPUs boot to the same state, firmware handles necessary initializations in the cases the CPU can't make them because of it's mode.
Quoted 18 lines
Quoted 7 lines
Documentation/devicetree/bindings/arm/cpu-enable-method/annapurna-labs,alpine-smp new file +7
-0+ soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic_main>; + ranges; +Documentation/devicetree/bindings/arm/cpu-enable-method/annapurna-labs,alpine-smp line 30
Quoted 10 lines
Documentation/devicetree/bindings/arm/cpu-enable-method/annapurna-labs,alpine-smp new file +10
-0+ arch-timer { + compatible = "arm,cortex-a15-timer", + "arm,armv7-timer"; + interrupts = + <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <0>; /* Filled by loader */ + };
Quoted 3 lines
Please fix your bootloader/FW to configure CNTFRQ on all CPUs whenever they are brought up.
For completeness, I agree. However, arch_timer_detect_rate in drivers/clocksource/arm_arch_timer.c seems to first try reading the frequency from devicetree, and fall-back to CNTFRQ only if that fails.
Either way, filling the arch-timer in bootloader seems right.
Quoted 6 lines
Are CPUs booted at Hyp? If not, is CNTVOFF configured uniformly across CPUs by the bootloader/FW?
If the answer to both those questions is no, timekeeping will not work on this platform.
Generally yes, all CPUs boot to HYP. We do plan for other options - so thanks for the heads up!
All other comments (unnecessary nodes/properties, bad brackets, etc..)
- will be fixed.
Thank you!
tsahee.
PATCH 4/4 ARM: dts: Add initial support for Alpine platform
In reply to Tsahee ZidenbergHi,
Some comments below. Some of these might be duplicated by other reviewers, apologies if that's the case.
Quoted 24 lines · Tsahee Zidenberg
This patch introduces an initial device-tree for the Alpine platform.
Signed-off-by Barak Wasserstrom <[email protected]>Signed-off-by Tsahee Zidenberg <[email protected]>--- .../bindings/arm/annapurna-labs,alpine.txt | 96 +++++++++++ .../cpu-enable-method/annapurna-labs,alpine-smp | 64 ++++++++ .../devicetree/bindings/vendor-prefixes.txt | 1 + arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/alpine.dts | 181 +++++++++++++++++++++ 5 files changed, 344 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/annapurna-labs,alpine.txt create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/annapurna-labs,alpine-smp create mode 100644 arch/arm/boot/dts/alpine.dtsDocumentation/devicetree/bindings/arm/annapurna-labs,alpine.txt new file +3
-0@@ -0,0 +1,96 @@ +Annapurna Labs Alpine Platform Device Tree Bindings +--------------------------------------------------------------- +
Documentation/devicetree/bindings/arm/annapurna-labs,alpine.txt line 13
Quoted 10 lines
Documentation/devicetree/bindings/arm/annapurna-labs,alpine.txt new file +10
-0+Boards in the Alpine family shall have the following properties: + +* Required root node properties: +compatible: must contain "annapurna-labs,alpine" + +* Example: + +/ { + model = "Annapurna Labs Alpine Dev Board"; + compatible = "annapurna-labs,alpine";
1. Bikeshed comment, feel free to ignore: "annapurna-labs" is a pretty long prefix, feel free to use some sort of abbreviation instead (most do).
2. More important: You should probably have a fallback compatible to the SoC, and not just the board name. That way, if you have several derivative but similar boards you don't have to update the compatible table for every board name.
Documentation/devicetree/bindings/arm/annapurna-labs,alpine.txt line 87
Quoted 8 lines
Documentation/devicetree/bindings/arm/annapurna-labs,alpine.txt new file +8
-0+* Alpine System-Fabric Service Registers + +The System-Fabric Service Registers allow various operation on CPU and +system fabric, like powering CPUs off. + +Properties: +- compatible : Should contain "annapurna-labs,al-sysfabric-service". +- reg : Offset and length of the register set for the device
Double naming: annapurna-labs and "al-*". One is enough.
Actually, "al" seems like it's an unused abbreviation. Feel free to use it per above.
arch/arm/boot/dts/Makefile line 7
Quoted 12 lines
arch/arm/boot/dts/Makefile +2
-0@@ -1,5 +1,7 @@ ifeq ($(CONFIG_OF),y) +dtb-$(CONFIG_ARCH_ALPINE) += alpine_db.dtb + # Keep at91 dtb files sorted alphabetically for each SoC # rm9200 dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb
Common format of these are: <platform_prefix>-boardname.dtb
alpine-devboard.dtb or alpine-db.dtb would be appropriate here.
arch/arm/boot/dts/alpine.dts
Quoted 5 lines
arch/arm/boot/dts/alpine.dts new file +0
-0
As mentioned elsewhere, a dtsi/dts combo is preferred here.
Quoted 5 lines
arch/arm/boot/dts/alpine.dts new file +4
-0@@ -0,0 +1,181 @@ +/* + * Copyright 2015 Annapurna Labs Ltd. + * + * This program is free software; you can redistribute it and/or modify it
arch/arm/boot/dts/alpine.dts line 14
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arch/arm/boot/dts/alpine.dts new file +10
-0+ * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>.
We're asking for dual-license for DTS these days, so that they can be incorporated in non-GPL firmware if needed. See other files in arch/arm/boot/dts for the standard copyright header.
Quoted 78 lines
arch/arm/boot/dts/alpine.dts new file +78
-0+ */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "skeleton64.dtsi" + +/ { + version = "2.4"; + compatible = "annapurna-labs,alpine"; + #address-cells = <2>; + #size-cells = <2>; + clock-ranges; + + /* CPU Configuration */ + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "annapurna-labs,alpine-smp"; + + cpu at 0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + clocks = <&cpuclk>; + clock-names = "cpu"; + }; + + cpu at 1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + clocks = <&cpuclk>; + clock-names = "cpu"; + }; + + cpu at 2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + clocks = <&cpuclk>; + clock-names = "cpu"; + }; + + cpu at 3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + clocks = <&cpuclk>; + clock-names = "cpu"; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic_main>; + ranges; + + arch-timer { + compatible = "arm,cortex-a15-timer", + "arm,armv7-timer"; + interrupts = + <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <0>; /* Filled by loader */ + }; + + /* Interrupt Controller */ + gic_main: gic_main { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + #address-cells = <0>; + interrupt-controller;
arch/arm/boot/dts/alpine.dts line 102
Quoted 10 lines
arch/arm/boot/dts/alpine.dts new file +10
-0+ reg = <0x0 0xfb001000 0x0 0x1000>, + <0x0 0xfb002000 0x0 0x2000>, + <0x0 0xfb004000 0x0 0x1000>, + <0x0 0xfb006000 0x0 0x2000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + /* CPU Resume registers */ + cpu_resume {
Underscores are generally uncommon in node names, here and elsewhere in this file.
Also, please use an unit address @0xfbff5ec0.
Quoted 18 lines
arch/arm/boot/dts/alpine.dts new file +18
-0+ compatible = "annapurna-labs,al-cpu-resume"; + reg = <0x0 0xfbff5ec0 0x0 0x30>; + }; + + /* North Bridge Service Registers */ + nb_service { + compatible = "annapurna-labs,al-sysfabric-service"; + reg = <0x0 0xfb070000 0x0 0x10000>; + }; + + /* Performance Monitor Unit */ + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + };
arch/arm/boot/dts/alpine.dts line 130
Quoted 10 lines
arch/arm/boot/dts/alpine.dts new file +10
-0+ + wdt0 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xfd88c000 0x0 0x1000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sbclk>; + clock-names = "apb_pclk"; + }; + + uart0 {
The label can be uart0, but the node should be generic, and not uart0/uart1 for the two nodes. To distinguish them, include unit address.
Quoted 41 lines
arch/arm/boot/dts/alpine.dts new file +41
-0+ compatible = "ns16550a"; + reg = <0x0 0xfd883000 0x0 0x1000>; + clock-frequency = <0>; /* Filled by loader */ + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart1 { + compatible = "ns16550a"; + reg = <0x0 0xfd884000 0x0 0x1000>; + clock-frequency = <0>; /* Filled by loader */ + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + /* Reference clock */ + refclk: refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; /* Filled by loader */ + }; + + /* South Bridge Clock */ + sbclk: sbclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; /* Filled by loader */ + }; + + /* North Bridge Clock */ + nbclk: nbclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; /* Filled by loader */ + };
arch/arm/boot/dts/alpine.dts line 181
Quoted 10 lines
arch/arm/boot/dts/alpine.dts new file +10
-0+ + /* CPU Clock */ + cpuclk: cpuclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; /* Filled by loader */ + }; + }; + }; +};
-Olof