ppc4xx/Canyonlands added USB board callbacks

index 23874d2..2e30a32 100644
@@ -34,6 +34,18 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH ch
 
 DECLARE_GLOBAL_DATA_PTR;
 
+
+struct ep460c_bcsr {
+	u8 cpld_rev,
+		led_user,
+		board_status,
+		reset_ctrl,
+		flash_ctrl,
+		eth_ctrl,
+		usb_ctrl,
+		irq_ctrl;
+};
+
 #define CONFIG_SYS_BCSR3_PCIE		0x10
 
 #define BOARD_CANYONLANDS_PCIE	1

@@ -41,6 +53,14 @@ DECLARE_GLOBAL_DATA_PTR;
 #define BOARD_GLACIER		3
 #define BOARD_ARCHES		4
 
+#define BCSR_CPLDREV		0x00
+#define BCSR_BRDSTS		0x03
+#define BCSR_FLASHCTRL		0x05
+#define BCSR_ETHCTRL		0x06
+#define BCSR_USBCTRL		0x07
+#define BCSR_USBCTRL_OTG_RST	0x32
+#define BCSR_USBCTRL_HOST_RST	0x01
+
 /*
  * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
  * board specific values.

@@ -112,6 +132,9 @@ int board_early_init_f(void)
 {
 #if !defined(CONFIG_ARCHES)
 	u32 sdr0_cust0;
+	struct ep460c_bcsr *bcsr_data =
+		(struct ep460c_bcsr *)CONFIG_SYS_BCSR_BASE;
+
 #endif
 
 	/*

@@ -172,13 +195,11 @@ int board_early_init_f(void)
 
 #if !defined(CONFIG_ARCHES)
 	/* Enable ethernet and take out of reset */
+
 	out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0);
 
 	/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
-	out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0);
-
-	/* Enable USB host & USB-OTG */
-	out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0);
+	bcsr_data->flash_ctrl = 0;
 
 	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */
 

@@ -186,21 +207,45 @@ int board_early_init_f(void)
 	mtdcr(AHB_TOP, 0x8000004B);
 	mtdcr(AHB_BOT, 0x8000004B);
 
-	if (pvr_460ex()) {
-		/*
-		 * Configure USB-STP pins as alternate and not GPIO
-		 * It seems to be neccessary to configure the STP pins as GPIO
-		 * input at powerup (perhaps while USB reset is asserted). So
-		 * we configure those pins to their "real" function now.
-		 */
-		gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
-		gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
-	}
 #endif
 
 	return 0;
 }
 
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
+int usb_board_init(void)
+{
+	struct ep460c_bcsr *bcsr_data =
+		(struct ep460c_bcsr *)CONFIG_SYS_BCSR_BASE;
+
+	/* Enable USB host & USB-OTG */
+	bcsr_data->usb_ctrl &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
+
+	/*
+	 * Configure USB-STP pins as alternate and not GPIO.
+	 */
+	gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+	gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+
+	return 0;
+}
+
+int usb_board_stop(void)
+{
+	struct ep460c_bcsr *bcsr_data =
+		(struct ep460c_bcsr *)CONFIG_SYS_BCSR_BASE;
+
+	/* Disable USB host & USB-OTG */
+	bcsr_data->usb_ctrl |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
+	return 0;
+}
+
+int usb_board_init_fail(void)
+{
+	return usb_board_stop();
+}
+#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
+
 #if !defined(CONFIG_ARCHES)
 static void canyonlands_sata_init(int board_type)
 {

@@ -244,11 +289,13 @@ int get_cpu_num(void)
 #if !defined(CONFIG_ARCHES)
 int checkboard(void)
 {
+	struct ep460c_bcsr *bcsr_data =
+		(struct ep460c_bcsr *)CONFIG_SYS_BCSR_BASE;
 	char *s = getenv("serial#");
 
 	if (pvr_460ex()) {
 		printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
-		if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
+		if (bcsr_data->board_status & CONFIG_SYS_BCSR3_PCIE)
 			gd->board_type = BOARD_CANYONLANDS_PCIE;
 		else
 			gd->board_type = BOARD_CANYONLANDS_SATA;

@@ -268,7 +315,7 @@ int checkboard(void)
 		break;
 	}
 
-	printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)));
+	printf(", Rev. %X", bcsr_data->cpld_rev);
 
 	if (s != NULL) {
 		puts(", serial# ");

index ac9b3c5..6a70160 100644
@@ -417,6 +417,7 @@
 #define CONFIG_SYS_USB_OHCI_REGS_BASE	(CONFIG_SYS_AHB_BASE | 0xd0000)
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ppc440"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+#define CONFIG_SYS_USB_OHCI_BOARD_INIT
 #endif
 
 /*