clk: sunxi: Improve MMC clocks support

From: Mike Turquette <[email protected]>

A common operation for a clock signal generator is to shift the phase of that signal. This patch introduces a new function to the clk.h API to dynamically adjust the phase of a clock signal. Additionally this patch introduces support for the new function in the common clock framework via the .set_phase call back in struct clk_ops.

Signed-off-by Mike Turquette <[email protected]>

Signed-off-by Maxime Ripard <[email protected]>

---
 drivers/clk/clk.c            | 85
+++++++++++++++++++++++++++++++++++++++++--- include/linux/clk-private.h  |
 1 +
 include/linux/clk-provider.h |  5 +++
 include/linux/clk.h          | 29 +++++++++++++++
 4 files changed, 116 insertions(+), 4 deletions(-)

drivers/clk/clk.c +2 -3

index b76fa69b44cb..d87661af0c72 100644
@@ -117,11 +117,11 @@ static void clk_summary_show_one(struct seq_file *s,
 struct clk *c, int level) if (!c)
 		return;
 
-	seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu\n",
+	seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu %-3d\n",
 		   level * 3 + 1, "",
 		   30 - level * 3, c->name,
 		   c->enable_count, c->prepare_count, clk_get_rate(c),
-		   clk_get_accuracy(c));
+		   clk_get_accuracy(c), clk_get_phase(c));
 }
 
 static void clk_summary_show_subtree(struct seq_file *s, struct clk *c,

@@ -143,8 +143,8 @@ static int clk_summary_show(struct seq_file *s, void
 *data) struct clk *c;
 	struct hlist_head **lists = (struct hlist_head **)s->private;
 
-	seq_puts(s, "   clock                         enable_cnt  prepare_cnt     
  rate   accuracy\n"); -	seq_puts(s,

"--------------------------------------------------------------------------
------\n"); + seq_puts(s, " clock enable_cnt
prepare_cnt rate accuracy phase\n"); + seq_puts(s,
"-------------------------------------------------------------------------- --------------\n");

drivers/clk/clk.c +77 -0

 	clk_prepare_lock();

@@ -180,6 +180,7 @@ static void clk_dump_one(struct seq_file *s, struct clk
 *c, int level) seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
 	seq_printf(s, "\"rate\": %lu", clk_get_rate(c));
 	seq_printf(s, "\"accuracy\": %lu", clk_get_accuracy(c));
+	seq_printf(s, "\"phase\": %d", clk_get_phase(c));
 }
 
 static void clk_dump_subtree(struct seq_file *s, struct clk *c, int level)

@@ -264,6 +265,11 @@ static int clk_debug_create_one(struct clk *clk, struct
 dentry *pdentry) if (!d)
 		goto err_out;
 
+	d = debugfs_create_u32("clk_phase", S_IRUGO, clk->dentry,
+			(u32 *)&clk->phase);
+	if (!d)
+		goto err_out;
+
 	d = debugfs_create_x32("clk_flags", S_IRUGO, clk->dentry,
 			(u32 *)&clk->flags);
 	if (!d)

@@ -1739,6 +1745,77 @@ out:
 EXPORT_SYMBOL_GPL(clk_set_parent);
 
 /**
+ * clk_set_phase - adjust the phase shift of a clock signal
+ * @clk: clock signal source
+ * @degrees: number of degrees the signal is shifted
+ *
+ * Shifts the phase of a clock signal by the specified
+ * degrees. Returns 0 on success, -EERROR otherwise.
+ *
+ * This function makes no distinction about the input or reference
+ * signal that we adjust the clock signal phase against. For example
+ * phase locked-loop clock signal generators we may shift phase with
+ * respect to feedback clock signal input, but for other cases the
+ * clock phase may be shifted with respect to some other, unspecified
+ * signal.
+ *
+ * Additionally the concept of phase shift does not propagate through
+ * the clock tree hierarchy, which sets it apart from clock rates and
+ * clock accuracy. A parent clock phase attribute does not have an
+ * impact on the phase attribute of a child clock.
+ */
+int clk_set_phase(struct clk *clk, int degrees)
+{
+	int ret = 0;
+
+	if (!clk)
+		goto out;
+
+	/* sanity check degrees */
+	degrees %= 360;
+	if (degrees < 0)
+		degrees += 360;
+
+	clk_prepare_lock();
+
+	if (!clk->ops->set_phase)
+		goto out_unlock;
+
+	ret = clk->ops->set_phase(clk->hw, degrees);
+
+	if (!ret)
+		clk->phase = degrees;
+
+out_unlock:
+	clk_prepare_unlock();
+
+out:
+	return ret;
+}
+
+/**
+ * clk_get_phase - return the phase shift of a clock signal
+ * @clk: clock signal source
+ *
+ * Returns the phase shift of a clock node in degrees, otherwise returns
+ * -EERROR.
+ */
+int clk_get_phase(struct clk *clk)
+{
+	int ret = 0;
+
+	if (!clk)
+		goto out;
+
+	clk_prepare_lock();
+	ret = clk->phase;
+	clk_prepare_unlock();
+
+out:
+	return ret;
+}
+
+/**
  * __clk_init - initialize the data structures in a struct clk
  * @dev:	device initializing this clk, placeholder for now
  * @clk:	clk being initialized

include/linux/clk-private.h +1 -0

index efbf70b9fd84..845be30be50f 100644
@@ -46,6 +46,7 @@ struct clk {
 	unsigned int		enable_count;
 	unsigned int		prepare_count;
 	unsigned long		accuracy;
+	int			phase;
 	struct hlist_head	children;
 	struct hlist_node	child_node;
 	unsigned int		notifier_count;

include/linux/clk-provider.h +5 -0

index 411dd7eb2653..201a6195a3eb 100644
@@ -129,6 +129,10 @@ struct dentry;
  *		set then clock accuracy will be initialized to parent accuracy
  *		or 0 (perfect clock) if clock has no parent.
  *
+ * @set_phase:	Shift the phase this clock signal in degrees specified
+ *		by the second argument. Valid values for degrees are
+ *		0-359. Return 0 on success, otherwise -EERROR.
+ *
  * @init:	Perform platform-specific initialization magic.
  *		This is not not used by any of the basic clock types.
  *		Please consider other ways of solving initialization problems

@@ -177,6 +181,7 @@ struct clk_ops {
 				    unsigned long parent_rate, u8 index);
 	unsigned long	(*recalc_accuracy)(struct clk_hw *hw,
 					   unsigned long parent_accuracy);
+	int		(*set_phase)(struct clk_hw *hw, int degrees);
 	void		(*init)(struct clk_hw *hw);
 	int		(*debug_init)(struct clk_hw *hw, struct dentry *dentry);
 };

include/linux/clk.h +0 -0

index fb5e097d8f72..38bdedd3e389 100644
@@ -106,6 +106,25 @@ int clk_notifier_unregister(struct clk *clk, struct

notifier_block *nb); */
long clk_get_accuracy(struct clk *clk);

+/**
+ * clk_set_phase - adjust the phase shift of a clock signal
+ * @clk: clock signal source
+ * @degrees: number of degrees the signal is shifted
+ *
+ * Shifts the phase of a clock signal by the specified degrees. Returns 0 on + * success, -EERROR otherwise.
+ */

include/linux/clk.h +21 -0

+int clk_set_phase(struct clk *clk, int degrees);
+
+/**
+ * clk_get_phase - return the phase shift of a clock signal
+ * @clk: clock signal source
+ *
+ * Returns the phase shift of a clock node in degrees, otherwise returns
+ * -EERROR.
+ */
+int clk_get_phase(struct clk *clk);
+
 #else
 
 static inline long clk_get_accuracy(struct clk *clk)

@@ -113,6 +132,16 @@ static inline long clk_get_accuracy(struct clk *clk)
 	return -ENOTSUPP;
 }
 
+static inline long clk_set_phase(struct clk *clk, int phase)
+{
+	return -ENOTSUPP;
+}
+
+static inline long clk_get_phase(struct clk *clk)
+{
+	return -ENOTSUPP;
+}
+
 #endif
 
 /**

The current phase API doesn't look into the actual hardware to get the phase value, but will rather get it from a variable only set by the set_phase function.

This will cause issue when the client driver will never call the set_phase function, where we can end up having a reported phase that will not match what the hardware has been programmed to by the bootloader or what phase is programmed out of reset.

Add a new get_phase function for the drivers to implement so that we can get this value.

Signed-off-by Maxime Ripard <[email protected]>

---
 drivers/clk/clk.c            | 10 ++++++++++
 include/linux/clk-provider.h |  5 +++++
 2 files changed, 15 insertions(+)

drivers/clk/clk.c +10 -0

index d87661af0c72..113d75db371d 100644
@@ -1934,6 +1934,16 @@ int __clk_init(struct device *dev, struct clk *clk)
 		clk->accuracy = 0;
 
 	/*
+	 * Set clk's phase.
+	 * Since a phase is by definition relative to its parent, just
+	 * query the current clock phase, or just assume it's in phase.
+	 */
+	if (clk->ops->get_phase)
+		clk->phase = clk->ops->get_phase(clk->hw);
+	else
+		clk->phase = 0;
+
+	/*
 	 * Set clk's rate.  The preferred method is to use .recalc_rate.  For
 	 * simple clocks and lazy developers the default fallback is to use the
 	 * parent's rate.  If a clock doesn't have a parent (or is orphaned)

include/linux/clk-provider.h +5 -0

index 69b20d4c1e1a..abec961092a7 100644
@@ -130,6 +130,10 @@ struct dentry;
  *		set then clock accuracy will be initialized to parent accuracy
  *		or 0 (perfect clock) if clock has no parent.
  *
+ * @get_phase:	Queries the hardware to get the current phase of a clock.
+ *		Returned values are 0-359 degrees on success, negative
+ *		error codes on failure.
+ *
  * @set_phase:	Shift the phase this clock signal in degrees specified
  *		by the second argument. Valid values for degrees are
  *		0-359. Return 0 on success, otherwise -EERROR.

@@ -182,6 +186,7 @@ struct clk_ops {
 				    unsigned long parent_rate, u8 index);
 	unsigned long	(*recalc_accuracy)(struct clk_hw *hw,
 					   unsigned long parent_accuracy);
+	int		(*get_phase)(struct clk_hw *hw);
 	int		(*set_phase)(struct clk_hw *hw, int degrees);
 	void		(*init)(struct clk_hw *hw);
 	int		(*debug_init)(struct clk_hw *hw, struct dentry *dentry);

The current phase API doesn't look into the actual hardware to get the phase value, but will rather get it from a variable only set by the set_phase function.

This will cause issue when the client driver will never call the set_phase function, where we can end up having a reported phase that will not match what the hardware has been programmed to by the bootloader or what phase is programmed out of reset.

Add a new get_phase function for the drivers to implement so that we can get this value.

Signed-off-by Maxime Ripard <[email protected]>

---
 drivers/clk/clk.c            | 10 ++++++++++
 include/linux/clk-provider.h |  5 +++++
 2 files changed, 15 insertions(+)

drivers/clk/clk.c +0 -0

index d87661af0c72..113d75db371d 100644
@@ -1934,6 +1934,16 @@ int __clk_init(struct device *dev, struct clk *clk)
                clk->accuracy = 0;

drivers/clk/clk.c +2 -0

+
+       /*
         * Set clk's rate.  The preferred method is to use .recalc_rate.  For
         * simple clocks and lazy developers the default fallback is to use the
         * parent's rate.  If a clock doesn't have a parent (or is orphaned)

include/linux/clk-provider.h +5 -0

index 69b20d4c1e1a..abec961092a7 100644
@@ -130,6 +130,10 @@ struct dentry;
  *             set then clock accuracy will be initialized to parent accuracy
  *             or 0 (perfect clock) if clock has no parent.
  *
+ * @get_phase: Queries the hardware to get the current phase of a clock.
+ *             Returned values are 0-359 degrees on success, negative
+ *             error codes on failure.
+ *
  * @set_phase: Shift the phase this clock signal in degrees specified
  *             by the second argument. Valid values for degrees are
  *             0-359. Return 0 on success, otherwise -EERROR.

@@ -182,6 +186,7 @@ struct clk_ops {
                                    unsigned long parent_rate, u8 index);
        unsigned long   (*recalc_accuracy)(struct clk_hw *hw,
                                           unsigned long parent_accuracy);
+       int             (*get_phase)(struct clk_hw *hw);
        int             (*set_phase)(struct clk_hw *hw, int degrees);
        void            (*init)(struct clk_hw *hw);
        int             (*debug_init)(struct clk_hw *hw, struct dentry *dentry);

Signature · 1 line

2.1.0

Quoting Maxime Ripard (2014-09-11 13:18:17)

Quoted 24 lines

The current phase API doesn't look into the actual hardware to get the phase value, but will rather get it from a variable only set by the set_phase function.

This will cause issue when the client driver will never call the set_phase function, where we can end up having a reported phase that will not match what the hardware has been programmed to by the bootloader or what phase is programmed out of reset.

Add a new get_phase function for the drivers to implement so that we can get this value.

Signed-off-by Maxime Ripard <[email protected]>

---
 drivers/clk/clk.c            | 10 ++++++++++
 include/linux/clk-provider.h |  5 +++++
 2 files changed, 15 insertions(+)

drivers/clk/clk.c +0 -0

index d87661af0c72..113d75db371d 100644
@@ -1934,6 +1934,16 @@ int __clk_init(struct device *dev, struct clk *clk)
                clk->accuracy = 0;

drivers/clk/clk.c int __clk_init(struct device *dev, struct clk *clk) · line 1944

Quoted 10 lines

drivers/clk/clk.c +8 -0

 
        /*
+        * Set clk's phase.
+        * Since a phase is by definition relative to its parent, just
+        * query the current clock phase, or just assume it's in phase.
+        */
+       if (clk->ops->get_phase)
+               clk->phase = clk->ops->get_phase(clk->hw);
+       else
+               clk->phase = 0;

I probably wasn't paying enough attention to this. Based on the coverletter I thought that v3 would introduce something like CLK_GET_PHASE_NOCACHE and stuff that logic into a __clk_get_phase function? Looks like this version of the series doesn't handle phases that can be changed by hardware (e.g. coming out of idle).

Correct me if I am wrong, but it looks like we retrieve the phase only once at init and then never again? The rest of the time we rely on clk->phase to always be accurate...

Hi Mike,

Quoted 42 lines · Mike Turquette

Quoting Maxime Ripard (2014-09-11 13:18:17)

Quoted 24 lines

The current phase API doesn't look into the actual hardware to get the phase value, but will rather get it from a variable only set by the set_phase function.

This will cause issue when the client driver will never call the set_phase function, where we can end up having a reported phase that will not match what the hardware has been programmed to by the bootloader or what phase is programmed out of reset.

Add a new get_phase function for the drivers to implement so that we can get this value.

Signed-off-by Maxime Ripard <[email protected]>

---
 drivers/clk/clk.c            | 10 ++++++++++
 include/linux/clk-provider.h |  5 +++++
 2 files changed, 15 insertions(+)

drivers/clk/clk.c +0 -0

index d87661af0c72..113d75db371d 100644
@@ -1934,6 +1934,16 @@ int __clk_init(struct device *dev, struct clk *clk)
                clk->accuracy = 0;

drivers/clk/clk.c int __clk_init(struct device *dev, struct clk *clk) · line 1944

Quoted 10 lines

drivers/clk/clk.c +8 -0

 
        /*
+        * Set clk's phase.
+        * Since a phase is by definition relative to its parent, just
+        * query the current clock phase, or just assume it's in phase.
+        */
+       if (clk->ops->get_phase)
+               clk->phase = clk->ops->get_phase(clk->hw);
+       else
+               clk->phase = 0;

I probably wasn't paying enough attention to this. Based on the coverletter I thought that v3 would introduce something like CLK_GET_PHASE_NOCACHE and stuff that logic into a __clk_get_phase function? Looks like this version of the series doesn't handle phases that can be changed by hardware (e.g. coming out of idle).

Quoted 3 lines

Correct me if I am wrong, but it looks like we retrieve the phase only once at init and then never again? The rest of the time we rely on clk->phase to always be accurate...

Yeah, I didn't have any use for it at the moment, and thought that if someone ever needed it, it would be trivial to add, so I left it out.

If you want me to still do it, I can send an additional patch.

Thanks!
Maxime

Signature · 3 lines

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Add the sample and output clocks for the MMC phase support.

Signed-off-by Maxime Ripard <[email protected]>

---
 arch/arm/boot/dts/sun4i-a10.dtsi  | 104 +++++++++++++++++++++++++++++++++++---
 arch/arm/boot/dts/sun5i-a10s.dtsi |  79 ++++++++++++++++++++++++++---
 arch/arm/boot/dts/sun5i-a13.dtsi  |  80 +++++++++++++++++++++++++----
 arch/arm/boot/dts/sun6i-a31.dtsi  | 104 +++++++++++++++++++++++++++++++++++---
 arch/arm/boot/dts/sun7i-a20.dtsi  | 104 +++++++++++++++++++++++++++++++++++---
 arch/arm/boot/dts/sun8i-a23.dtsi  |  78 +++++++++++++++++++++++++---

 6 files changed, 502 insertions(+), 47 deletions(-)

arch/arm/boot/dts/sun4i-a10.dtsi +64 -0

index 380f914b226d..57ca74a149eb 100644
@@ -227,6 +227,22 @@
                        clock-output-names = "mmc0";
                };
 
+               mmc0_output_clk: mmc_output_clk at 01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_output";
+               };
+
+               mmc0_sample_clk: mmc_sample_clk at 01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_sample";
+               };
+
                mmc1_clk: clk at 01c2008c {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -235,6 +251,22 @@
                        clock-output-names = "mmc1";
                };
 
+               mmc1_output_clk: mmc_output_clk at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_output";
+               };
+
+               mmc1_sample_clk: mmc_sample_clk at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_sample";
+               };
+
                mmc2_clk: clk at 01c20090 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -243,6 +275,22 @@
                        clock-output-names = "mmc2";
                };
 
+               mmc2_output_clk: mmc_output_clk at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_output";
+               };
+
+               mmc2_sample_clk: mmc_sample_clk at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_sample";
+               };
+
                mmc3_clk: clk at 01c20094 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -251,6 +299,22 @@
                        clock-output-names = "mmc3";
                };
 
+               mmc3_output_clk: mmc_output_clk at 01c20094 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20094 0x4>;
+                       clocks = <&mmc3_clk>;
+                       clock-output-names = "mmc3_output";
+               };
+
+               mmc3_sample_clk: mmc_sample_clk at 01c20094 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20094 0x4>;
+                       clocks = <&mmc3_clk>;
+                       clock-output-names = "mmc3_sample";
+               };
+
                ts_clk: clk at 01c20098 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -392,8 +456,14 @@
                mmc0: mmc at 01c0f000 {
                        compatible = "allwinner,sun4i-a10-mmc";
                        reg = <0x01c0f000 0x1000>;

arch/arm/boot/dts/sun4i-a10.dtsi +24 -6

                        interrupts = <32>;
                        status = "disabled";
                };

@@ -401,8 +471,14 @@
                mmc1: mmc at 01c10000 {
                        compatible = "allwinner,sun4i-a10-mmc";
                        reg = <0x01c10000 0x1000>;
-                       clocks = <&ahb_gates 9>, <&mmc1_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 9>,
+                                <&mmc1_clk>,
+                                <&mmc1_sample_clk>,
+                                <&mmc1_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <33>;
                        status = "disabled";
                };

@@ -410,8 +486,14 @@
                mmc2: mmc at 01c11000 {
                        compatible = "allwinner,sun4i-a10-mmc";
                        reg = <0x01c11000 0x1000>;
-                       clocks = <&ahb_gates 10>, <&mmc2_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 10>,
+                                <&mmc2_clk>,
+                                <&mmc2_sample_clk>,
+                                <&mmc2_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <34>;
                        status = "disabled";
                };

@@ -419,8 +501,14 @@
                mmc3: mmc at 01c12000 {
                        compatible = "allwinner,sun4i-a10-mmc";
                        reg = <0x01c12000 0x1000>;
-                       clocks = <&ahb_gates 11>, <&mmc3_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 11>,
+                                <&mmc3_clk>,
+                                <&mmc3_sample_clk>,
+                                <&mmc3_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <35>;
                        status = "disabled";
                };

arch/arm/boot/dts/sun5i-a10s.dtsi +72 -7

index 531272c0e526..59c93287fd66 100644
@@ -212,6 +212,22 @@
                        clock-output-names = "mmc0";
                };
 
+               mmc0_output_clk: mmc_output_clk at 01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_output";
+               };
+
+               mmc0_sample_clk: mmc_sample_clk at 01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_sample";
+               };
+
                mmc1_clk: clk at 01c2008c {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -220,6 +236,22 @@
                        clock-output-names = "mmc1";
                };
 
+               mmc1_output_clk: mmc_output_clk at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_output";
+               };
+
+               mmc1_sample_clk: mmc_sample_clk at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_sample";
+               };
+
                mmc2_clk: clk at 01c20090 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -228,6 +260,22 @@
                        clock-output-names = "mmc2";
                };
 
+               mmc2_output_clk: mmc_output_clk at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_output";
+               };
+
+               mmc2_sample_clk: mmc_sample_clk at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_sample";
+               };
+
                ts_clk: clk at 01c20098 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -353,8 +401,14 @@
                mmc0: mmc at 01c0f000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c0f000 0x1000>;
-                       clocks = <&ahb_gates 8>, <&mmc0_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 8>,
+                                <&mmc0_clk>,
+                                <&mmc0_sample_clk>,
+                                <&mmc0_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <32>;
                        status = "disabled";
                };

@@ -362,8 +416,14 @@
                mmc1: mmc at 01c10000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c10000 0x1000>;
-                       clocks = <&ahb_gates 9>, <&mmc1_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 9>,
+                                <&mmc1_clk>,
+                                <&mmc1_sample_clk>,
+                                <&mmc1_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <33>;
                        status = "disabled";
                };

@@ -371,12 +431,17 @@
                mmc2: mmc at 01c11000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c11000 0x1000>;
-                       clocks = <&ahb_gates 10>, <&mmc2_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 10>,
+                                <&mmc2_clk>,
+                                <&mmc2_sample_clk>,
+                                <&mmc2_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <34>;
                        status = "disabled";
                };
-
                usbphy: phy at 01c13400 {
                        #phy-cells = <1>;
                        compatible = "allwinner,sun5i-a13-usb-phy";

arch/arm/boot/dts/sun5i-a13.dtsi +70 -10

index b131068f4f35..2c5cee912f33 100644
@@ -202,30 +202,78 @@
                        clock-output-names = "ms";
                };
 
-               mmc0_clk: clk at 01c20088 {
+               mmc0_clk: clk_mmc at 01c20088 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mmc-clk";
                        reg = <0x01c20088 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc0";
                };
 
-               mmc1_clk: clk at 01c2008c {
+               mmc0_output_clk: mmc_output_clk at 01c20088 {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_output";
+               };
+
+               mmc0_sample_clk: mmc_sample_clk at 01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_sample";
+               };
+
+               mmc1_clk: clk_mmc at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-clk";
                        reg = <0x01c2008c 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc1";
                };
 
-               mmc2_clk: clk at 01c20090 {
+               mmc1_output_clk: mmc_output_clk at 01c2008c {
                        #clock-cells = <0>;
-                       compatible = "allwinner,sun4i-a10-mod0-clk";
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_output";
+               };
+
+               mmc1_sample_clk: mmc_sample_clk at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_sample";
+               };
+
+               mmc2_clk: clk_mmc at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-clk";
                        reg = <0x01c20090 0x4>;
                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
                        clock-output-names = "mmc2";
                };
 
+               mmc2_output_clk: mmc_output_clk at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_output";
+               };
+
+               mmc2_sample_clk: mmc_sample_clk at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_sample";
+               };
+
                ts_clk: clk at 01c20098 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -335,8 +383,14 @@
                mmc0: mmc at 01c0f000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c0f000 0x1000>;
-                       clocks = <&ahb_gates 8>, <&mmc0_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 8>,
+                                <&mmc0_clk>,
+                                <&mmc0_sample_clk>,
+                                <&mmc0_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <32>;
                        status = "disabled";
                };

@@ -344,8 +398,14 @@
                mmc2: mmc at 01c11000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c11000 0x1000>;
-                       clocks = <&ahb_gates 10>, <&mmc2_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 10>,
+                                <&mmc2_clk>,
+                                <&mmc2_sample_clk>,
+                                <&mmc2_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <34>;
                        status = "disabled";
                };

arch/arm/boot/dts/sun6i-a31.dtsi +96 -8

index 543f895d18d3..436eb7429a7d 100644
@@ -252,6 +252,22 @@
                        clock-output-names = "mmc0";
                };
 
+               mmc0_output_clk: mmc_output_clk at 01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_output";
+               };
+
+               mmc0_sample_clk: mmc_sample_clk at 01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_sample";
+               };
+
                mmc1_clk: clk at 01c2008c {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -260,6 +276,22 @@
                        clock-output-names = "mmc1";
                };
 
+               mmc1_output_clk: mmc_output_clk at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_output";
+               };
+
+               mmc1_sample_clk: mmc_sample_clk at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_sample";
+               };
+
                mmc2_clk: clk at 01c20090 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -268,6 +300,22 @@
                        clock-output-names = "mmc2";
                };
 
+               mmc2_output_clk: mmc_output_clk at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_output";
+               };
+
+               mmc2_sample_clk: mmc_sample_clk at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_sample";
+               };
+
                mmc3_clk: clk at 01c20094 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -276,6 +324,22 @@
                        clock-output-names = "mmc3";
                };
 
+               mmc3_output_clk: mmc_output_clk at 01c20094 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20094 0x4>;
+                       clocks = <&mmc3_clk>;
+                       clock-output-names = "mmc3_output";
+               };
+
+               mmc3_sample_clk: mmc_sample_clk at 01c20094 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20094 0x4>;
+                       clocks = <&mmc3_clk>;
+                       clock-output-names = "mmc3_sample";
+               };
+
                spi0_clk: clk at 01c200a0 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -366,8 +430,14 @@
                mmc0: mmc at 01c0f000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c0f000 0x1000>;
-                       clocks = <&ahb1_gates 8>, <&mmc0_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb1_gates 8>,
+                                <&mmc0_clk>,
+                                <&mmc0_sample_clk>,
+                                <&mmc0_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        resets = <&ahb1_rst 8>;
                        reset-names = "ahb";
                        interrupts = <0 60 4>;

@@ -377,8 +447,14 @@
                mmc1: mmc at 01c10000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c10000 0x1000>;
-                       clocks = <&ahb1_gates 9>, <&mmc1_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb1_gates 9>,
+                                <&mmc1_clk>,
+                                <&mmc1_sample_clk>,
+                                <&mmc1_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        resets = <&ahb1_rst 9>;
                        reset-names = "ahb";
                        interrupts = <0 61 4>;

@@ -388,8 +464,14 @@
                mmc2: mmc at 01c11000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c11000 0x1000>;
-                       clocks = <&ahb1_gates 10>, <&mmc2_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb1_gates 10>,
+                                <&mmc2_clk>,
+                                <&mmc2_sample_clk>,
+                                <&mmc2_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        resets = <&ahb1_rst 10>;
                        reset-names = "ahb";
                        interrupts = <0 62 4>;

@@ -399,8 +481,14 @@
                mmc3: mmc at 01c12000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c12000 0x1000>;
-                       clocks = <&ahb1_gates 11>, <&mmc3_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb1_gates 11>,
+                                <&mmc3_clk>,
+                                <&mmc3_sample_clk>,
+                                <&mmc3_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        resets = <&ahb1_rst 11>;
                        reset-names = "ahb";
                        interrupts = <0 63 4>;

arch/arm/boot/dts/sun7i-a20.dtsi +96 -8

index 82097c905c48..aa61f4887a5e 100644
@@ -275,6 +275,22 @@
                        clock-output-names = "mmc0";
                };
 
+               mmc0_output_clk: mmc_output_clk at 01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_output";
+               };
+
+               mmc0_sample_clk: mmc_sample_clk at 01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_sample";
+               };
+
                mmc1_clk: clk at 01c2008c {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -283,6 +299,22 @@
                        clock-output-names = "mmc1";
                };
 
+               mmc1_output_clk: mmc_output_clk at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_output";
+               };
+
+               mmc1_sample_clk: mmc_sample_clk at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_sample";
+               };
+
                mmc2_clk: clk at 01c20090 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -291,6 +323,22 @@
                        clock-output-names = "mmc2";
                };
 
+               mmc2_output_clk: mmc_output_clk at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_output";
+               };
+
+               mmc2_sample_clk: mmc_sample_clk at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_sample";
+               };
+
                mmc3_clk: clk at 01c20094 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -299,6 +347,22 @@
                        clock-output-names = "mmc3";
                };
 
+               mmc3_output_clk: mmc_output_clk at 01c20094 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20094 0x4>;
+                       clocks = <&mmc3_clk>;
+                       clock-output-names = "mmc3_output";
+               };
+
+               mmc3_sample_clk: mmc_sample_clk at 01c20094 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20094 0x4>;
+                       clocks = <&mmc3_clk>;
+                       clock-output-names = "mmc3_sample";
+               };
+
                ts_clk: clk at 01c20098 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -512,8 +576,14 @@
                mmc0: mmc at 01c0f000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c0f000 0x1000>;
-                       clocks = <&ahb_gates 8>, <&mmc0_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 8>,
+                                <&mmc0_clk>,
+                                <&mmc0_sample_clk>,
+                                <&mmc0_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <0 32 4>;
                        status = "disabled";
                };

@@ -521,8 +591,14 @@
                mmc1: mmc at 01c10000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c10000 0x1000>;
-                       clocks = <&ahb_gates 9>, <&mmc1_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 9>,
+                                <&mmc1_clk>,
+                                <&mmc1_sample_clk>,
+                                <&mmc1_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <0 33 4>;
                        status = "disabled";
                };

@@ -530,8 +606,14 @@
                mmc2: mmc at 01c11000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c11000 0x1000>;
-                       clocks = <&ahb_gates 10>, <&mmc2_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 10>,
+                                <&mmc2_clk>,
+                                <&mmc2_sample_clk>,
+                                <&mmc2_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <0 34 4>;
                        status = "disabled";
                };

@@ -539,8 +621,14 @@
                mmc3: mmc at 01c12000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c12000 0x1000>;
-                       clocks = <&ahb_gates 11>, <&mmc3_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 11>,
+                                <&mmc3_clk>,
+                                <&mmc3_sample_clk>,
+                                <&mmc3_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        interrupts = <0 35 4>;
                        status = "disabled";
                };

arch/arm/boot/dts/sun8i-a23.dtsi +72 -7

index a35039224cb5..4379ae93b217 100644
@@ -224,6 +224,22 @@
                        clock-output-names = "mmc0";
                };
 
+               mmc0_output_clk: mmc_output_clk at 01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_output";
+               };
+
+               mmc0_sample_clk: mmc_sample_clk at 01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&mmc0_clk>;
+                       clock-output-names = "mmc0_sample";
+               };
+
                mmc1_clk: clk at 01c2008c {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -232,6 +248,22 @@
                        clock-output-names = "mmc1";
                };
 
+               mmc1_output_clk: mmc_output_clk at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_output";
+               };
+
+               mmc1_sample_clk: mmc_sample_clk at 01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&mmc1_clk>;
+                       clock-output-names = "mmc1_sample";
+               };
+
                mmc2_clk: clk at 01c20090 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";

@@ -239,6 +271,22 @@
                        clocks = <&osc24M>, <&pll6>;
                        clock-output-names = "mmc2";
                };
+
+               mmc2_output_clk: mmc_output_clk at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-output-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_output";
+               };
+
+               mmc2_sample_clk: mmc_sample_clk at 01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-mmc-sample-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&mmc2_clk>;
+                       clock-output-names = "mmc2_sample";
+               };
        };
 
        soc at 01c00000 {

@@ -250,8 +298,14 @@
                mmc0: mmc at 01c0f000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c0f000 0x1000>;
-                       clocks = <&ahb1_gates 8>, <&mmc0_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb1_gates 8>,
+                                <&mmc0_clk>,
+                                <&mmc0_sample_clk>,
+                                <&mmc0_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        resets = <&ahb1_rst 8>;
                        reset-names = "ahb";
                        interrupts = <0 60 4>;

@@ -261,8 +315,14 @@
                mmc1: mmc at 01c10000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c10000 0x1000>;
-                       clocks = <&ahb1_gates 9>, <&mmc1_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb1_gates 9>,
+                                <&mmc1_clk>,
+                                <&mmc1_sample_clk>,
+                                <&mmc1_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        resets = <&ahb1_rst 9>;
                        reset-names = "ahb";
                        interrupts = <0 61 4>;

@@ -272,8 +332,14 @@
                mmc2: mmc at 01c11000 {
                        compatible = "allwinner,sun5i-a13-mmc";
                        reg = <0x01c11000 0x1000>;
-                       clocks = <&ahb1_gates 10>, <&mmc2_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb1_gates 10>,
+                                <&mmc2_clk>,
+                                <&mmc2_sample_clk>,
+                                <&mmc2_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";
                        resets = <&ahb1_rst 10>;
                        reset-names = "ahb";
                        interrupts = <0 62 4>;
--

2.1.0

arch/arm/boot/dts/sun4i-a10.dtsi line 466

Quoted 13 lines

                mmc0: mmc at 01c0f000 {
                        compatible = "allwinner,sun4i-a10-mmc";
                        reg = <0x01c0f000 0x1000>;

arch/arm/boot/dts/sun4i-a10.dtsi +8 -2

-                       clocks = <&ahb_gates 8>, <&mmc0_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 8>,
+                                <&mmc0_clk>,
+                                <&mmc0_sample_clk>,
+                                <&mmc0_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";

Just a stylish nitpick. All the other resources in these files are listed inline if possible, not one phandle/value per line.

Quoted 14 lines · Chen-Yu Tsai

Quoted 13 lines

                mmc0: mmc at 01c0f000 {
                        compatible = "allwinner,sun4i-a10-mmc";
                        reg = <0x01c0f000 0x1000>;

arch/arm/boot/dts/sun4i-a10.dtsi +8 -2

-                       clocks = <&ahb_gates 8>, <&mmc0_clk>;
-                       clock-names = "ahb", "mmc";
+                       clocks = <&ahb_gates 8>,
+                                <&mmc0_clk>,
+                                <&mmc0_sample_clk>,
+                                <&mmc0_output_clk>;
+                       clock-names = "ahb",
+                                     "mmc",
+                                     "sample",
+                                     "output";

Quoted 2 lines

Just a stylish nitpick. All the other resources in these files are listed inline if possible, not one phandle/value per line.

Look at the PIO interrupts, every USB PHY resources, etc. ;)

Hello

drivers/mmc/host/sunxi-mmc.c static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, · line 648

Quoted 10 lines

Now that we have proper support to use the generic phase API in our clock driver, switch the MMC driver to use it.
[...]

drivers/mmc/host/sunxi-mmc.c +2 -2

 	/* determine delays */
 	if (rate <= 400000) {
-		oclk_dly = 0;
-		sclk_dly = 7;
+		oclk_dly = 180;
+		sclk_dly = 42;
[...]

How did you calculate the actual phase values from the original parameters?

Quoted 3 lines

Quoted 1 line

[...]

How did you calculate the actual phase values from the original parameters?

Like shown in the clock driver. 0 is always a 180 deg phase shift, and any other value is the number of the parent clock cycle to outphase the clock of.

the clock out phase is calculating using:

phase = 360 * interval / period.

with period = 1 / (parent_freq / divider)
and interval = reg / parent_freq

which makes

phase = 360 * (reg / parent_freq) * (parent_freq / divider)

If we simplify by removing the parent_freq, we end up with

phase = 360 * reg / divider, which makes it rather trivial to calculate.

Maxime

Hi everyone,

Here is an attempt at improving the MMC clock support in the Allwinner SoCs.

Until now, the MMC clocks were having a custom phase function that was directly setting an obscure value in the right register, because we were not really having any idea of what these values were.

Now that we have more informations, we can introduce a common function call to get and set the phase of a particular clock, and use this in both our provider and our client.

Thanks,
Maxime

Hi everyone,

Here is an attempt at improving the MMC clock support in the Allwinner SoCs.

Until now, the MMC clocks were having a custom phase function that was directly setting an obscure value in the right register, because we were not really having any idea of what these values were.

Now that we have more informations, we can introduce a common function call to get and set the phase of a particular clock, and use this in both our provider and our client.

Mike,

Quoted 9 lines · Maxime Ripard

Hi everyone,

Here is an attempt at improving the MMC clock support in the Allwinner SoCs.

Until now, the MMC clocks were having a custom phase function that was directly setting an obscure value in the right register, because we were not really having any idea of what these values were.

Quoted 3 lines

Now that we have more informations, we can introduce a common function call to get and set the phase of a particular clock, and use this in both our provider and our client.

It would be great that we have that custom phase API out of the kernel for 3.18, and you were one of the greatest supporters to that idea, could we please have your view on this?

Thanks,
Maxime

Signature · 3 lines

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Quoting Maxime Ripard (2014-09-22 04:31:33)

Quoted 16 lines

Mike,

Quoted 12 lines · Maxime Ripard

Hi everyone,

Here is an attempt at improving the MMC clock support in the Allwinner SoCs.

Until now, the MMC clocks were having a custom phase function that was directly setting an obscure value in the right register, because we were not really having any idea of what these values were.

Now that we have more informations, we can introduce a common function call to get and set the phase of a particular clock, and use this in both our provider and our client.

Quoted 3 lines

It would be great that we have that custom phase API out of the kernel for 3.18, and you were one of the greatest supporters to that idea, could we please have your view on this?

Patches all look good to me. Did you want the whole series to go through the clk tree?

If so we'll need an Ack for the MMC patch and for the ARM DTS patches as well.

Hi Mike,

Quoted 17 lines · Mike Turquette

Quoting Maxime Ripard (2014-09-22 04:31:33)

Quoted 16 lines

Mike,

Quoted 12 lines · Maxime Ripard

Hi everyone,

Here is an attempt at improving the MMC clock support in the Allwinner SoCs.

Until now, the MMC clocks were having a custom phase function that was directly setting an obscure value in the right register, because we were not really having any idea of what these values were.

Now that we have more informations, we can introduce a common function call to get and set the phase of a particular clock, and use this in both our provider and our client.

Quoted 6 lines

Quoted 3 lines

It would be great that we have that custom phase API out of the kernel for 3.18, and you were one of the greatest supporters to that idea, could we please have your view on this?

Patches all look good to me. Did you want the whole series to go through the clk tree?

I guess it would be where it most make sense yes.

Quoted 2 lines

If so we'll need an Ack for the MMC patch and for the ARM DTS patches as well.

We already have an Ack from Ulf on the MMC patch, and I'm the maintainer of the DTS involved, so we should be ok :)

Thanks!
Maxime

Signature · 3 lines

Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com