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clk: rockchip: fix rk3368 cpuclk divider offsets

PATCH Applied Heiko Stübner 1 participant 2 messages Dec 1, 2015 – Dec 3, 2015

Subsystems (2)
Common clk Arm Rockchip
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Heiko Stübner

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#0 lore raw

PATCH 1/1 clk: rockchip: fix rk3368 cpuclk divider offsets

Due to a copy-paste error the the rk3368 cpuclk settings were acessing rk3288-specific register offsets. This never caused problems till now, as cpu frequency scaling in't used currently at all.

Reported-by Xing Zheng <[email protected]>
Signed-off-by Heiko Stuebner <[email protected]>

---
Posted for reference, as described above this doesn't cause any breakage, so can probably simply wait for 4.5

 drivers/clk/rockchip/clk-rk3368.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/clk/rockchip/clk-rk3368.c +2 -2
index 7e6b783..2ae9c57 100644
@@ -184,13 +184,13 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
 
 #define RK3368_CLKSEL0(_offs, _aclkm)					\
 	{								\
-		.reg = RK3288_CLKSEL_CON(0 + _offs),			\
+		.reg = RK3368_CLKSEL_CON(0 + _offs),			\
 		.val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK,	\
 				RK3368_DIV_ACLKM_SHIFT),		\
 	}
 #define RK3368_CLKSEL1(_offs, _atclk, _pdbg)				\
 	{								\
-		.reg = RK3288_CLKSEL_CON(1 + _offs),			\
+		.reg = RK3368_CLKSEL_CON(1 + _offs),			\
 		.val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK,	\
 				RK3368_DIV_ATCLK_SHIFT) |		\
 		       HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK,	\
Signature · 1 line
2.6.1
author maintainer Applied
#1 lore raw

Am Dienstag, 1. Dezember 2015, 22:31:56 schrieb Heiko St=FCbner:

Quoted 1 line

Due to a copy-paste error the the rk3368 cpuclk settings were acessin=

g

Quoted 1 line

rk3288-specific register offsets. This never caused problems till now=

,

Quoted 4 lines

as cpu frequency scaling in't used currently at all. =20

Reported-by Xing Zheng <[email protected]>
Signed-off-by Heiko Stuebner <[email protected]>

applied to my clock-branch for 4.5