exynos: add basic support for exynos5260 SoC
Subsystems (8)
v2 cover exynos: add basic support for exynos5260 SoC
Add basic support for exynos5260 SoC.
This series is based on linux-next, Kukjin's for-next and Mike's clk-for-linus-3.13 branches.
This patch is dependent on the following series from Tomasz Figa <[email protected]>:
http://www.spinics.net/lists/arm-kernel/msg280223.html
V2:
1) Move suspend resume handling to Exynos5410 Clock file.
2) Removed Unused Macros and Condition checks for Exynos5260.
3) Add spin lock to clock provider context.
4) Add clock provider context for Exynos5410.
5) Uniform implementation for callbacks for PLL2550xx.
6) Split Exynos5260 clock file patch to bring it under 100 Kb limit.
7) Replace aclk/pclk/hclk gates with combined gates.
8) Remove CLK_IGNORE_UNUSED flag for gate clocks.
9) Split up DT patch into SoC and Board patch.
Pankaj Dubey (2):
ARM: EXYNOS: initial board support for exynos5260 SoC clk/samsung: add support for pll2550xx
Rahul Sharma (7):
clk/exynos5410: Move suspend/resume handling to SoC driver clk/samsung: add support for multuple clock providers clk/samsung: add support for pll2650xx clk/exynos5260: add macros and documentation for exynos5260 clk/exynos5260: add clock file for exynos5260
ARM: dts: add dts files for exynos5260 SoC
ARM: dts: add dts files for xyref5260 board
Young-Gun Jang (1):
pinctrl: exynos: add exynos5260 SoC specific data
.../devicetree/bindings/clock/exynos5260-clock.txt | 299 +++ .../bindings/pinctrl/samsung-pinctrl.txt | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 572 ++++++ arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 105 + arch/arm/boot/dts/exynos5260.dtsi | 317 +++ arch/arm/mach-exynos/Kconfig | 9 + arch/arm/mach-exynos/common.c | 19 +- arch/arm/mach-exynos/include/mach/map.h | 1 + arch/arm/mach-exynos/mach-exynos5-dt.c | 1 + arch/arm/plat-samsung/include/plat/cpu.h | 8 + arch/arm/plat-samsung/include/plat/map-s5p.h | 1 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos4.c | 47 +- drivers/clk/samsung/clk-exynos5250.c | 26 +- drivers/clk/samsung/clk-exynos5260.c | 2062 ++++++++++++++++++++ drivers/clk/samsung/clk-exynos5260.h | 496 +++++ drivers/clk/samsung/clk-exynos5410.c | 59 +- drivers/clk/samsung/clk-exynos5420.c | 24 +- drivers/clk/samsung/clk-exynos5440.c | 18 +- drivers/clk/samsung/clk-pll.c | 223 ++- drivers/clk/samsung/clk-pll.h | 3 +- drivers/clk/samsung/clk-s3c64xx.c | 44 +- drivers/clk/samsung/clk.c | 115 +- drivers/clk/samsung/clk.h | 72 +- drivers/pinctrl/pinctrl-exynos.c | 82 + drivers/pinctrl/pinctrl-samsung.c | 2 + drivers/pinctrl/pinctrl-samsung.h | 1 + include/dt-bindings/clk/exynos5260-clk.h | 234 +++ 29 files changed, 4684 insertions(+), 159 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts create mode 100644 arch/arm/boot/dts/exynos5260.dtsi create mode 100644 drivers/clk/samsung/clk-exynos5260.c create mode 100644 drivers/clk/samsung/clk-exynos5260.h create mode 100644 include/dt-bindings/clk/exynos5260-clk.h
Signature · 1 line
1.7.9.5
PATCH v2 1/10 clk/exynos5410: move suspend/resume handling to SoC driver
Suspend/resume handling is already moved for all other Exynos SoCs other than Exynos5420 which is addressed in this patch.
Signed-off-by Rahul Sharma <[email protected]>
--- drivers/clk/samsung/clk-exynos5410.c | 49 ++++++++++++++++++++++++++++++---- 1 file changed, 44 insertions(+), 5 deletions(-)
drivers/clk/samsung/clk-exynos5410.c +44 -5
@@ -16,6 +16,7 @@#include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/syscore_ops.h> #include "clk.h"
@@ -60,6 +61,11 @@ enum exynos5410_plls { nr_plls /* number of PLLs */ }; +static void __iomem *reg_base; + +#ifdef CONFIG_PM_SLEEP +static struct samsung_clk_reg_dump *exynos5410_save; +/* * list of controller registers to be saved and restored during a * suspend/resume cycle.
@@ -89,6 +95,41 @@ static unsigned long exynos5410_clk_regs[] __initdata = { DIV_KFC0, }; +static int exynos5410_clk_suspend (void ) +{ +samsung_clk_save (reg_base, exynos5410_save, +ARRAY_SIZE (exynos5410_clk_regs)); + +return 0 ; +} + +static void exynos5410_clk_resume (void ) +{ +samsung_clk_restore (reg_base, exynos5410_save, +ARRAY_SIZE (exynos5410_clk_regs)); +} + +static struct syscore_ops exynos5410_clk_syscore_ops = { + .suspend = exynos5410_clk_suspend, + .resume = exynos5410_clk_resume, +}; + +static void exynos5410_clk_sleep_init (void ) +{ + exynos5410_save =samsung_clk_alloc_reg_dump (exynos5410_clk_regs, +ARRAY_SIZE (exynos5410_clk_regs)); +if (!exynos5410_save) { +pr_warn ("%s: failed to allocate sleep save data, no sleep support!\n" , + __func__); +return ; + } + +register_syscore_ops (&exynos5410_clk_syscore_ops); +} +#else +static void exynos5410_clk_sleep_init (void ) {} +#endif +/* list of all parent clocks */ PNAME (apll_p) = {"fin_pll" ,"fout_apll" , };PNAME (bpll_p) = {"fin_pll" ,"fout_bpll" , };
@@ -214,15 +255,11 @@ static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {/* register exynos5410 clocks */ static void __init exynos5410_clk_init (struct device_node *np) { -void __iomem *reg_base; - reg_base =of_iomap (np,0 );if (!reg_base)panic ("%s: failed to map registers\n" , __func__); -samsung_clk_init (np, reg_base,CLK_NR_CLKS , - exynos5410_clk_regs,ARRAY_SIZE (exynos5410_clk_regs), -NULL ,0 ); +samsung_clk_init (np, reg_base,CLK_NR_CLKS );samsung_clk_register_pll (exynos5410_plls,ARRAY_SIZE (exynos5410_plls), reg_base);
@@ -234,6 +271,8 @@ static void __init exynos5410_clk_init(struct device_node *np)samsung_clk_register_gate (exynos5410_gate_clks,ARRAY_SIZE (exynos5410_gate_clks)); +exynos5410_clk_sleep_init (); +pr_debug ("Exynos5410: clock setup completed.\n" ); }CLK_OF_DECLARE (exynos5410_clk,"samsung,exynos5410-clock" , exynos5410_clk_init);
Signature · 1 line
1.7.9.5
PATCH v2 1/10 clk/exynos5410: move suspend/resume handling to SoC driver
Quoted 7 lines · Rahul Sharma
Suspend/resume handling is already moved for all other Exynos SoCs other than Exynos5420 which is addressed in this patch.
Signed-off-by Rahul Sharma <[email protected]>--- drivers/clk/samsung/clk-exynos5410.c | 49 ++++++++++++++++++++++++++++++---- 1 file changed, 44 insertions(+), 5 deletions(-)
Acked-by Tomasz Figa <[email protected]>
Best regards,
Tomasz
PATCH v2 2/10 ARM: EXYNOS: initial board support for exynos5260 SoC
In reply to Rahul SharmaFrom: Pankaj Dubey <[email protected]>
This patch add basic arch side support for exynos5260 SoC.
Signed-off-by Pankaj Dubey <[email protected]>
Signed-off-by Arun Kumar K <[email protected]>
Signed-off-by Rahul Sharma <[email protected]>
--- arch/arm/mach-exynos/Kconfig | 9 +++++++++ arch/arm/mach-exynos/common.c | 19 ++++++++++++++++++- arch/arm/mach-exynos/include/mach/map.h | 1 + arch/arm/mach-exynos/mach-exynos5-dt.c | 1 + arch/arm/plat-samsung/include/plat/cpu.h | 8 ++++++++ arch/arm/plat-samsung/include/plat/map-s5p.h | 1 + 6 files changed, 38 insertions(+), 1 deletion(-)
arch/arm/mach-exynos/Kconfig +9 -0
@@ -101,6 +101,15 @@ config SOC_EXYNOS5410 help Enable EXYNOS5410 SoC support +config SOC_EXYNOS5260 + bool "SAMSUNG EXYNOS5260" + default y + depends on ARCH_EXYNOS5 + select AUTO_ZRELADDR + select SAMSUNG_DMADEV + help + Enable EXYNOS5260 SoC support + config SOC_EXYNOS5420 bool "SAMSUNG EXYNOS5420" default y
arch/arm/mach-exynos/common.c +18 -1
@@ -52,6 +52,7 @@ static const char name_exynos4210[] = "EXYNOS4210";static const char name_exynos4212[] ="EXYNOS4212" ;static const char name_exynos4412[] ="EXYNOS4412" ;static const char name_exynos5250[] ="EXYNOS5250" ; +static const char name_exynos5260[] ="EXYNOS5260" ;static const char name_exynos5410[] ="EXYNOS5410" ;static const char name_exynos5420[] ="EXYNOS5420" ;static const char name_exynos5440[] ="EXYNOS5440" ;
@@ -92,6 +93,12 @@ static struct cpu_table cpu_ids[] __initdata = { .init = exynos_init, .name = name_exynos5410, }, { + .idcode = EXYNOS5260_SOC_ID, + .idmask = EXYNOS5_SOC_MASK, + .map_io = exynos5_map_io, + .init = exynos_init, + .name = name_exynos5260, + }, { .idcode = EXYNOS5420_SOC_ID, .idmask = EXYNOS5_SOC_MASK, .map_io = exynos5_map_io,
@@ -279,6 +286,15 @@ static struct map_desc exynos5_iodesc[] __initdata = { }, }; +static struct map_desc exynos5260_iodesc[]__initdata = { + { + .virtual = (unsigned long )S5P_VA_SYSRAM_NS , + .pfn =__phys_to_pfn (EXYNOS5260_PA_SYSRAM_NS ), + .length =SZ_4K , + .type =MT_DEVICE , + }, +}; +void exynos4_restart (enum reboot_mode mode,const char *cmd) {__raw_writel (0x1 ,S5P_SWRESET );
@@ -387,9 +403,10 @@ static void __init exynos4_map_io(void)static void __init exynos5_map_io (void ) {iotable_init (exynos5_iodesc,ARRAY_SIZE (exynos5_iodesc)); -if (soc_is_exynos5250 ())iotable_init (exynos5250_iodesc,ARRAY_SIZE (exynos5250_iodesc)); +if (soc_is_exynos5260 ()) +iotable_init (exynos5260_iodesc,ARRAY_SIZE (exynos5260_iodesc));if (soc_is_exynos5410 ())iotable_init (exynos5410_iodesc,ARRAY_SIZE (exynos5410_iodesc)); }
arch/arm/mach-exynos/include/mach/map.h +1 -0
@@ -30,6 +30,7 @@#define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000#define EXYNOS5250_PA_SYSRAM_NS 0x0204F000#define EXYNOS5410_PA_SYSRAM_NS 0x02073000 +#define EXYNOS5260_PA_SYSRAM_NS 0x02073000#define EXYNOS_PA_CHIPID 0x10000000
arch/arm/mach-exynos/mach-exynos5-dt.c +1 -0
@@ -50,6 +50,7 @@ static void __init exynos5_dt_machine_init(void)static char const *exynos5_dt_compat[]__initdata = {"samsung,exynos5250" , +"samsung,exynos5260" ,"samsung,exynos5410" ,"samsung,exynos5420" ,"samsung,exynos5440" ,
arch/arm/plat-samsung/include/plat/cpu.h +8 -0
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;#define EXYNOS4_CPU_MASK 0xFFFE0000#define EXYNOS5250_SOC_ID 0x43520000 +#define EXYNOS5260_SOC_ID 0xE5260000#define EXYNOS5410_SOC_ID 0xE5410000#define EXYNOS5420_SOC_ID 0xE5420000#define EXYNOS5440_SOC_ID 0xE5440000
@@ -69,6 +70,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5260, EXYNOS5260_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)IS_SAMSUNG_CPU (exynos5440,EXYNOS5440_SOC_ID ,EXYNOS5_SOC_MASK )
@@ -156,6 +158,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)# define soc_is_exynos5410 () 0#endif +#if defined(CONFIG_SOC_EXYNOS5260 ) +# define soc_is_exynos5260 () is_samsung_exynos5260() +#else +# define soc_is_exynos5260 () 0 +#endif +#if defined(CONFIG_SOC_EXYNOS5420 )# define soc_is_exynos5420 () is_samsung_exynos5420()#else
arch/arm/plat-samsung/include/plat/map-s5p.h +1 -0
@@ -23,6 +23,7 @@#define S5P_VA_SYSRAM S3C_ADDR(0x02400000)#define S5P_VA_SYSRAM_NS S3C_ADDR(0x02410000) +#define S5P_VA_DMC0 S3C_ADDR(0x02440000)#define S5P_VA_DMC1 S3C_ADDR(0x02480000)#define S5P_VA_SROMC S3C_ADDR(0x024C0000)
Signature · 1 line
1.7.9.5
Arnd Bergmann
maintainerPATCH v2 2/10 ARM: EXYNOS: initial board support for exynos5260 SoC
Quoted 23 lines · On Tuesday 07 January 2014 18:29:00 Rahul Sharma wrote:
From: Pankaj Dubey <[email protected]>
This patch add basic arch side support for exynos5260 SoC.
Signed-off-by Pankaj Dubey <[email protected]>Signed-off-by Arun Kumar K <[email protected]>Signed-off-by Rahul Sharma <[email protected]>---
arch/arm/mach-exynos/common.c +1
-0@@ -52,6 +52,7 @@ static const char name_exynos4210[] = "EXYNOS4210";static const char name_exynos4212[] ="EXYNOS4212" ;static const char name_exynos4412[] ="EXYNOS4412" ;static const char name_exynos5250[] ="EXYNOS5250" ; +static const char name_exynos5260[] ="EXYNOS5260" ;static const char name_exynos5410[] ="EXYNOS5410" ;static const char name_exynos5420[] ="EXYNOS5420" ;static const char name_exynos5440[] ="EXYNOS5440" ;@@ -92,6 +93,12 @@ static struct cpu_table cpu_ids[] __initdata = { .init = exynos_init, .name = name_exynos5410,
arch/arm/mach-exynos/common.c static struct cpu_table cpu_ids[] __initdata = { · line 104
Quoted 10 lines
arch/arm/mach-exynos/common.c +6
-0}, { + .idcode = EXYNOS5260_SOC_ID, + .idmask = EXYNOS5_SOC_MASK, + .map_io = exynos5_map_io, + .init = exynos_init, + .name = name_exynos5260, + }, { .idcode = EXYNOS5420_SOC_ID, .idmask = EXYNOS5_SOC_MASK, .map_io = exynos5_map_io,
I think we've seen enough of these. Please generalize it enough so we won't need to add any more entries whenever a new SoC comes up. It's probably fine for now to have to tell the difference between EXYNOS4 and EXYNOS5, but not new chips within some family.
According to rumors on the web, EXYNOS6 is going to be released soon with a 64-bit CPU in it, and since we don't allow platform specific code for arm64 like this any more, you should just drop it for arm32 as well.
Quoted 6 lines
arch/arm/mach-exynos/common.c +2
-0@@ -279,6 +286,15 @@ static struct map_desc exynos5_iodesc[] __initdata = { }, }; +static struct map_desc exynos5260_iodesc[]__initdata = { + {
arch/arm/mach-exynos/common.c static struct map_desc exynos5_iodesc[] __initdata = { · line 300
Quoted 10 lines
arch/arm/mach-exynos/common.c +7
-0+ .virtual = (unsigned long)S5P_VA_SYSRAM_NS, + .pfn = __phys_to_pfn(EXYNOS5260_PA_SYSRAM_NS), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; +void exynos4_restart (enum reboot_mode mode,const char *cmd) {__raw_writel (0x1 ,S5P_SWRESET );
The only difference you have is the map descriptor, and that should go away if you only add a proper DT binding for SYSRAM. Try to get rid of the remaining map_desc entries while you're at it.
arch/arm/plat-samsung/include/plat/map-s5p.h line 29
Quoted 13 lines
arch/arm/plat-samsung/include/plat/map-s5p.h +1
-0@@ -23,6 +23,7 @@#define S5P_VA_SYSRAM S3C_ADDR(0x02400000)#define S5P_VA_SYSRAM_NS S3C_ADDR(0x02410000) +#define S5P_VA_DMC0 S3C_ADDR(0x02440000)#define S5P_VA_DMC1 S3C_ADDR(0x02480000)#define S5P_VA_SROMC S3C_ADDR(0x024C0000)
This hunk doesn't really belong in the patch at all.
Arnd
PATCH v2 2/10 ARM: EXYNOS: initial board support for exynos5260 SoC
Thanks Arnd,
Quoted 40 lines · Arnd Bergmann
Quoted 23 lines · On Tuesday 07 January 2014 18:29:00 Rahul Sharma wrote:
From: Pankaj Dubey <[email protected]>
This patch add basic arch side support for exynos5260 SoC.
Signed-off-by Pankaj Dubey <[email protected]>Signed-off-by Arun Kumar K <[email protected]>Signed-off-by Rahul Sharma <[email protected]>---
arch/arm/mach-exynos/common.c +1
-0@@ -52,6 +52,7 @@ static const char name_exynos4210[] = "EXYNOS4210";static const char name_exynos4212[] ="EXYNOS4212" ;static const char name_exynos4412[] ="EXYNOS4412" ;static const char name_exynos5250[] ="EXYNOS5250" ; +static const char name_exynos5260[] ="EXYNOS5260" ;static const char name_exynos5410[] ="EXYNOS5410" ;static const char name_exynos5420[] ="EXYNOS5420" ;static const char name_exynos5440[] ="EXYNOS5440" ;@@ -92,6 +93,12 @@ static struct cpu_table cpu_ids[] __initdata = { .init = exynos_init, .name = name_exynos5410,arch/arm/mach-exynos/common.c static struct cpu_table cpu_ids[] __initdata = { · line 104
Quoted 10 lines
arch/arm/mach-exynos/common.c +6
-0}, { + .idcode = EXYNOS5260_SOC_ID, + .idmask = EXYNOS5_SOC_MASK, + .map_io = exynos5_map_io, + .init = exynos_init, + .name = name_exynos5260, + }, { .idcode = EXYNOS5420_SOC_ID, .idmask = EXYNOS5_SOC_MASK, .map_io = exynos5_map_io,I think we've seen enough of these. Please generalize it enough so we won't need to add any more entries whenever a new SoC comes up. It's probably fine for now to have to tell the difference between EXYNOS4 and EXYNOS5, but not new chips within some family.
Quoted 4 lines
According to rumors on the web, EXYNOS6 is going to be released soon with a 64-bit CPU in it, and since we don't allow platform specific code for arm64 like this any more, you should just drop it for arm32 as well.
I agree with you. Let me explore options to optimize this part of the code. I prefer
to add code here (along with legacy ) to accept DT bindings for Exynos5 family SoCs and use them for Exynos5260. Next, I will migrate the rest of the existing platforms and get rid of existing platform code.
Quoted 5 lines
Quoted 5 lines
arch/arm/mach-exynos/common.c +0
-0@@ -279,6 +286,15 @@ static struct map_desc exynos5_iodesc[] __initdata = { }, };
Quoted 17 lines
arch/arm/mach-exynos/common.c static struct map_desc exynos5_iodesc[] __initdata = { · line 300
Quoted 12 lines
arch/arm/mach-exynos/common.c +9
-0+static struct map_desc exynos5260_iodesc[]__initdata = { + { + .virtual = (unsigned long )S5P_VA_SYSRAM_NS , + .pfn =__phys_to_pfn (EXYNOS5260_PA_SYSRAM_NS ), + .length =SZ_4K , + .type =MT_DEVICE , + }, +}; +void exynos4_restart (enum reboot_mode mode,const char *cmd) {__raw_writel (0x1 ,S5P_SWRESET );The only difference you have is the map descriptor, and that should go away if you only add a proper DT binding for SYSRAM. Try to get rid of the remaining
map_descentries while you're at it.
Ok. let me check this.
Quoted 6 lines
Quoted 6 lines
arch/arm/plat-samsung/include/plat/map-s5p.h +0
-0@@ -23,6 +23,7 @@
Quoted 9 lines
arch/arm/plat-samsung/include/plat/map-s5p.h line 29
Quoted 7 lines
arch/arm/plat-samsung/include/plat/map-s5p.h +1
-0#define S5P_VA_SYSRAM S3C_ADDR(0x02400000)#define S5P_VA_SYSRAM_NS S3C_ADDR(0x02410000) +#define S5P_VA_DMC0 S3C_ADDR(0x02440000)#define S5P_VA_DMC1 S3C_ADDR(0x02480000)#define S5P_VA_SROMC S3C_ADDR(0x024C0000)This hunk doesn't really belong in the patch at all.
I will move it to correct patch.
Regards,
Rahul Sharma
Quoted 2 lines
Arnd
PATCH v2 3/10 pinctrl: exynos: add exynos5260 SoC specific data
In reply to Rahul SharmaFrom: Young-Gun Jang <[email protected]>
Add Samsung Exynos5260 SoC specific data to enable pinctrl support for all platforms based on EXYNOS5260.
Signed-off-by Pankaj Dubey <[email protected]>
Signed-off-by Young-Gun Jang <[email protected]>
Signed-off-by Rahul Sharma <[email protected]>
Signed-off-by Arun Kumar K <[email protected]>
--- .../bindings/pinctrl/samsung-pinctrl.txt | 1 + drivers/pinctrl/pinctrl-exynos.c | 82 ++++++++++++++++++++ drivers/pinctrl/pinctrl-samsung.c | 2 + drivers/pinctrl/pinctrl-samsung.h | 1 + 4 files changed, 86 insertions(+)
Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +1 -0
@@ -16,6 +16,7 @@ Required Properties: - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller. - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. + - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller. - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. - reg: Base address of the pin controller hardware module and length of
drivers/pinctrl/pinctrl-exynos.c +82 -0
88 lines not on this page · raw message
drivers/pinctrl/pinctrl-samsung.c +2 -0
@@ -1120,6 +1120,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = (void *)exynos4x12_pin_ctrl }, { .compatible = "samsung,exynos5250-pinctrl", .data = (void *)exynos5250_pin_ctrl }, + { .compatible = "samsung,exynos5260-pinctrl", + .data = (void *)exynos5260_pin_ctrl }, { .compatible = "samsung,exynos5420-pinctrl", .data = (void *)exynos5420_pin_ctrl }, { .compatible = "samsung,s5pv210-pinctrl",
drivers/pinctrl/pinctrl-samsung.h +1 -0
@@ -254,6 +254,7 @@ struct samsung_pmx_func {extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];extern struct samsung_pin_ctrl exynos5250_pin_ctrl[]; +extern struct samsung_pin_ctrl exynos5260_pin_ctrl[];extern struct samsung_pin_ctrl exynos5420_pin_ctrl[];extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[];extern struct samsung_pin_ctrl s3c2412_pin_ctrl[];
Signature · 1 line
1.7.9.5
Arnd Bergmann
maintainerPATCH v2 3/10 pinctrl: exynos: add exynos5260 SoC specific data
Quoted 9 lines · On Tuesday 07 January 2014 18:29:01 Rahul Sharma wrote:
From: Young-Gun Jang <[email protected]>
Add Samsung Exynos5260 SoC specific data to enable pinctrl support for all platforms based on EXYNOS5260.
Signed-off-by Pankaj Dubey <[email protected]>Signed-off-by Young-Gun Jang <[email protected]>Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Arun Kumar K <[email protected]>
On a similar note to the comment about the platform patch, I think it would be good to extend the DT binding in a way that allows you to describe the differences between the SoCs without having to change the driver every time a new model comes out.
We still have to maintain backwards compatibility with the existing bindings I suppose, but I'd rather not see new ones added like this. I realize that there is a tradeoff between having too much information in DT when it is always fixed, and having too much hardcoded in the driver, and at some point there was a conscious decision to do it like this, but I fear the tradeoff has changed with the number of EXYNOS implementations that really only differ in their pin banks.
Arnd
PATCH v2 3/10 pinctrl: exynos: add exynos5260 SoC specific data
Quoted 16 lines · Arnd Bergmann
Quoted 9 lines · On Tuesday 07 January 2014 18:29:01 Rahul Sharma wrote:
From: Young-Gun Jang <[email protected]>
Add Samsung Exynos5260 SoC specific data to enable pinctrl support for all platforms based on EXYNOS5260.
Signed-off-by Pankaj Dubey <[email protected]>Signed-off-by Young-Gun Jang <[email protected]>Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Arun Kumar K <[email protected]>On a similar note to the comment about the platform patch, I think it would be good to extend the DT binding in a way that allows you to describe the differences between the SoCs without having to change the driver every time a new model comes out.
Quoted 8 lines
We still have to maintain backwards compatibility with the existing bindings I suppose, but I'd rather not see new ones added like this. I realize that there is a tradeoff between having too much information in DT when it is always fixed, and having too much hardcoded in the driver, and at some point there was a conscious decision to do it like this, but I fear the tradeoff has changed with the number of EXYNOS implementations that really only differ in their pin banks.
There isn't really too much data being added to the driver on per-SoC basis. Anyway, I remember that when I was trying to move all the data to DT long time ago when refactoring the driver, after a long discussion on the ML it was decided that it is not really a good idea and so we have the end result as we can see now.
Personally I'd prefer all the static data of struct samsung_pin_bank to be located in DT, with each bank having a compatible string that would translate to appropriate struct samsung_pin_bank_type, which is common across multiple SoCs (basically all >= S5PV210), and parameters such as pin-count, control-base, and geint-/weint-base (which would also imply interrupt type) - name (which is used only for human readable text) could be implied by node names. However that would mean quite significant effort (and churn), especially considering the fact that we need to maintain compatibility with existing bindings, due to "ABI stability" (which I'm slowly losing my faith in), so I don't think it's worth it.
So, from me:
Acked-by Tomasz Figa <[email protected]>
Best regards,
Tomasz
PATCH v2 4/10 clk/samsung: add support for multiple clock providers
In reply to Rahul SharmaSamsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer.
This layer is modified accordingly to enable the support.
Clock file for exynos4, exynos5250, exynos5420, exynos5440 and S3c64xx are also modified as per changed helper functions.
Signed-off-by Rahul Sharma <[email protected]>
--- drivers/clk/samsung/clk-exynos4.c | 47 +++++++------- drivers/clk/samsung/clk-exynos5250.c | 26 +++++--- drivers/clk/samsung/clk-exynos5410.c | 14 +++-- drivers/clk/samsung/clk-exynos5420.c | 24 ++++--- drivers/clk/samsung/clk-exynos5440.c | 18 +++--- drivers/clk/samsung/clk-pll.c | 14 +++-- drivers/clk/samsung/clk-s3c64xx.c | 44 +++++++------ drivers/clk/samsung/clk.c | 115 +++++++++++++++++++--------------- drivers/clk/samsung/clk.h | 72 ++++++++++++++------- 9 files changed, 220 insertions(+), 154 deletions(-)
drivers/clk/samsung/clk-exynos4.c +25 -22
@@ -1094,7 +1094,7 @@ static unsigned long exynos4_get_xom(void)return xom; } -static void __init exynos4_clk_register_finpll (void ) +static void __init exynos4_clk_register_finpll (struct samsung_clk_provider *ctx) {struct samsung_fixed_rate_clock fclk;struct clk *clk;
@@ -1117,7 +1117,7 @@ static void __init exynos4_clk_register_finpll(void) fclk.parent_name =NULL ; fclk.flags =CLK_IS_ROOT ; fclk.fixed_rate = finpll_f; -samsung_clk_register_fixed_rate (&fclk,1 ); +samsung_clk_register_fixed_rate (ctx, &fclk,1 ); }
@@ -1227,22 +1227,25 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {static void __init exynos4_clk_init (struct device_node *np,enum exynos4_soc soc) { +struct samsung_clk_provider *ctx; exynos4_soc = soc; reg_base =of_iomap (np,0 );if (!reg_base)panic ("%s: failed to map registers\n" , __func__); -samsung_clk_init (np, reg_base, nr_clks); + ctx =samsung_clk_init (np, reg_base, nr_clks); +if (!ctx) +panic ("%s: unable to allocate context.\n" , __func__); -samsung_clk_of_register_fixed_ext (exynos4_fixed_rate_ext_clks, +samsung_clk_of_register_fixed_ext (ctx, exynos4_fixed_rate_ext_clks,ARRAY_SIZE (exynos4_fixed_rate_ext_clks), ext_clk_match); -exynos4_clk_register_finpll (); +exynos4_clk_register_finpll (ctx);if (exynos4_soc ==EXYNOS4210 ) { -samsung_clk_register_mux (exynos4210_mux_early, +samsung_clk_register_mux (ctx, exynos4210_mux_early,ARRAY_SIZE (exynos4210_mux_early));if (_get_rate ("fin_pll" ) ==24000000 ) {
@@ -1256,7 +1259,7 @@ static void __init exynos4_clk_init(struct device_node *np, exynos4210_plls[vpll].rate_table = exynos4210_vpll_rates; -samsung_clk_register_pll (exynos4210_plls, +samsung_clk_register_pll (ctx, exynos4210_plls,ARRAY_SIZE (exynos4210_plls), reg_base); }else {if (_get_rate ("fin_pll" ) ==24000000 ) {
@@ -1268,42 +1271,42 @@ static void __init exynos4_clk_init(struct device_node *np, exynos4x12_vpll_rates; } -samsung_clk_register_pll (exynos4x12_plls, +samsung_clk_register_pll (ctx, exynos4x12_plls,ARRAY_SIZE (exynos4x12_plls), reg_base); } -samsung_clk_register_fixed_rate (exynos4_fixed_rate_clks, +samsung_clk_register_fixed_rate (ctx, exynos4_fixed_rate_clks,ARRAY_SIZE (exynos4_fixed_rate_clks)); -samsung_clk_register_mux (exynos4_mux_clks, +samsung_clk_register_mux (ctx, exynos4_mux_clks,ARRAY_SIZE (exynos4_mux_clks)); -samsung_clk_register_div (exynos4_div_clks, +samsung_clk_register_div (ctx, exynos4_div_clks,ARRAY_SIZE (exynos4_div_clks)); -samsung_clk_register_gate (exynos4_gate_clks, +samsung_clk_register_gate (ctx, exynos4_gate_clks,ARRAY_SIZE (exynos4_gate_clks));if (exynos4_soc ==EXYNOS4210 ) { -samsung_clk_register_fixed_rate (exynos4210_fixed_rate_clks, +samsung_clk_register_fixed_rate (ctx, exynos4210_fixed_rate_clks,ARRAY_SIZE (exynos4210_fixed_rate_clks)); -samsung_clk_register_mux (exynos4210_mux_clks, +samsung_clk_register_mux (ctx, exynos4210_mux_clks,ARRAY_SIZE (exynos4210_mux_clks)); -samsung_clk_register_div (exynos4210_div_clks, +samsung_clk_register_div (ctx, exynos4210_div_clks,ARRAY_SIZE (exynos4210_div_clks)); -samsung_clk_register_gate (exynos4210_gate_clks, +samsung_clk_register_gate (ctx, exynos4210_gate_clks,ARRAY_SIZE (exynos4210_gate_clks)); -samsung_clk_register_alias (exynos4210_aliases, +samsung_clk_register_alias (ctx, exynos4210_aliases,ARRAY_SIZE (exynos4210_aliases)); }else { -samsung_clk_register_mux (exynos4x12_mux_clks, +samsung_clk_register_mux (ctx, exynos4x12_mux_clks,ARRAY_SIZE (exynos4x12_mux_clks)); -samsung_clk_register_div (exynos4x12_div_clks, +samsung_clk_register_div (ctx, exynos4x12_div_clks,ARRAY_SIZE (exynos4x12_div_clks)); -samsung_clk_register_gate (exynos4x12_gate_clks, +samsung_clk_register_gate (ctx, exynos4x12_gate_clks,ARRAY_SIZE (exynos4x12_gate_clks)); -samsung_clk_register_alias (exynos4x12_aliases, +samsung_clk_register_alias (ctx, exynos4x12_aliases,ARRAY_SIZE (exynos4x12_aliases)); } -samsung_clk_register_alias (exynos4_aliases, +samsung_clk_register_alias (ctx, exynos4_aliases,ARRAY_SIZE (exynos4_aliases));exynos4_clk_sleep_init ();
drivers/clk/samsung/clk-exynos5250.c +16 -10
@@ -583,6 +583,8 @@ static struct of_device_id ext_clk_match[] __initdata = {/* register exynox5250 clocks */ static void __init exynos5250_clk_init (struct device_node *np) { +struct samsung_clk_provider *ctx; +if (np) { reg_base =of_iomap (np,0 );if (!reg_base)
@@ -591,11 +593,14 @@ static void __init exynos5250_clk_init(struct device_node *np)panic ("%s: unable to determine soc\n" , __func__); } -samsung_clk_init (np, reg_base, nr_clks); -samsung_clk_of_register_fixed_ext (exynos5250_fixed_rate_ext_clks, + ctx =samsung_clk_init (np, reg_base, nr_clks); +if (!ctx) +panic ("%s: unable to allocate context.\n" , __func__); + +samsung_clk_of_register_fixed_ext (ctx, exynos5250_fixed_rate_ext_clks,ARRAY_SIZE (exynos5250_fixed_rate_ext_clks), ext_clk_match); -samsung_clk_register_mux (exynos5250_pll_pmux_clks, +samsung_clk_register_mux (ctx, exynos5250_pll_pmux_clks,ARRAY_SIZE (exynos5250_pll_pmux_clks));if (_get_rate ("fin_pll" ) ==24 *MHZ )
@@ -604,17 +609,18 @@ static void __init exynos5250_clk_init(struct device_node *np)if (_get_rate ("mout_vpllsrc" ) ==24 *MHZ ) exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl; -samsung_clk_register_pll (exynos5250_plls,ARRAY_SIZE (exynos5250_plls), - reg_base); -samsung_clk_register_fixed_rate (exynos5250_fixed_rate_clks, +samsung_clk_register_pll (ctx, exynos5250_plls, +ARRAY_SIZE (exynos5250_plls), + reg_base); +samsung_clk_register_fixed_rate (ctx, exynos5250_fixed_rate_clks,ARRAY_SIZE (exynos5250_fixed_rate_clks)); -samsung_clk_register_fixed_factor (exynos5250_fixed_factor_clks, +samsung_clk_register_fixed_factor (ctx, exynos5250_fixed_factor_clks,ARRAY_SIZE (exynos5250_fixed_factor_clks)); -samsung_clk_register_mux (exynos5250_mux_clks, +samsung_clk_register_mux (ctx, exynos5250_mux_clks,ARRAY_SIZE (exynos5250_mux_clks)); -samsung_clk_register_div (exynos5250_div_clks, +samsung_clk_register_div (ctx, exynos5250_div_clks,ARRAY_SIZE (exynos5250_div_clks)); -samsung_clk_register_gate (exynos5250_gate_clks, +samsung_clk_register_gate (ctx, exynos5250_gate_clks,ARRAY_SIZE (exynos5250_gate_clks));exynos5250_clk_sleep_init ();
drivers/clk/samsung/clk-exynos5410.c +9 -5
@@ -255,20 +255,24 @@ static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {/* register exynos5410 clocks */ static void __init exynos5410_clk_init (struct device_node *np) { +struct samsung_clk_provider *ctx; + reg_base =of_iomap (np,0 );if (!reg_base)panic ("%s: failed to map registers\n" , __func__); -samsung_clk_init (np, reg_base,CLK_NR_CLKS ); + ctx =samsung_clk_init (np, reg_base,CLK_NR_CLKS ); +if (!ctx) +panic ("%s: unable to allocate context.\n" , __func__); -samsung_clk_register_pll (exynos5410_plls,ARRAY_SIZE (exynos5410_plls), +samsung_clk_register_pll (ctx, exynos5410_plls,ARRAY_SIZE (exynos5410_plls), reg_base); -samsung_clk_register_mux (exynos5410_mux_clks, +samsung_clk_register_mux (ctx, exynos5410_mux_clks,ARRAY_SIZE (exynos5410_mux_clks)); -samsung_clk_register_div (exynos5410_div_clks, +samsung_clk_register_div (ctx, exynos5410_div_clks,ARRAY_SIZE (exynos5410_div_clks)); -samsung_clk_register_gate (exynos5410_gate_clks, +samsung_clk_register_gate (ctx, exynos5410_gate_clks,ARRAY_SIZE (exynos5410_gate_clks));exynos5410_clk_sleep_init ();
drivers/clk/samsung/clk-exynos5420.c +15 -9
@@ -808,6 +808,8 @@ static struct of_device_id ext_clk_match[] __initdata = {/* register exynos5420 clocks */ static void __init exynos5420_clk_init (struct device_node *np) { +struct samsung_clk_provider *ctx; +if (np) { reg_base =of_iomap (np,0 );if (!reg_base)
@@ -816,21 +818,25 @@ static void __init exynos5420_clk_init(struct device_node *np)panic ("%s: unable to determine soc\n" , __func__); } -samsung_clk_init (np, reg_base, nr_clks); -samsung_clk_of_register_fixed_ext (exynos5420_fixed_rate_ext_clks, + ctx =samsung_clk_init (np, reg_base, nr_clks); +if (!ctx) +panic ("%s: unable to allocate context.\n" , __func__); + +samsung_clk_of_register_fixed_ext (ctx, exynos5420_fixed_rate_ext_clks,ARRAY_SIZE (exynos5420_fixed_rate_ext_clks), ext_clk_match); -samsung_clk_register_pll (exynos5420_plls,ARRAY_SIZE (exynos5420_plls), - reg_base); -samsung_clk_register_fixed_rate (exynos5420_fixed_rate_clks, +samsung_clk_register_pll (ctx, exynos5420_plls, +ARRAY_SIZE (exynos5420_plls), + reg_base); +samsung_clk_register_fixed_rate (ctx, exynos5420_fixed_rate_clks,ARRAY_SIZE (exynos5420_fixed_rate_clks)); -samsung_clk_register_fixed_factor (exynos5420_fixed_factor_clks, +samsung_clk_register_fixed_factor (ctx, exynos5420_fixed_factor_clks,ARRAY_SIZE (exynos5420_fixed_factor_clks)); -samsung_clk_register_mux (exynos5420_mux_clks, +samsung_clk_register_mux (ctx, exynos5420_mux_clks,ARRAY_SIZE (exynos5420_mux_clks)); -samsung_clk_register_div (exynos5420_div_clks, +samsung_clk_register_div (ctx, exynos5420_div_clks,ARRAY_SIZE (exynos5420_div_clks)); -samsung_clk_register_gate (exynos5420_gate_clks, +samsung_clk_register_gate (ctx, exynos5420_gate_clks,ARRAY_SIZE (exynos5420_gate_clks));exynos5420_clk_sleep_init ();
drivers/clk/samsung/clk-exynos5440.c +11 -7
@@ -106,6 +106,7 @@ static struct of_device_id ext_clk_match[] __initdata = {static void __init exynos5440_clk_init (struct device_node *np) {void __iomem *reg_base; +struct samsung_clk_provider *ctx; reg_base =of_iomap (np,0 );if (!reg_base) {
@@ -114,22 +115,25 @@ static void __init exynos5440_clk_init(struct device_node *np)return ; } -samsung_clk_init (np, reg_base, nr_clks); -samsung_clk_of_register_fixed_ext (exynos5440_fixed_rate_ext_clks, + ctx =samsung_clk_init (np, reg_base, nr_clks); +if (!ctx) +panic ("%s: unable to allocate context.\n" , __func__); + +samsung_clk_of_register_fixed_ext (ctx, exynos5440_fixed_rate_ext_clks,ARRAY_SIZE (exynos5440_fixed_rate_ext_clks), ext_clk_match);samsung_clk_register_pll2550x ("cplla" ,"xtal" , reg_base +0x1c ,0x10 );samsung_clk_register_pll2550x ("cpllb" ,"xtal" , reg_base +0x20 ,0x10 ); -samsung_clk_register_fixed_rate (exynos5440_fixed_rate_clks, +samsung_clk_register_fixed_rate (ctx, exynos5440_fixed_rate_clks,ARRAY_SIZE (exynos5440_fixed_rate_clks)); -samsung_clk_register_fixed_factor (exynos5440_fixed_factor_clks, +samsung_clk_register_fixed_factor (ctx, exynos5440_fixed_factor_clks,ARRAY_SIZE (exynos5440_fixed_factor_clks)); -samsung_clk_register_mux (exynos5440_mux_clks, +samsung_clk_register_mux (ctx, exynos5440_mux_clks,ARRAY_SIZE (exynos5440_mux_clks)); -samsung_clk_register_div (exynos5440_div_clks, +samsung_clk_register_div (ctx, exynos5440_div_clks,ARRAY_SIZE (exynos5440_div_clks)); -samsung_clk_register_gate (exynos5440_gate_clks, +samsung_clk_register_gate (ctx, exynos5440_gate_clks,ARRAY_SIZE (exynos5440_gate_clks));pr_info ("Exynos5440: arm_clk = %ldHz\n" ,_get_rate ("arm_clk" ));
drivers/clk/samsung/clk-pll.c +8 -6
@@ -710,8 +710,9 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name,return clk; } -static void __init _samsung_clk_register_pll (struct samsung_pll_clock *pll_clk, -void __iomem *base) +static void __init _samsung_clk_register_pll (struct samsung_clk_provider *ctx, +struct samsung_pll_clock *pll_clk, +void __iomem *base) {struct samsung_clk_pll *pll;struct clk *clk;
@@ -804,7 +805,7 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,return ; } -samsung_clk_add_lookup (clk, pll_clk->id); +samsung_clk_add_lookup (ctx, clk, pll_clk->id);if (!pll_clk->alias)return ;
@@ -815,11 +816,12 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk, __func__, pll_clk->name, ret); } -void __init samsung_clk_register_pll (struct samsung_pll_clock *pll_list, -unsigned int nr_pll,void __iomem *base) +void __init samsung_clk_register_pll (struct samsung_clk_provider *ctx, +struct samsung_pll_clock *pll_list, +unsigned int nr_pll,void __iomem *base) {int cnt;for (cnt =0 ; cnt < nr_pll; cnt++) -_samsung_clk_register_pll (&pll_list[cnt], base); +_samsung_clk_register_pll (ctx, &pll_list[cnt], base); }
drivers/clk/samsung/clk-s3c64xx.c +25 -19
91 lines not on this page · raw message
drivers/clk/samsung/clk.c +63 -52
246 lines not on this page · raw message
drivers/clk/samsung/clk.h +48 -24
94 lines not on this page · raw message
Signature · 1 line
1.7.9.5
PATCH v2 4/10 clk/samsung: add support for multiple clock providers
Hi Rahul,
The patch looks mostly fine now, but I still have one inline comment.
Quoted 9 lines · Rahul Sharma
Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer.
This layer is modified accordingly to enable the support.
Clock file for exynos4, exynos5250, exynos5420, exynos5440
[snip]
Quoted 13 lines
/* setup the essentials required to support clock lookup using ccf */
drivers/clk/samsung/clk.c +8
-3-void __init samsung_clk_init (struct device_node *np,void __iomem *base, -unsigned long nr_clks) +struct samsung_clk_provider *__init samsung_clk_init (struct device_node *np, +void __iomem *base,unsigned long nr_clks) { - reg_base = base; +struct samsung_clk_provider *ctx; +struct clk **clk_table; +int ret; + + ctx =kzalloc (sizeof (struct samsung_clk_provider ),GFP_KERNEL ); +if (!ctx)
drivers/clk/samsung/clk.c struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump( · line 69
Quoted 10 lines
drivers/clk/samsung/clk.c +5
-0+panic ("could not allocate clock provider context.\n" ); clk_table =kzalloc (sizeof (struct clk *) * nr_clks,GFP_KERNEL );if (!clk_table)panic ("could not allocate clock lookup table\n" ); + ctx->reg_base = base; + ctx->clk_data.clks = clk_table; + ctx->clk_data.clk_num = nr_clks; + ctx->lock =__SPIN_LOCK_UNLOCKED (lock);
spin_lock_init(&ctx->lock);
Best regards,
Tomasz
PATCH v2 5/10 clk/samsung: add support for pll2550xx
In reply to Rahul SharmaFrom: Pankaj Dubey <[email protected]>
exynos5260 use pll2550xx and it has different bit fields for P,M,S values as compared to pll2550. Support for pll2550xx is added here.
Signed-off-by Pankaj Dubey <[email protected]>
Signed-off-by Rahul Sharma <[email protected]>
Signed-off-by Arun Kumar K <[email protected]>
--- drivers/clk/samsung/clk-pll.c | 108 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 109 insertions(+)
drivers/clk/samsung/clk-pll.c +108 -0
@@ -710,6 +710,108 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name,return clk; } +/* +* PLL2550xx Clock Type +*/ + +/* Maximum lock time can be 270 * PDIV cycles */ +#define PLL2550XX_LOCK_FACTOR 270 + +#define PLL2550XX_M_MASK 0x3FF +#define PLL2550XX_P_MASK 0x3F +#define PLL2550XX_S_MASK 0x7 +#define PLL2550XX_LOCK_STAT_MASK 0x1 +#define PLL2550XX_M_SHIFT 9 +#define PLL2550XX_P_SHIFT 3 +#define PLL2550XX_S_SHIFT 0 +#define PLL2550XX_LOCK_STAT_SHIFT 21 + +static unsigned long samsung_pll2550xx_recalc_rate (struct clk_hw *hw, +unsigned long parent_rate) +{ +struct samsung_clk_pll *pll =to_clk_pll (hw); +u32 mdiv, pdiv, sdiv, pll_con; +u64 fvco = parent_rate; + + pll_con =__raw_readl (pll->con_reg); + mdiv = (pll_con >>PLL2550XX_M_SHIFT ) &PLL2550XX_M_MASK ; + pdiv = (pll_con >>PLL2550XX_P_SHIFT ) &PLL2550XX_P_MASK ; + sdiv = (pll_con >>PLL2550XX_S_SHIFT ) &PLL2550XX_S_MASK ; + + fvco *= mdiv; +do_div (fvco, (pdiv << sdiv)); + +return (unsigned long )fvco; +} + +static inline bool samsung_pll2550xx_mp_change (u32 mdiv,u32 pdiv,u32 pll_con) +{ +u32 old_mdiv, old_pdiv; + + old_mdiv = (pll_con >>PLL2550XX_M_SHIFT ) &PLL2550XX_M_MASK ; + old_pdiv = (pll_con >>PLL2550XX_P_SHIFT ) &PLL2550XX_P_MASK ; + +return mdiv != old_mdiv || pdiv != old_pdiv; +} + +static int samsung_pll2550xx_set_rate (struct clk_hw *hw,unsigned long drate, +unsigned long prate) +{ +struct samsung_clk_pll *pll =to_clk_pll (hw); +const struct samsung_pll_rate_table *rate; +u32 tmp; + +/* Get required rate settings from table */ + rate =samsung_get_pll_settings (pll, drate); +if (!rate) { +pr_err ("%s: Invalid rate : %lu for pll clk %s\n" , __func__, + drate,__clk_get_name (hw->clk)); +return -EINVAL ; + } + + tmp =__raw_readl (pll->con_reg); + +if (!(samsung_pll2550xx_mp_change (rate->mdiv, rate->pdiv, tmp))) { +/* If only s change, change just s value only*/ + tmp &= ~(PLL2550XX_S_MASK <<PLL2550XX_S_SHIFT ); + tmp |= rate->sdiv <<PLL2550XX_S_SHIFT ; +__raw_writel (tmp, pll->con_reg); + +return 0 ; + } + +/* Set PLL lock time. */ +__raw_writel (rate->pdiv *PLL2550XX_LOCK_FACTOR , pll->lock_reg); + +/* Change PLL PMS values */ + tmp &= ~((PLL2550XX_M_MASK <<PLL2550XX_M_SHIFT ) | + (PLL2550XX_P_MASK <<PLL2550XX_P_SHIFT ) | + (PLL2550XX_S_MASK <<PLL2550XX_S_SHIFT )); + tmp |= (rate->mdiv <<PLL2550XX_M_SHIFT ) | + (rate->pdiv <<PLL2550XX_P_SHIFT ) | + (rate->sdiv <<PLL2550XX_S_SHIFT ); +__raw_writel (tmp, pll->con_reg); + +/* wait_lock_time */ +do { +cpu_relax (); + tmp =__raw_readl (pll->con_reg); + }while (!(tmp & (PLL2550XX_LOCK_STAT_MASK + <<PLL2550XX_LOCK_STAT_SHIFT ))); + +return 0 ; +} + +static const struct clk_ops samsung_pll2550xx_clk_ops = { + .recalc_rate = samsung_pll2550xx_recalc_rate, + .round_rate = samsung_pll_round_rate, + .set_rate = samsung_pll2550xx_set_rate, +}; + +static const struct clk_ops samsung_pll2550xx_clk_min_ops = { + .recalc_rate = samsung_pll2550xx_recalc_rate, +}; +static void __init _samsung_clk_register_pll (struct samsung_clk_provider *ctx,struct samsung_pll_clock *pll_clk,void __iomem *base)
@@ -787,6 +889,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,else init.ops = &samsung_pll46xx_clk_ops;break ; +case pll_2550xx: +if (!pll->rate_table) + init.ops = &samsung_pll2550xx_clk_min_ops; +else + init.ops = &samsung_pll2550xx_clk_ops; +break ;default :pr_warn ("%s: Unknown pll type for pll clk %s\n" , __func__, pll_clk->name);
drivers/clk/samsung/clk-pll.h +1 -0
@@ -25,6 +25,7 @@ enum samsung_pll_type { pll_4650c, pll_6552, pll_6553, + pll_2550xx, };#define PLL_35XX_RATE (_rate, _m, _p, _s) \
Signature · 1 line
1.7.9.5
PATCH v2 5/10 clk/samsung: add support for pll2550xx
Quoted 6 lines · Rahul Sharma
From: Pankaj Dubey <[email protected]>
exynos5260 use pll2550xx and it has different bit fields for P,M,S values as compared to pll2550. Support for pll2550xx is added here.
Quoted 7 lines
Signed-off-by Pankaj Dubey <[email protected]>Signed-off-by Rahul Sharma <[email protected]>Signed-off-by Arun Kumar K <[email protected]>--- drivers/clk/samsung/clk-pll.c | 108 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 109 insertions(+)
Acked-by Tomasz Figa <[email protected]>
Best regards,
Tomasz
PATCH v2 6/10 clk/samsung: add support for pll2650xx
In reply to Rahul SharmaAdd support for pll2650xx in samsung pll file. This pll variant is close to pll36xx but uses CON2 registers instead of CON1.
Aud_pll in Exynos5260 is pll2650xx and uses this code.
Signed-off-by Rahul Sharma <[email protected]>
--- drivers/clk/samsung/clk-pll.c | 101 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 2 +- 2 files changed, 102 insertions(+), 1 deletion(-)
drivers/clk/samsung/clk-pll.c +101 -0
@@ -812,6 +812,101 @@ static const struct clk_ops samsung_pll2550xx_clk_min_ops = { .recalc_rate = samsung_pll2550xx_recalc_rate, }; +/* +* PLL2650XX Clock Type +*/ + +/* Maximum lock time can be 3000 * PDIV cycles */ +#define PLL2650XX_LOCK_FACTOR (3000) + +#define PLL2650XX_MDIV_SHIFT (9) +#define PLL2650XX_PDIV_SHIFT (3) +#define PLL2650XX_SDIV_SHIFT (0) +#define PLL2650XX_KDIV_SHIFT (0) +#define PLL2650XX_MDIV_MASK (0x1ff) +#define PLL2650XX_PDIV_MASK (0x3f) +#define PLL2650XX_SDIV_MASK (0x7) +#define PLL2650XX_KDIV_MASK (0xffff) +#define PLL2650XX_PLL_ENABLE_SHIFT (23) +#define PLL2650XX_PLL_LOCKTIME_SHIFT (21) +#define PLL2650XX_PLL_FOUTMASK_SHIFT (31) + +static unsigned long samsung_pll2650xx_recalc_rate (struct clk_hw *hw, +unsigned long parent_rate) +{ +struct samsung_clk_pll *pll =to_clk_pll (hw); +u32 mdiv, pdiv, sdiv, pll_con0, pll_con2; +s16 kdiv; +u64 fvco = parent_rate; + + pll_con0 =__raw_readl (pll->con_reg); + pll_con2 =__raw_readl (pll->con_reg +8 ); + mdiv = (pll_con0 >>PLL2650XX_MDIV_SHIFT ) &PLL2650XX_MDIV_MASK ; + pdiv = (pll_con0 >>PLL2650XX_PDIV_SHIFT ) &PLL2650XX_PDIV_MASK ; + sdiv = (pll_con0 >>PLL2650XX_SDIV_SHIFT ) &PLL2650XX_SDIV_MASK ; + kdiv = (s16)(pll_con2 &PLL2650XX_KDIV_MASK ); + + fvco *= (mdiv <<16 ) + kdiv; +do_div (fvco, (pdiv << sdiv)); + fvco >>=16 ; + +return (unsigned long )fvco; +} + +static int samsung_pll2650xx_set_rate (struct clk_hw *hw,unsigned long drate, +unsigned long parent_rate) +{ +struct samsung_clk_pll *pll =to_clk_pll (hw); +u32 tmp, pll_con0, pll_con2; +const struct samsung_pll_rate_table *rate; + + rate =samsung_get_pll_settings (pll, drate); +if (!rate) { +pr_err ("%s: Invalid rate : %lu for pll clk %s\n" , __func__, + drate,__clk_get_name (hw->clk)); +return -EINVAL ; + } + + pll_con0 =__raw_readl (pll->con_reg); + pll_con2 =__raw_readl (pll->con_reg +8 ); + +/* Change PLL PMS values */ + pll_con0 &= ~(PLL2650XX_MDIV_MASK <<PLL2650XX_MDIV_SHIFT | +PLL2650XX_PDIV_MASK <<PLL2650XX_PDIV_SHIFT | +PLL2650XX_SDIV_MASK <<PLL2650XX_SDIV_SHIFT ); + pll_con0 |= rate->mdiv <<PLL2650XX_MDIV_SHIFT ; + pll_con0 |= rate->pdiv <<PLL2650XX_PDIV_SHIFT ; + pll_con0 |= rate->sdiv <<PLL2650XX_SDIV_SHIFT ; + pll_con0 |=1 <<PLL2650XX_PLL_ENABLE_SHIFT ; + pll_con0 |=1 <<PLL2650XX_PLL_FOUTMASK_SHIFT ; + + pll_con2 &= ~(PLL2650XX_KDIV_MASK <<PLL2650XX_KDIV_SHIFT ); + pll_con2 |= ((~(rate->kdiv) +1 ) &PLL2650XX_KDIV_MASK ) + <<PLL2650XX_KDIV_SHIFT ; + +/* Set PLL lock time. */ +__raw_writel (PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); + +__raw_writel (pll_con0, pll->con_reg); +__raw_writel (pll_con2, pll->con_reg +8 ); + +do { + tmp =__raw_readl (pll->con_reg); + }while (!(tmp & (0x1 <<PLL2650XX_PLL_LOCKTIME_SHIFT ))); + +return 0 ; +} + +static const struct clk_ops samsung_pll2650xx_clk_ops = { + .recalc_rate = samsung_pll2650xx_recalc_rate, + .set_rate = samsung_pll2650xx_set_rate, + .round_rate = samsung_pll_round_rate, +}; + +static const struct clk_ops samsung_pll2650xx_clk_min_ops = { + .recalc_rate = samsung_pll2650xx_recalc_rate, +}; +static void __init _samsung_clk_register_pll (struct samsung_clk_provider *ctx,struct samsung_pll_clock *pll_clk,void __iomem *base)
@@ -895,6 +990,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,else init.ops = &samsung_pll2550xx_clk_ops;break ; +case pll_2650xx: +if (!pll->rate_table) + init.ops = &samsung_pll2650xx_clk_min_ops; +else + init.ops = &samsung_pll2650xx_clk_ops; +break ;default :pr_warn ("%s: Unknown pll type for pll clk %s\n" , __func__, pll_clk->name);
drivers/clk/samsung/clk-pll.h +1 -1
@@ -26,6 +26,7 @@ enum samsung_pll_type { pll_6552, pll_6553, pll_2550xx, + pll_2650xx, };#define PLL_35XX_RATE (_rate, _m, _p, _s) \
@@ -93,5 +94,4 @@ struct samsung_pll_rate_table {extern struct clk *__init samsung_clk_register_pll2550x (const char *name,const char *pname,const void __iomem *reg_base,const unsigned long offset); -#endif /* __SAMSUNG_CLK_PLL_H */
Signature · 1 line
1.7.9.5
PATCH v2 6/10 clk/samsung: add support for pll2650xx
Hi Rahul,
Quoted 27 lines · Rahul Sharma
Add support for pll2650xx in samsung pll file. This pll variant is close to pll36xx but uses CON2 registers instead of CON1.
Aud_pllin Exynos5260 is pll2650xx and uses this code.Signed-off-by Rahul Sharma <[email protected]>--- drivers/clk/samsung/clk-pll.c | 101 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 2 +- 2 files changed, 102 insertions(+), 1 deletion(-)drivers/clk/samsung/clk-pll.c +8
-0@@ -812,6 +812,101 @@ static const struct clk_ops samsung_pll2550xx_clk_min_ops = { .recalc_rate = samsung_pll2550xx_recalc_rate, }; +/* +* PLL2650XX Clock Type +*/ + +/* Maximum lock time can be 3000 * PDIV cycles */ +#define PLL2650XX_LOCK_FACTOR (3000) + +#define PLL2650XX_MDIV_SHIFT (9)
drivers/clk/samsung/clk-pll.c static const struct clk_ops samsung_pll2550xx_clk_min_ops = { · line 832
Quoted 10 lines
drivers/clk/samsung/clk-pll.c +10
-0+#define PLL2650XX_PDIV_SHIFT (3) +#define PLL2650XX_SDIV_SHIFT (0) +#define PLL2650XX_KDIV_SHIFT (0) +#define PLL2650XX_MDIV_MASK (0x1ff) +#define PLL2650XX_PDIV_MASK (0x3f) +#define PLL2650XX_SDIV_MASK (0x7) +#define PLL2650XX_KDIV_MASK (0xffff) +#define PLL2650XX_PLL_ENABLE_SHIFT (23) +#define PLL2650XX_PLL_LOCKTIME_SHIFT (21) +#define PLL2650XX_PLL_FOUTMASK_SHIFT (31)
For single bit fields it would be better to use simple definitions, using BIT() macro, such as
#define PLL2650XX_PLL_ENABLE BIT(23)
and then using it with | or & ~ operators directly.
Also there is no need for parentheses around simple integers.
Quoted 43 lines
drivers/clk/samsung/clk-pll.c +43
-0+ +static unsigned long samsung_pll2650xx_recalc_rate (struct clk_hw *hw, +unsigned long parent_rate) +{ +struct samsung_clk_pll *pll =to_clk_pll (hw); +u32 mdiv, pdiv, sdiv, pll_con0, pll_con2; +s16 kdiv; +u64 fvco = parent_rate; + + pll_con0 =__raw_readl (pll->con_reg); + pll_con2 =__raw_readl (pll->con_reg +8 ); + mdiv = (pll_con0 >>PLL2650XX_MDIV_SHIFT ) &PLL2650XX_MDIV_MASK ; + pdiv = (pll_con0 >>PLL2650XX_PDIV_SHIFT ) &PLL2650XX_PDIV_MASK ; + sdiv = (pll_con0 >>PLL2650XX_SDIV_SHIFT ) &PLL2650XX_SDIV_MASK ; + kdiv = (s16)(pll_con2 &PLL2650XX_KDIV_MASK ); + + fvco *= (mdiv <<16 ) + kdiv; +do_div (fvco, (pdiv << sdiv)); + fvco >>=16 ; + +return (unsigned long )fvco; +} + +static int samsung_pll2650xx_set_rate (struct clk_hw *hw,unsigned long drate, +unsigned long parent_rate) +{ +struct samsung_clk_pll *pll =to_clk_pll (hw); +u32 tmp, pll_con0, pll_con2; +const struct samsung_pll_rate_table *rate; + + rate =samsung_get_pll_settings (pll, drate); +if (!rate) { +pr_err ("%s: Invalid rate : %lu for pll clk %s\n" , __func__, + drate,__clk_get_name (hw->clk)); +return -EINVAL ; + } + + pll_con0 =__raw_readl (pll->con_reg); + pll_con2 =__raw_readl (pll->con_reg +8 ); + +/* Change PLL PMS values */ + pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT | + PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT |
drivers/clk/samsung/clk-pll.c static const struct clk_ops samsung_pll2550xx_clk_min_ops = { · line 885
Quoted 10 lines
drivers/clk/samsung/clk-pll.c +10
-0+ PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT); + pll_con0 |= rate->mdiv <<PLL2650XX_MDIV_SHIFT ; + pll_con0 |= rate->pdiv <<PLL2650XX_PDIV_SHIFT ; + pll_con0 |= rate->sdiv <<PLL2650XX_SDIV_SHIFT ; + pll_con0 |=1 <<PLL2650XX_PLL_ENABLE_SHIFT ; + pll_con0 |=1 <<PLL2650XX_PLL_FOUTMASK_SHIFT ; + + pll_con2 &= ~(PLL2650XX_KDIV_MASK <<PLL2650XX_KDIV_SHIFT ); + pll_con2 |= ((~(rate->kdiv) +1 ) &PLL2650XX_KDIV_MASK ) + <<PLL2650XX_KDIV_SHIFT ;
Huh? This looks suspiciously. Why KDIV needs to be negated and increased by 1?
drivers/clk/samsung/clk-pll.c static const struct clk_ops samsung_pll2550xx_clk_min_ops = { · line 895
Quoted 10 lines
drivers/clk/samsung/clk-pll.c +10
-0+ +/* Set PLL lock time. */ +__raw_writel (PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); + +__raw_writel (pll_con0, pll->con_reg); +__raw_writel (pll_con2, pll->con_reg +8 ); + +do { + tmp =__raw_readl (pll->con_reg); + }while (!(tmp & (0x1 <<PLL2650XX_PLL_LOCKTIME_SHIFT )));
Is the right bit being checked here? On other PLLs it's 29th bit named LOCK_STAT. Could you confirm this?
Quoted 43 lines
drivers/clk/samsung/clk-pll.c +20
-0+ +return 0 ; +} + +static const struct clk_ops samsung_pll2650xx_clk_ops = { + .recalc_rate = samsung_pll2650xx_recalc_rate, + .set_rate = samsung_pll2650xx_set_rate, + .round_rate = samsung_pll_round_rate, +}; + +static const struct clk_ops samsung_pll2650xx_clk_min_ops = { + .recalc_rate = samsung_pll2650xx_recalc_rate, +}; +static void __init _samsung_clk_register_pll (struct samsung_clk_provider *ctx,struct samsung_pll_clock *pll_clk,void __iomem *base)@@ -895,6 +990,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,else init.ops = &samsung_pll2550xx_clk_ops;break ; +case pll_2650xx: +if (!pll->rate_table) + init.ops = &samsung_pll2650xx_clk_min_ops; +else + init.ops = &samsung_pll2650xx_clk_ops; +break ;default :pr_warn ("%s: Unknown pll type for pll clk %s\n" , __func__, pll_clk->name);drivers/clk/samsung/clk-pll.h +1
-0@@ -26,6 +26,7 @@ enum samsung_pll_type { pll_6552, pll_6553, pll_2550xx, + pll_2650xx, };#define PLL_35XX_RATE (_rate, _m, _p, _s) \
drivers/clk/samsung/clk-pll.h struct samsung_pll_rate_table { · line 96
Quoted 4 lines
drivers/clk/samsung/clk-pll.h +0
-1@@ -93,5 +94,4 @@ struct samsung_pll_rate_table {extern struct clk *__init samsung_clk_register_pll2550x (const char *name,const char *pname,const void __iomem *reg_base,const unsigned long offset); -
Not a part of this change.
Best regards,
Tomasz
PATCH v2 7/10 clk/exynos5260: add macros and documentation for exynos5260
In reply to Rahul SharmaAdd macros which are used as Clock IDs in DT and clock file. It also adds the documentation for the exynos5260 clocks.
Signed-off-by Rahul Sharma <[email protected]>
--- .../devicetree/bindings/clock/exynos5260-clock.txt | 299 ++++++++++++++++++++ include/dt-bindings/clk/exynos5260-clk.h | 234 +++++++++++++++ 2 files changed, 533 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt create mode 100644 include/dt-bindings/clk/exynos5260-clk.h
Documentation/devicetree/bindings/clock/exynos5260-clock.txt new file +299 -0
@@ -0,0 +1,299 @@ +* Samsung Exynos5260 Clock Controller + +The Exynos5260 clock controller encalsulate all CMUs which are +instantiaited independently from the device-tree. As a whole, +these CMUs generates and supplies clocks to various controllers +within the Exynos5260 SoC. + +Required Properties: + +- compatible: should be one of the following. + - First compatible should be one of the following + "exynos5260-cmu-top" + "exynos5260-cmu-peri" + "exynos5260-cmu-egl" + "exynos5260-cmu-kfc" + "exynos5260-cmu-g2d" + "exynos5260-cmu-mif" + "exynos5260-cmu-mfc" + "exynos5260-cmu-g3d" + "exynos5260-cmu-fsys" + "exynos5260-cmu-aud" + "exynos5260-cmu-isp" + "exynos5260-cmu-gscl" + "exynos5260-cmu-disp" + - Second compatible should be "samsung,exynos5260-clock". + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +The following is the list of clocks generated by the each controller. Each +clock is assigned a MACRO constant. These constants are defined in +"dt-bindings/clk/exynos5260-clk.h". DT client nodes use this MACRO to specify +the clock which they consume. + +----------------------- + CMU_TOP clocks +----------------------- + + FIN_PLL + TOP_FOUT_DISP_PLL + TOP_FOUT_AUD_PLL + TOP_SCLK_MMC0 + TOP_SCLK_MMC1 + TOP_SCLK_MMC2 + TOP_SCLK_HDMIPHY + TOP_SCLK_FIMD1 + TOP_MOUT_FIMD1 + TOP_MOUT_DISP_PLL + +----------------------- + CMU_EGL clocks +----------------------- + + EGL_FOUT_EGL_PLL + EGL_FOUT_EGL_DPLL + +----------------------- + CMU_KFC clocks +----------------------- + + KFC_FOUT_KFC_PLL + +----------------------- + CMU_MIF clocks +----------------------- + + MIF_FOUT_MEM_PLL + MIF_FOUT_BUS_PLL + MIF_FOUT_MEDIA_PLL + +----------------------- + CMU_G3D clocks +----------------------- + + G3D_FOUT_G3D_PLL + G3D_CLK_G3D_HPM + G3D_CLK_G3D + +----------------------- + CMU_AUD clocks +----------------------- + + AUD_CLK_AUD_UART + AUD_CLK_PCM + AUD_CLK_I2S + AUD_CLK_DMAC + AUD_SCLK_AUD_UART + AUD_SCLK_PCM + AUD_SCLK_I2S + AUD_NR_CLK + +----------------------- + CMU_MFC clocks +----------------------- + + MFC_CLK_MFC + MFC_CLK_SMMU2_MFCM1 + MFC_CLK_SMMU2_MFCM0 + +----------------------- + CMU_GSCL clocks +----------------------- + + GSCL_CLK_PIXEL_GSCL1 + GSCL_CLK_PIXEL_GSCL0 + GSCL_CLK_MSCL1 + GSCL_CLK_MSCL0 + GSCL_CLK_GSCL1 + GSCL_CLK_GSCL0 + GSCL_CLK_FIMC_LITE_D + GSCL_CLK_FIMC_LITE_B + GSCL_CLK_FIMC_LITE_A + GSCL_CLK_CSIS1 + GSCL_CLK_CSIS0 + GSCL_CLK_SMMU3_LITE_D + GSCL_CLK_SMMU3_LITE_B + GSCL_CLK_SMMU3_LITE_A + GSCL_CLK_SMMU3_GSCL0 + GSCL_CLK_SMMU3_GSCL1 + GSCL_CLK_SMMU3_MSCL0 + GSCL_CLK_SMMU3_MSCL1 + GSCL_SCLK_CSIS1_WRAP + GSCL_SCLK_CSIS0_WRAP + +----------------------- + CMU_FSYS clocks +----------------------- + + FSYS_CLK_TSI + FSYS_CLK_USBLINK + FSYS_CLK_USBHOST20 + FSYS_CLK_USBDRD30 + FSYS_CLK_SROMC + FSYS_CLK_PDMA + FSYS_CLK_MMC2 + FSYS_CLK_MMC1 + FSYS_CLK_MMC0 + FSYS_CLK_RTIC + FSYS_CLK_SMMU_RTIC + FSYS_PHYCLK_USBDRD30 + FSYS_PHYCLK_USBHOST20 + FSYS_NR_CLK + +----------------------- + CMU_PERI clocks +----------------------- + + PERI_CLK_WDT_KFC + PERI_CLK_WDT_EGL + PERI_CLK_HSIC3 + PERI_CLK_HSIC2 + PERI_CLK_HSIC1 + PERI_CLK_HSIC0 + PERI_CLK_PCM + PERI_CLK_MCT + PERI_CLK_I2S + PERI_CLK_I2CHDMI + PERI_CLK_I2C7 + PERI_CLK_I2C6 + PERI_CLK_I2C5 + PERI_CLK_I2C4 + PERI_CLK_I2C9 + PERI_CLK_I2C8 + PERI_CLK_I2C11 + PERI_CLK_I2C10 + PERI_CLK_HDMICEC + PERI_CLK_EFUSE_WRITER + PERI_CLK_ABB + PERI_CLK_UART2 + PERI_CLK_UART1 + PERI_CLK_UART0 + PERI_CLK_ADC + PERI_CLK_TMU4 + PERI_CLK_TMU3 + PERI_CLK_TMU2 + PERI_CLK_TMU1 + PERI_CLK_TMU0 + PERI_CLK_SPI2 + PERI_CLK_SPI1 + PERI_CLK_SPI0 + PERI_CLK_SPDIF + PERI_CLK_PWM + PERI_CLK_UART4 + PERI_CLK_CHIPID + PERI_CLK_PROVKEY0 + PERI_CLK_PROVKEY1 + PERI_CLK_SECKEY + PERI_CLK_TOP_RTC + PERI_CLK_TZPC10 + PERI_CLK_TZPC9 + PERI_CLK_TZPC8 + PERI_CLK_TZPC7 + PERI_CLK_TZPC6 + PERI_CLK_TZPC5 + PERI_CLK_TZPC4 + PERI_CLK_TZPC3 + PERI_CLK_TZPC2 + PERI_CLK_TZPC1 + PERI_CLK_TZPC0 + PERI_SCLK_SPI2 + PERI_SCLK_SPI1 + PERI_SCLK_SPI0 + PERI_SCLK_SPDIF + PERI_SCLK_I2S + PERI_SCLK_PCM1 + PERI_SCLK_UART2 + PERI_SCLK_UART1 + PERI_SCLK_UART0 + +----------------------- + CMU_DISP clocks +----------------------- + + DISP_CLK_SMMU_TV + DISP_CLK_SMMU_FIMD1M1 + DISP_CLK_SMMU_FIMD1M0 + DISP_CLK_MIXER + DISP_CLK_MIPIPHY + DISP_CLK_HDMIPHY + DISP_CLK_HDMI + DISP_CLK_FIMD1 + DISP_CLK_DSIM1 + DISP_CLK_DPPHY + DISP_CLK_DP + DISP_SCLK_PIXEL + DISP_SCLK_HDMI + DISP_MOUT_HDMI_PHY_PIXEL + DISP_NR_CLK + +----------------------- + CMU_G2D clocks +----------------------- + + G2D_CLK_SMMU3_JPEG + G2D_CLK_MDMA + G2D_CLK_JPEG + G2D_CLK_G2D + G2D_CLK_SSS + G2D_CLK_SLIM_SSS + G2D_CLK_SMMU_SLIM_SSS + G2D_CLK_SMMU_SSS + G2D_CLK_SMMU_MDMA + G2D_CLK_SMMU3_G2D + +----------------------- + CMU_ISP clocks +----------------------- + + ISP_CLK_GIC + ISP_CLK_WDT + ISP_CLK_UART + ISP_CLK_SPI1 + ISP_CLK_SPI0 + ISP_CLK_SMMU_SCALERP + ISP_CLK_SMMU_SCALERC + ISP_CLK_SMMU_ISPCX + ISP_CLK_SMMU_ISP + ISP_CLK_SMMU_FD + ISP_CLK_SMMU_DRC + ISP_CLK_PWM + ISP_CLK_MTCADC + ISP_CLK_MPWM + ISP_CLK_MCUCTL + ISP_CLK_I2C1 + ISP_CLK_I2C0 + ISP_CLK_FIMC_SCALERP + ISP_CLK_FIMC_SCALERC + ISP_CLK_FIMC + ISP_CLK_FIMC_FD + ISP_CLK_FIMC_DRC + ISP_CLK_CA5 + ISP_SCLK_SPI0_EXT + ISP_SCLK_SPI1_EXT + ISP_SCLK_UART_EXT + + +Example 1: An example of a clock controller node is listed below. + + cmu_disp: clock-controller at 0x14550000 { + compatible = "exynos5260-cmu-disp", "samsung,exynos5260-clock"; + reg = <0x14550000 0x10000>; + #clock-cells = <1>; + }; + +Example 2: UART controller node that consumes the clock generated by the + peri clock controller. Refer to the standard clock bindings for + information about 'clocks' and 'clock-names' property. + + serial at 12C00000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C00000 0x100>; + interrupts = <0 146 0>; + clocks = <&cmu_peri PERI_PCLK_UART0>, <&cmu_peri PERI_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; +
include/dt-bindings/clk/exynos5260-clk.h new file +234 -0
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1.7.9.5
PATCH v2 8/10 clk/exynos5260: add clock file for exynos5260
In reply to Rahul SharmaAdd support for exynos5260 clocks in clock driver.
Signed-off-by Rahul Sharma <[email protected]>
Signed-off-by Pankaj Dubey <[email protected]>
--- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5260.c | 2062 ++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-exynos5260.h | 496 ++++++++ 3 files changed, 2559 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos5260.c create mode 100644 drivers/clk/samsung/clk-exynos5260.h
drivers/clk/samsung/Makefile +1 -0
@@ -5,6 +5,7 @@ obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o +obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
drivers/clk/samsung/clk-exynos5260.c new file +2062 -0
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drivers/clk/samsung/clk-exynos5260.h new file +496 -0
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1.7.9.5
PATCH v2 9/10 ARM: dts: add dts files for exynos5260 SoC
In reply to Rahul SharmaThe patch adds the dts files for exynos5260.
Signed-off-by Pankaj Dubey <[email protected]>
Signed-off-by Rahul Sharma <[email protected]>
Signed-off-by Arun Kumar K <[email protected]>
--- arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 572 +++++++++++++++++++++++++++++ arch/arm/boot/dts/exynos5260.dtsi | 317 ++++++++++++++++ 2 files changed, 889 insertions(+) create mode 100644 arch/arm/boot/dts/exynos5260-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/exynos5260.dtsi
arch/arm/boot/dts/exynos5260-pinctrl.dtsi new file +572 -0
@@ -0,0 +1,572 @@ +/* + * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/ { + pinctrl at 11600000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb3: gpb3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb4: gpb4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb5: gpb5 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd2: gpd2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk0: gpk0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_data: uart1-data { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart2_data: uart2-data { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpa2-5", "gpa2-6", "gpa2-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + usb3_vbus0_en: usb3-vbus0-en { + samsung,pins = "gpa2-4"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm1_bus: pcm1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spdif1_bus: spdif1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2"; + samsung,pin-function = <4>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c0_hs_bus: i2c0-hs-bus { + samsung,pins = "gpb3-0", "gpb3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c1_hs_bus: i2c1-hs-bus { + samsung,pins = "gpb3-2", "gpb3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c2_hs_bus: i2c2-hs-bus { + samsung,pins = "gpb3-4", "gpb3-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c3_hs_bus: i2c3-hs-bus { + samsung,pins = "gpb3-6", "gpb3-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c4_bus: i2c4-bus { + samsung,pins = "gpb4-0", "gpb4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c5_bus: i2c5-bus { + samsung,pins = "gpb4-2", "gpb4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c6_bus: i2c6-bus { + samsung,pins = "gpb4-4", "gpb4-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c7_bus: i2c7-bus { + samsung,pins = "gpb4-6", "gpb4-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c8_bus: i2c8-bus { + samsung,pins = "gpb5-0", "gpb5-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c9_bus: i2c9-bus { + samsung,pins = "gpb5-2", "gpb5-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c10_bus: i2c10-bus { + samsung,pins = "gpb5-4", "gpb5-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c11_bus: i2c11-bus { + samsung,pins = "gpb5-6", "gpb5-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_gpio_a: cam-gpio-a { + samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", + "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", + "gpe1-0", "gpe1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_gpio_b: cam-gpio-b { + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_i2c1_bus: cam-i2c1-bus { + samsung,pins = "gpf0-2", "gpf0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_i2c0_bus: cam-i2c0-bus { + samsung,pins = "gpf0-0", "gpf0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_spi0_bus: cam-spi0-bus { + samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + cam_spi1_bus: cam-spi1-bus { + samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + }; + + pinctrl at 12290000 { + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc4: gpc4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpc0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpc0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpc0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_rdqs: sd0-rdqs { + samsung,pins = "gpc0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpc1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpc1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpc1-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus8: sd1-bus-width8 { + samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpc2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpc2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpc2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpc2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + }; + + pinctrl at 128B0000 { + gpz0: gpz0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpz1: gpz1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +};
arch/arm/boot/dts/exynos5260.dtsi new file +317 -0
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1.7.9.5
PATCH v2 10/10 ARM: dts: add dts files for xyref5260 board
In reply to Rahul SharmaThe patch adds the dts files for xyref5260 board which is based on Exynos5260 Evt0 sample.
Signed-off-by Pankaj Dubey <[email protected]>
Signed-off-by Rahul Sharma <[email protected]>
Signed-off-by Arun Kumar K <[email protected]>
--- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 105 +++++++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts
arch/arm/boot/dts/Makefile +1 -0
@@ -64,6 +64,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ exynos5250-snow.dtb \ + exynos5260-xyref5260-evt0.dtb \ exynos5410-smdk5410.dtb \ exynos5420-arndale-octa.dtb \ exynos5420-smdk5420.dtb \
arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts new file +105 -0
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1.7.9.5