cache line size cleanup
PATCH 1/1 cache line size cleanup
Hi Dan,
This patch addresses the following issues :
- removed various definitions of PPC cache stuff (now everything is in include/asm-pcc/cache.h
- removed unused L1_CACHE_PAGES in include/asm-ppc/cache.h
- fixed file arch/ppc/lib/string.S, function __copy_tofrom_user for 16-byte cache lines
- fixed PAGE_SIZE for assembly (gcc understands UL, gas does not)
I am not sure about the cache line size of the 4xx processors :
if needed, please modify include/asm-ppc/cache.h accordingly.
Daniel Marmier
arch/ppc/kernel/misc.S +19 -22
@@ -14,19 +14,14 @@ #include <linux/config.h> #include <linux/sys.h> +#include <asm/cache.h> #include <asm/unistd.h> #include <asm/errno.h> #include <asm/processor.h> #include <asm/page.h> #include "ppc_asm.h" -#if defined(CONFIG_4xx) || defined(CONFIG_8xx) -CACHE_LINE_SIZE = 16 -LG_CACHE_LINE_SIZE = 4 -#else -CACHE_LINE_SIZE = 32 -LG_CACHE_LINE_SIZE = 5 -#endif /* CONFIG_4xx || CONFIG_8xx */ +#define CACHELINES_PER_PAGE (PAGE_SIZE/L1_CACHE_BYTES) .text
@@ -188,21 +183,21 @@ rlwinm r5,r5,16,16,31 cmpi 0,r5,1 beqlr /* for 601, do nothing */ - li r5,CACHE_LINE_SIZE-1 + li r5,L1_CACHE_MASK andc r3,r3,r5 subf r4,r3,r4 add r4,r4,r5 - srwi. r4,r4,LG_CACHE_LINE_SIZE + srwi. r4,r4,L1_CACHE_SHIFT beqlr mtctr r4 mr r6,r3 1: dcbst 0,r3 - addi r3,r3,CACHE_LINE_SIZE + addi r3,r3,L1_CACHE_BYTES bdnz 1b sync /* wait for dcbst's to get to ram */ mtctr r4 2: icbi 0,r6 - addi r6,r6,CACHE_LINE_SIZE + addi r6,r6,L1_CACHE_BYTES bdnz 2b sync isync
@@ -214,16 +209,16 @@ * flush_dcache_range(unsigned long start, unsigned long stop) */ _GLOBAL(flush_dcache_range) - li r5,CACHE_LINE_SIZE-1 + li r5,L1_CACHE_MASK andc r3,r3,r5 subf r4,r3,r4 add r4,r4,r5 - srwi. r4,r4,LG_CACHE_LINE_SIZE + srwi. r4,r4,L1_CACHE_SHIFT beqlr mtctr r4 1: dcbst 0,r3 - addi r3,r3,CACHE_LINE_SIZE + addi r3,r3,L1_CACHE_BYTES bdnz 1b sync /* wait for dcbst's to get to ram */ blr
@@ -243,16 +238,16 @@ beqlr /* for 601, do nothing */ li r4,0x0FFF andc r3,r3,r4 /* Get page base address */ - li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ + li r4,CACHELINES_PER_PAGE /* Number of lines in a page */ mtctr r4 mr r6,r3 0: dcbst 0,r3 /* Write line to ram */ - addi r3,r3,CACHE_LINE_SIZE + addi r3,r3,L1_CACHE_BYTES bdnz 0b sync mtctr r4 1: icbi 0,r6 - addi r6,r6,CACHE_LINE_SIZE + addi r6,r6,L1_CACHE_BYTES bdnz 1b sync isync
@@ -271,10 +266,10 @@ rlwinm r5,r5,16,16,31 cmpi 0,r5,1 beqlr /* for 601, do nothing */ - li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ + li r4,CACHELINES_PER_PAGE /* Number of lines in a page */ mtctr r4 1: icbi 0,r3 - addi r3,r3,CACHE_LINE_SIZE + addi r3,r3,L1_CACHE_BYTES bdnz 1b sync isync
@@ -286,10 +281,10 @@ * displaced). This only works on cacheable memory. */ _GLOBAL(clear_page) - li r0,4096/CACHE_LINE_SIZE + li r0,CACHELINES_PER_PAGE mtctr r0 1: dcbz 0,r3 - addi r3,r3,CACHE_LINE_SIZE + addi r3,r3,L1_CACHE_BYTES bdnz 1b blr
@@ -300,7 +295,7 @@ * is cacheable. */ _GLOBAL(copy_page) - li r0,4096/CACHE_LINE_SIZE + li r0,CACHELINES_PER_PAGE mtctr r0 addi r3,r3,-4 addi r4,r4,-4
@@ -314,6 +309,7 @@ stw r7,8(r3) stw r8,12(r3) stwu r9,16(r3) +#if (L1_CACHE_BYTES == 32) lwz r6,4(r4) lwz r7,8(r4) lwz r8,12(r4)
@@ -322,6 +318,7 @@ stw r7,8(r3) stw r8,12(r3) stwu r9,16(r3) +#endif bdnz 1b blr
arch/ppc/lib/string.S +27 -18
149 lines not on this page · raw message
include/asm-ppc/cache.h +7 -3
@@ -5,12 +5,16 @@#define __ARCH_PPC_CACHE_H#include <linux/config.h> -#include <asm/processor.h> /* bytes per L1 cache line */ -#define L1_CACHE_BYTES 32 +#if defined(CONFIG_4xx) || defined(CONFIG_8xx) +#define L1_CACHE_SHIFT 4 +#else +#define L1_CACHE_SHIFT 5 +#endif +#define L1_CACHE_BYTES (1<<L1_CACHE_SHIFT) +#define L1_CACHE_MASK (L1_CACHE_BYTES-1)#define L1_CACHE_ALIGN (x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) -#define L1_CACHE_PAGES 8#define SMP_CACHE_BYTES L1_CACHE_BYTES
include/asm-ppc/page.h +4 -0
@@ -5,7 +5,11 @@/* PAGE_SHIFT determines the page size */ #define PAGE_SHIFT 12 +#ifndef __ASSEMBLY__#define PAGE_SIZE (1UL << PAGE_SHIFT) +#else +#define PAGE_SIZE (1 << PAGE_SHIFT) +#endif #define PAGE_MASK (~(PAGE_SIZE-1))#define PAGE_OFFSET 0xc0000000
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