8260 io and caches
Hi all,
I'm currently trying to get linux running on EST SBC8260 board. I had some problems with serial ports. Initially it just sent some garbage. I found that serial port driver doesn't initialize BRG division factor in SCCR register even though it assumes that it should be set to 0. I modified my bootloader to initialize it and output looks now much better.
There still seems to be some problems with caches. Everything is just fine with caches disabled, but if i enable caches output doesn't look correct. Adding some flush_dcache_range() calls to uart.c seems to fix that problem, but shouldn't rx & tx buffers be allocated from some non cacheable region??
Thanks
Arto
--
Arto Vuori
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Quoted 2 lines · Arto Vuori
I'm currently trying to get linux running on EST SBC8260 board. I had some problems with serial ports.
OK.....
Quoted 1 line
There still seems to be some problems with caches.
What version of processor silicon do you have?
-- Dan
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Quoted 2 lines
From what I can see, the uart driver in the current linux source is written
for the 860, with no mods for the 8260. The 8260 has some different bits in the RFCR/TFCR parameter RAM fields. There is a GBL bit (bit 2) that enables cache snooping.
I'm looking at the 2.3.99-pre5 sources, at about line 2519 in uart.c:
up->smc_rfcr = SMC_EB; up->smc_tfcr = SMC_EB;
change them to:
up->smc_rfcr = SMC_EB | 0x20; up->smc_tfcr = SMC_EB | 0x20;
and see what happens. Of course, you probably want to add a SMC_GBL #define to do this properly.
Neil.
Quoted 7 lines · Arto Vuori
I'm currently trying to get linux running on EST SBC8260 board. I had some problems with serial ports. Initially it just sent some garbage. I found that serial port driver doesn't initialize BRG division factor in SCCR register even though it assumes that it should be set to 0. I modified my bootloader to initialize it and output looks now much better.
Quoted 5 lines
There still seems to be some problems with caches. Everything is just fine with caches disabled, but if i enable caches output doesn't look correct. Adding some
flush_dcache_range()calls touart.cseems to fix that problem, but shouldn't rx & tx buffers be allocated from some non cacheable region??
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Quoted 3 lines · Neil Russell
Quoted 2 lines
From what I can see, the uart driver in the current linux source is written
for the 860, with no mods for the 8260.
Oh, there are some mods, but I did start with the 8xx code :-).
Quoted 3 lines
.... The 8260 has some different bits
in the RFCR/TFCR parameter RAM fields. There is a GBL bit (bit 2) that enables cache snooping.
Oooops. Sorry about that. I was playing with caches (and not) and I guess I didn't get everything checked in properly. Make sure you also make the same cache changes to the SCC Ethernet.
Don't consider this software ready to run. I have more to check in and I am still making lots of changes.
Quoted 2 lines
..... Of course, you probably want to add a
SMC_GBL#define to do this properly.
It was supposed to be there...........
-- Dan
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