Fix MTRR support for AMD Athlon
PATCH 1/1 Fix MTRR support for AMD Athlon
Hello world,
Dave Jones' recent 2.4.2ac17 patch to mtrr.c to support the Cyrix III unfortunately broke the AMD Athlon support. Here's a patch to correct the problem (Dave must have overlooked the fall-through logic of the switch statement).
Enjoy...
Signature · 61 lines
Troels Walsted Hansen
--- mtrr.c1.38 Sun Mar 11 13:42:30 2001
+++ mtrr.c Mon Mar 12 21:02:15 2001
@@ -235,6 +235,12 @@
v1.38
20010309 Dave Jones <[email protected]>
Add support for Cyrix III.
+
+ v1.39
+ 20010312 Troels Walsted Hansen <[email protected]>
+ Fixed the AMD Athlon support that Dave Jones' patch
broke.
+ Also updated the version number to match this changelog.
+
*/
#include <linux/types.h>
#include <linux/errno.h>
@@ -274,7 +280,7 @@
#include <asm/hardirq.h>
#include <linux/irq.h>
-#define MTRR_VERSION "1.37 (20001109)"
+#define MTRR_VERSION "1.39 (20010312)"
#define TRUE 1
#define FALSE 0
@@ -1964,6 +1970,14 @@
get_mtrr = intel_get_mtrr;
set_mtrr_up = intel_set_mtrr_up;
switch (boot_cpu_data.x86_vendor) {
+ case X86_VENDOR_CENTAUR:
+ /* Cyrix III has Intel style MTRRs, but doesn't support
PAE */
+ if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model ==
6) {
+ size_or_mask = 0xfff00000; /* 32 bits */
+ size_and_mask = 0;
+ }
+ break;
+
case X86_VENDOR_AMD:
/* The original Athlon docs said that
total addressable memory is 44 bits wide.
@@ -1982,13 +1996,7 @@
size_and_mask = ~size_or_mask & 0xfff00000;
break;
}
- case X86_VENDOR_CENTAUR:
- /* Cyrix III has Intel style MTRRs, but doesn't support
PAE */
- if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model ==
6) {
- size_or_mask = 0xfff00000; /* 32 bits */
- size_and_mask = 0;
- }
- break;
+ /* NOTE: fallthrough to default here! */
default:
/* Intel, etc. */On Mon, 12 Mar 2001, Troels Walsted Hansen wrote:
Hi Troels,
Quoted 4 lines
Dave Jones' recent 2.4.2ac17 patch to
mtrr.cto support the Cyrix III unfortunately broke the AMD Athlon support. Here's a patch to correct the problem (Dave must have overlooked the fall-through logic of the switch statement).
Indeed I did. I was about to look into this just as your mail arrived, after someone told me about MTRRs with 'size=16773376MB'. This should fix it. However I think the patch below would be a better fix, removing the drop-through case, and making the switch more obvious. It guarantees no-one will make the mistake again :) (At least not with this switch).
Patch rediffed against 2.4.2-ac19
regards,
Dave.
arch/i386/kernel/mtrr.c +13 -1
@@ -235,6 +235,12 @@v1.38 20010309 Dave Jones <[email protected]> Add support for Cyrix III. + +v1.39 +20010312 Dave Jones <[email protected]> +Ugh, I broke AMD support. +Reworked fix by Troels Walsted Hansen <[email protected]> +*/ #include <linux/types.h> #include <linux/errno.h>
@@ -274,7 +280,7 @@#include <asm/hardirq.h> #include <linux/irq.h> -#define MTRR_VERSION "1.37 (20001109)" +#define MTRR_VERSION "1.39 (20010312)"#define TRUE 1#define FALSE 0
@@ -1964,6 +1970,7 @@ get_mtrr = intel_get_mtrr; set_mtrr_up = intel_set_mtrr_up;switch (boot_cpu_data.x86_vendor) { +case X86_VENDOR_AMD :/* The original Athlon docs said that total addressable memory is 44 bits wide.
@@ -1982,6 +1989,10 @@ size_and_mask = ~size_or_mask &0xfff00000 ;break ; } + size_or_mask =0xff000000 ;/* 36 bits */ + size_and_mask =0x00f00000 ; +break ; +case X86_VENDOR_CENTAUR :/* Cyrix III has Intel style MTRRs, but doesn't support PAE */ if (boot_cpu_data.x86 ==6 && boot_cpu_data.x86_model ==6 ) {
@@ -1996,6 +2007,7 @@ size_and_mask =0x00f00000 ;break ; } + }else if (test_bit (X86_FEATURE_K6_MTRR , &boot_cpu_data.x86_capability) ) {/* Pre-Athlon (K6) AMD CPU MTRRs */ mtrr_if =MTRR_IF_AMD_K6 ;
Signature · 2 lines
| Dave Jones. http://www.suse.de/~davej | SuSE Labs