ppc little-endian port
Hello everyone!
This is a port of Montavista's 2.4.0-test2 kernel to ppc running in Little-Endian.
As a base, we used Sandpoint configuration, but disabled some irrelevant code for our board (these changes are not in the patch).
We made it just for a board with CPU and RAM only, so if you want to use anything extra (drives, PCI, etc.)
you have to look at the corresponding code and make changes accordingly (if needed). Additionally, if you use different configuration scheme (not sandpoint), you might have to do some other changes.
Sebastien Cote: [email protected]
Alexandre Nikoalev: [email protected]
--
*****************************************
| Alexandre Nikolaev | Software Designer | Matrox Electronic Systems Ltd | Imaging Department | Tel. (514) 8226000 ext. 2323 | E-mail: [email protected]
*****************************************:)
arch/ppc/Makefile renamed from usr/src/redhat/SOURCES/linux/arch/ppc/Makefile +1 -1
@@ -23,7 +23,7 @@ CPPFLAGS := $(CPPFLAGS) -D__powerpc__ CFLAGS := $(CFLAGS) -D__powerpc__ -fsigned-char \ -msoft-float -pipe -ffixed-r2 -Wno-uninitialized \ - -mmultiple -mstring +# -mmultiple -mstring CPP = $(CC) -E $(CFLAGS) ifdef CONFIG_4xx
arch/ppc/kernel/hashtable.S renamed from usr/src/redhat/SOURCES/linux/arch/ppc/kernel/hashtable.S +10 -8
@@ -321,7 +321,7 @@ /* Search the primary PTEG for a PTE whose 1st word matches r5 */ mtctr r2 - addi r3,r4,-8 + addi r3,r4,-4 /* Changed from -8 to -4 by me !!!! */ 1: lwzu r0,8(r3) /* get next PTE */ cmp 0,r0,r5 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
@@ -333,7 +333,7 @@ hash_page_patch_B: xoris r3,r4,Hash_msk>>16 /* compute secondary hash */ xori r3,r3,0xffc0 - addi r3,r3,-8 + addi r3,r3,-4 /* Changed from -8 to -4 by me !!!! */ mtctr r2 2: lwzu r0,8(r3) cmp 0,r0,r5
@@ -343,7 +343,8 @@ /* Search the primary PTEG for an empty slot */ 10: mtctr r2 - addi r3,r4,-8 /* search primary PTEG */ + addi r3,r4,-4 /* search primary PTEG */ + /* Changed from -8 to -4 by me !!!! */ 1: lwzu r0,8(r3) /* get next PTE */ rlwinm. r0,r0,0,0,0 /* only want to check valid bit */ bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
@@ -355,7 +356,7 @@ hash_page_patch_C: xoris r3,r4,Hash_msk>>16 /* compute secondary hash */ xori r3,r3,0xffc0 - addi r3,r3,-8 + addi r3,r3,-4 /* Changed from -8 to -4 by me !!!! */ mtctr r2 2: lwzu r0,8(r3)
@@ -380,6 +381,7 @@ andi. r2,r2,0x38 stw r2,next_slot@l(r3) add r3,r4,r2 + addi r3,r3,4 /* Add 4 to realign data, by me !!!! */ 11: /* update counter of evicted pages */ lis r2,htab_evicts@ha
@@ -393,7 +395,7 @@ found_empty: stw r5,0(r3) found_slot: - stw r6,4(r3) + stw r6,-4(r3) /* Changed to -4 to preserve LE by me !!!! */ sync #else /* CONFIG_SMP */
@@ -543,7 +545,7 @@ lwz r6,Hash_size@l(r6) /* size in bytes */ srwi r6,r6,3 /* # PTEs */ mtctr r6 - addi r5,r5,-8 + addi r5,r5,-4 /* Changed from -8 to -4 by me !!!! */ li r0,0 1: lwzu r6,8(r5) /* get next tag word */ cmplw 0,r6,r3
@@ -642,7 +644,7 @@ add r6,r6,r7 /* address of primary PTEG */ li r8,8 mtctr r8 - addi r7,r6,-8 + addi r7,r6,-4 /* Changed from -8 to -4 by me !!!! */ 1: lwzu r0,8(r7) /* get next PTE */ cmpw 0,r0,r3 /* see if tag matches */ bdnzf 2,1b /* while --ctr != 0 && !cr0.eq */
@@ -650,7 +652,7 @@ ori r3,r3,0x40 /* set H (alt. hash) bit */ xor r6,r6,r5 /* address of secondary PTEG */ mtctr r8 - addi r7,r6,-8 + addi r7,r6,-4 /* Changed from -8 to -4 by me !!!! */ 2: lwzu r0,8(r7) /* get next PTE */ cmpw 0,r0,r3 /* see if tag matches */ bdnzf 2,2b /* while --ctr != 0 && !cr0.eq */
arch/ppc/kernel/head.S renamed from usr/src/redhat/SOURCES/linux/arch/ppc/kernel/head.S +56 -18
188 lines not on this page · raw message
arch/ppc/kernel/irq.c renamed from usr/src/redhat/SOURCES/linux/arch/ppc/kernel/irq.c +2 -1
@@ -349,7 +349,8 @@else once++; - ppc_md.init_IRQ (); +if (ppc_md.init_IRQ)/* Added by me !!!! */ + ppc_md.init_IRQ (); }#ifdef CONFIG_SMP
Only in /usr/src/redhat/SOURCES/linux/arch/ppc/mbxboot: vmlinux.lds Only in /usr/src/redhat/SOURCES/linux/drivers/pcmcia: Config.in.orig
include/asm-ppc/bitops.h renamed from usr/src/redhat/SOURCES/linux/include/asm-ppc/bitops.h +4 -0
@@ -242,8 +242,12 @@* test_and_{set,clear}_bit guarantee atomicity without * disabling interrupts. */ +#if 0 #define ext2_set_bit (nr, addr) test_and_set_bit((nr) ^ 0x18, addr)#define ext2_clear_bit (nr, addr) test_and_clear_bit((nr) ^ 0x18, addr) +#endif /* Replaced by me !!!! (to remove XOR) */ +#define ext2_set_bit (nr, addr) test_and_set_bit((nr), addr) +#define ext2_clear_bit (nr, addr) test_and_clear_bit((nr), addr)#else extern __inline__int ext2_set_bit (int nr,void * addr)
include/asm-ppc/byteorder.h renamed from usr/src/redhat/SOURCES/linux/include/asm-ppc/byteorder.h +12 -9
@@ -9,7 +9,7 @@#ifdef __GNUC__ -extern __inline__unsigned ld_le16 (const volatile unsigned short *addr) +extern __inline__unsigned ld_be16 (const volatile unsigned short *addr) {unsigned val;
@@ -17,12 +17,12 @@return val; } -extern __inline__void st_le16 (volatile unsigned short *addr,const unsigned val) +extern __inline__void st_be16 (volatile unsigned short *addr,const unsigned val) { __asm__ __volatile__ ("sthbrx %1,0,%2" :"=m" (*addr) :"r" (val),"r" (addr)); } -extern __inline__unsigned ld_le32 (const volatile unsigned *addr) +extern __inline__unsigned ld_be32 (const volatile unsigned *addr) {unsigned val;
@@ -30,7 +30,7 @@return val; } -extern __inline__void st_le32 (volatile unsigned *addr,const unsigned val) +extern __inline__void st_be32 (volatile unsigned *addr,const unsigned val) { __asm__ __volatile__ ("stwbrx %1,0,%2" :"=m" (*addr) :"r" (val),"r" (addr)); }
@@ -71,18 +71,21 @@#endif /* The same, but returns converted value from the location pointer by addr. */ -#define __arch__swab16p (addr) ld_le16(addr) -#define __arch__swab32p (addr) ld_le32(addr) +#define __arch__swab16p (addr) ld_be16(addr) +#define __arch__swab32p (addr) ld_be32(addr)/* The same, but do the conversion in situ, ie. put the value back to addr. */ -#define __arch__swab16s (addr) st_le16(addr,*addr) -#define __arch__swab32s (addr) st_le32(addr,*addr) +#define __arch__swab16s (addr) st_be16(addr,*addr) +#define __arch__swab32s (addr) st_be32(addr,*addr)#endif /* __GNUC__ */ +/* All "le" changed to "be", and vice-versa, by me !!!! */ +#if defined(__GNUC__) && !defined(__STRICT_ANSI__)#define __BYTEORDER_HAS_U64__#endif -#include <linux/byteorder/big_endian.h> +#include <linux/byteorder/little_endian.h> +/* Changed from big_endian to little_endian by me !!!! */ #endif /* _PPC_BYTEORDER_H */
include/asm-ppc/io.h renamed from usr/src/redhat/SOURCES/linux/include/asm-ppc/io.h +8 -8
@@ -231,7 +231,7 @@ __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" :"=m" (*addr) :"r" (val)); } -extern inline int in_le16 (volatile unsigned short *addr) +extern inline int in_be16 (volatile unsigned short *addr) {int ret;
@@ -240,7 +240,7 @@return ret; } -extern inline int in_be16 (volatile unsigned short *addr) +extern inline int in_le16 (volatile unsigned short *addr) {int ret;
@@ -248,18 +248,18 @@return ret; } -extern inline void out_le16 (volatile unsigned short *addr,int val) +extern inline void out_be16 (volatile unsigned short *addr,int val) { __asm__ __volatile__("sthbrx %1,0,%2; eieio" :"=m" (*addr) :"r" (val),"r" (addr)); } -extern inline void out_be16 (volatile unsigned short *addr,int val) +extern inline void out_le16 (volatile unsigned short *addr,int val) { __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" :"=m" (*addr) :"r" (val)); } -extern inline unsigned in_le32 (volatile unsigned *addr) +extern inline unsigned in_be32 (volatile unsigned *addr) {unsigned ret;
@@ -268,7 +268,7 @@return ret; } -extern inline unsigned in_be32 (volatile unsigned *addr) +extern inline unsigned in_le32 (volatile unsigned *addr) {unsigned ret;
@@ -276,13 +276,13 @@return ret; } -extern inline void out_le32 (volatile unsigned *addr,int val) +extern inline void out_be32 (volatile unsigned *addr,int val) { __asm__ __volatile__("stwbrx %1,0,%2; eieio" :"=m" (*addr) :"r" (val),"r" (addr)); } -extern inline void out_be32 (volatile unsigned *addr,int val) +extern inline void out_le32 (volatile unsigned *addr,int val) { __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" :"=m" (*addr) :"r" (val)); }
include/asm-ppc/processor.h renamed from usr/src/redhat/SOURCES/linux/include/asm-ppc/processor.h +2 -1
@@ -45,7 +45,8 @@#ifdef CONFIG_APUS_FAST_EXCEPT #define MSR_ MSR_ME|MSR_IP|MSR_RI#else -#define MSR_ MSR_ME|MSR_RI +#define MSR_ MSR_ME|MSR_RI|MSR_LE|MSR_ILE +/* MSD_LE and MSR_ILE added by me !!!! */ #endif #define MSR_KERNEL MSR_|MSR_IR|MSR_DR#define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE
Why?
} This is a port of Montavista's 2.4.0-test2 kernel to ppc running in } Little-Endian.
} As a base, we used Sandpoint configuration, but disabled some irrelevant } code for our board (these changes are not in the patch).
} We made it just for a board with CPU and RAM only, so if you want to use } anything extra (drives, PCI, etc.)
} you have to look at the corresponding code and make changes accordingly } (if needed). Additionally, if you use different configuration scheme } (not sandpoint), you might have to do some other changes.
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
Quoted 2 lines · Cort Dougan
Why?
Yeah, we really don't care about little-endian. Like I always say, getting a kernel built and booted is the easy part. The entire world runs big endian tools, libraries and applications. Making all of that work is a task no one is going to tackle.
While refreshing my PowerPC history the other day, I found a UISA book from 1991.....The Little-Endian Byte Ordering chapter introduction has this to say:
It is computed that eleven Thousand Persons have, at several Times, suffered Death, rather than submit to break their Eggs at the smaller End. Many hundred large Volumes have been published upon this Controversy...
Jonathan Swift, "Gulliver's Travels"
Later in the text it states "There are 24 ways to specify the ordering of four bytes withing a word, but only two of these orderings are sensible."
I contend there is only one sensible ordering, and we are already using it.........
-- Dan
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
Quoted 9 lines · Dan Malek
Quoted 2 lines · Cort Dougan
Why?
Yeah, we really don't care about little-endian. Like I always say, getting a kernel built and booted is the easy part. The entire world runs big endian tools, libraries and applications. Making all of that work is a task no one is going to tackle.
Indeed...
Quoted 3 lines
While refreshing my PowerPC history the other day, I found a UISA book from 1991.....The Little-Endian Byte Ordering chapter introduction has this to say:
1991 ? I though PPC came in 1993. First Power systems were announced and delivered in 1990 AFAIR.
Quoted 3 lines
Later in the text it states "There are 24 ways to specify the ordering of four bytes withing a word, but only two of these orderings are sensible."
Indeed the PDP was a nightmare, like VAX floating-point formats BTW...
Quoted 2 lines
I contend there is only one sensible ordering, and we are already using it.........
Right, unfortunately so many people have been brainwashed by the niadne-elttil side and are unable to think on their own.
Regards,
Gabriel.
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
A message that is not in the archive (sent off-list or not yet received): [email protected]
Sorry, we were not clear enough...
Why we did it:
We have our own image processing PCI board. Hardware guys
decided that since PCI is little endian, it would be better from "their hardware point of view" to run ppc in little-endian as well. We can do nothing about that and just have to run ppc in little endian. Maybe someone else will be on the same boat :)
What else we did:
We compiled the whole Busy Box using glibc with some
modifications of glibc (endian related + strange bug). Also, we compiled the ash of standard source (taken from Montavista) using Dietlibc with no modifications. Then we compiled and run an application under ash shell (yieldt benchmark from Montavista) and saw good results: typically 7 ms and 11 ms thread context switch time regardless of number of threads and thread size, for revisions 2.09 and 2.06 respectfully.
Which processors did we test:
We ran only 7400, revision 2.06 and 2.09.
Alexandre
*****************************************
| Alexandre Nikolaev | Software Designer | Matrox Electronic Systems Ltd | Imaging Department | Tel. (514) 8226000 ext. 2323 | E-mail: [email protected]
*****************************************:)
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/