radeonfb for kernel-2.4.18-pre1
PATCH 1/1 radeonfb for kernel-2.4.18-pre1
Hi this patch fix's up the compiling issue with the Radeon Frame Buffer driver. With this patch it should compile. I checked all over the LKML and there has ben acouple of people who have sent the same patch in but have not been acknowledged. Please apply this patch. Or Alan would you please include this patch in your next ac release if you do have one?
Thank you Victor
drivers/video/radeonfb.c Sat Dec 29 22:35:21 2001 renamed from drivers/video/radeonfb.c.orig Sat Dec 29 20:48:07 2001 +4 -3
@@ -76,6 +76,7 @@ #include <video/fbcon-cfb32.h> #include "radeon.h" +#define LVDS_STATE_MASK 0xFFFFFFFF #define DEBUG 0
@@ -2280,7 +2281,7 @@ save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL); save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL); save->tmds_crc = INREG(TMDS_CRC); - save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL); +/* save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL); */ }
@@ -2557,8 +2558,8 @@ } else { /* DFP */ newmode.fp_gen_cntl |= (FP_FPON | FP_TMDS_EN); - newmode.tmds_transmitter_cntl = (TMDS_RAN_PAT_RST | - ICHCSEL) & ~(TMDS_PLLRST); +/* newmode.tmds_transmitter_cntl = (TMDS_RAN_PAT_RST | + ICHCSEL) & ~(TMDS_PLLRST); */ newmode.crtc_ext_cntl &= ~CRTC_CRT_ON; } @@ -2647,7 +2648,7 @@
OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
OUTREG(TMDS_CRC, mode->tmds_crc);
- OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
+/* OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl); */
if (primary_mon == MT_LCD) {
unsigned int tmp = INREG(LVDS_GEN_CNTL);The patch below is just a hack to get the driver to compile.
I've had success with the patch in the message referenced below which is from the driver maintainer. It fixes the compile problem in a cleaner manner by adding the required defines to the radeon.h header file.
http://marc.theaimsgroup.com/?l=linux-kernel&m=101046020806692&w=2
BTW - Also, here is my patch to radeonfb to detect panel geometry using radeon BIOS registers on Radeon Mobility M6 chipset.
http://gort.metaparadigm.com/radeonfb/radeon-bios-dfpinfo-2.patch
radeonfb still needs DDC detection added for x86 (use OF on PPC to get EDID info), although the BIOS detection is still required as not all panels support DDC (such as the LCD panel in my laptop).
~mc
Quoted 40 lines · reddog83 wrote:
Hi this patch fix's up the compiling issue with the Radeon Frame Buffer driver. With this patch it should compile. I checked all over the LKML and there has ben acouple of people who have sent the same patch in but have not been acknowledged. Please apply this patch. Or Alan would you please include this patch in your next ac release if you do have one? Thank you Victor
------------------------------------------------------------------------
drivers/video/radeonfb.c Sat Dec 29 22:35:21 2001 renamed from drivers/video/radeonfb.c.orig Sat Dec 29 20:48:07 2001 +4
-3@@ -76,6 +76,7 @@ #include <video/fbcon-cfb32.h> #include "radeon.h" +#define LVDS_STATE_MASK 0xFFFFFFFF #define DEBUG 0@@ -2280,7 +2281,7 @@ save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL); save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL); save->tmds_crc = INREG(TMDS_CRC); - save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL); +/* save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL); */ }@@ -2557,8 +2558,8 @@ } else { /* DFP */ newmode.fp_gen_cntl |= (FP_FPON | FP_TMDS_EN); - newmode.tmds_transmitter_cntl = (TMDS_RAN_PAT_RST | - ICHCSEL) & ~(TMDS_PLLRST); +/* newmode.tmds_transmitter_cntl = (TMDS_RAN_PAT_RST | + ICHCSEL) & ~(TMDS_PLLRST); */ newmode.crtc_ext_cntl &= ~CRTC_CRT_ON; } @@ -2647,7 +2648,7 @@OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch); OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl); OUTREG(TMDS_CRC, mode->tmds_crc);drivers/video/radeonfb.c Sat Dec 29 22:35:21 2001 renamed from drivers/video/radeonfb.c.orig Sat Dec 29 20:48:07 2001 +1
-1- OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl); +/* OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl); */ if (primary_mon == MT_LCD) { unsigned int tmp = INREG(LVDS_GEN_CNTL);
Hi Michael,
Thanks for the patch, I will merge it in tomorrow and release an updated version of the driver soon after.
ani
Quoted 68 lines · Michael Clark
The patch below is just a hack to get the driver to compile.
I've had success with the patch in the message referenced below which is from the driver maintainer. It fixes the compile problem in a cleaner manner by adding the required defines to the
radeon.hheader file.http://marc.theaimsgroup.com/?l=linux-kernel&m=101046020806692&w=2BTW - Also, here is my patch to radeonfb to detect panel geometry using radeon BIOS registers on Radeon Mobility M6 chipset.
http://gort.metaparadigm.com/radeonfb/radeon-bios-dfpinfo-2.patch
radeonfb still needs DDC detection added for x86 (use OF on PPC to get EDID info), although the BIOS detection is still required as not all panels support DDC (such as the LCD panel in my laptop).
~mc
Quoted 45 lines · reddog83 wrote:
Hi this patch fix's up the compiling issue with the Radeon Frame Buffer driver. With this patch it should compile. I checked all over the LKML and there has ben acouple of people who have sent the same patch in but have not been acknowledged. Please apply this patch. Or Alan would you please include this patch in your next ac release if you do have one?
Thank you Victor------------------------------------------------------------------------
drivers/video/radeonfb.c Sat Dec 29 22:35:21 2001 renamed from drivers/video/radeonfb.c.orig Sat Dec 29 20:48:07 2001 +4
-3@@ -76,6 +76,7 @@ #include <video/fbcon-cfb32.h> #include "radeon.h" +#define LVDS_STATE_MASK 0xFFFFFFFF #define DEBUG 0@@ -2280,7 +2281,7 @@ save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL); save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL); save->tmds_crc = INREG(TMDS_CRC); - save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL); +/* save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL); */ }@@ -2557,8 +2558,8 @@ } else { /* DFP */ newmode.fp_gen_cntl |= (FP_FPON | FP_TMDS_EN); - newmode.tmds_transmitter_cntl = (TMDS_RAN_PAT_RST | - ICHCSEL) & ~(TMDS_PLLRST); +/* newmode.tmds_transmitter_cntl = (TMDS_RAN_PAT_RST | + ICHCSEL) & ~(TMDS_PLLRST); */ newmode.crtc_ext_cntl &= ~CRTC_CRT_ON; } @@ -2647,7 +2648,7 @@OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch); OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl); OUTREG(TMDS_CRC, mode->tmds_crc);drivers/video/radeonfb.c Sat Dec 29 22:35:21 2001 renamed from drivers/video/radeonfb.c.orig Sat Dec 29 20:48:07 2001 +1
-1- OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl); +/* OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl); */ if (primary_mon == MT_LCD) { unsigned int tmp = INREG(LVDS_GEN_CNTL);
PATCH 1/1 drivers/video/modedb.c - 1400x1050 fbdev mode timings
Thanks Ani,
Here's another one people might find useful - these are the timings detected using the radeon BIOS registers for my 1400x1050 LCD. Someone might find these useful if their XGA panel geometry can't be detected as there are currently no 1400x1050 modes defined in modedb.c
cheers,
~mc
Quoted 10 lines · Ani Joshi
Hi Michael,
Thanks for the patch, I will merge it in tomorrow and release an updated version of the driver soon after.
ani
On Thu, 17 Jan 2002, Michael Clark wrote:
[snip]
Quoted 4 lines
Quoted 4 lines
BTW - Also, here is my patch to radeonfb to detect panel geometry using radeon BIOS registers on Radeon Mobility M6 chipset.
http://gort.metaparadigm.com/radeonfb/radeon-bios-dfpinfo-2.patch
drivers/video/modedb.c +4 -0
@@ -127,6 +127,10 @@NULL ,61 ,1280 ,1024 ,9090 ,200 ,48 ,26 ,1 ,184 ,3 ,0 ,FB_VMODE_NONINTERLACED }, { +/* 1400x1050 @ 60Hz, 63.9 kHz hsync */ +NULL ,68 ,1400 ,1050 ,9259 ,136 ,40 ,13 ,1 ,112 ,3 , +0 ,FB_VMODE_NONINTERLACED + }, {/* 1024x768 @ 85 Hz, 70.24 kHz hsync */ NULL ,85 ,1024 ,768 ,10111 ,192 ,32 ,34 ,14 ,160 ,6 ,0 ,FB_VMODE_NONINTERLACED
Quoted 1 line · reddog83 wrote:
Hi this patch fix's up the compiling issue with the Radeon Frame Buffer driver. With this patch it should compile. I checked all over the LKML and there has ben acouple of people who have sent the same patch in but have not been acknowledged. Please apply this patch. Or Alan would you please include this patch in your next ac release if you do have one? Thank you Victor
<more content snipped>
Review
Quoted 9 lines
@@ -2647,7 +2648,7 @@
OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch); OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl); OUTREG(TMDS_CRC, mode->tmds_crc);(quoted diff) +1
-1- OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl); +/* OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl); */ if (primary_mon == MT_LCD) { unsigned int tmp = INREG(LVDS_GEN_CNTL);
This should be the correct patch, which instead of disabling code in the driver just correctly defines the necessary code in radeon.h. This patch was posted to linux-kernel a while back and when it was originally posted it was said to have come straight from Ani Joshi. This would make sense as it brings the mainline radeon.h in sync with the radeon.h which is in the linuxppc-devel bitkeeper tree.
Jordan
drivers/video/radeon.h renamed from drivers/video/radeon.h.orig +35 -2
@@ -97,5 +97,7 @@#define MEM_VGA_RP_SEL 0x003C#define HDP_DEBUG 0x0138 -#define SW_SEMAPHORE 0x013C +#define SW_SEMAPHORE 0x013C +#define CRTC2_GEN_CNTL 0x03f8 +#define CRTC2_DISPLAY_BASE_ADDR 0x033c#define SURFACE_CNTL 0x0B00#define SURFACE0_LOWER_BOUND 0x0B04
@@ -338,4 +338,5 @@#define DST_WIDTH_HEIGHT 0x1598#define DST_HEIGHT_WIDTH 0x143c +#define DST_OFFSET 0x1404#define SRC_CLUT_ADDRESS 0x1780#define SRC_CLUT_DATA 0x1784
@@ -381,4 +381,5 @@#define LVDS_PLL_CNTL 0x02d4#define TMDS_CRC 0x02a0 +#define TMDS_TRANSMITTER_CNTL 0x02a4#define RADEON_BASE_CODE 0x0f0b
@@ -407,9 +407,9 @@#define SCLK_CNTL 0x000d#define MPLL_CNTL 0x000e +#define MDLL_CKO 0x000f#define MCLK_CNTL 0x0012#define AGP_PLL_CNTL 0x000b#define PLL_TEST_CNTL 0x0013 -/* MCLK_CNTL bit constants */ #define FORCEON_MCLKA (1 << 16)
@@ -475,8 +475,15 @@#define CRTC_EXT_DISP_EN (1 << 24)#define CRTC_EN (1 << 25) +#define CRTC_DISP_REQ_EN_B (1 << 26)/* CRTC_STATUS bit constants */ #define CRTC_VBLANK 0x00000001 +/* CRTC2_GEN_CNTL bit constants */ +#define CRT2_ON (1 << 7) +#define CRTC2_DISPLAY_DIS (1 << 23) +#define CRTC2_EN (1 << 25) +#define CRTC2_DISP_REQ_EN_B (1 << 26) +/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ #define CUR_LOCK 0x80000000
@@ -524,12 +524,24 @@#define LVDS_PANEL_FORMAT (1 << 3)#define LVDS_EN (1 << 7) +#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 +#define LVDS_BL_MOD_LEVEL_SHIFT 8 +#define LVDS_BL_MOD_EN (1 << 16)#define LVDS_DIGON (1 << 18)#define LVDS_BLON (1 << 19)#define LVDS_SEL_CRTC2 (1 << 23) +#define LVDS_STATE_MASK \ + (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | \ + LVDS_EN | LVDS_DIGON | LVDS_BLON)/* LVDS_PLL_CNTL bit constatns */ #define HSYNC_DELAY_SHIFT 0x1c#define HSYNC_DELAY_MASK (0xf << 0x1c) +/* TMDS_TRANSMITTER_CNTL bit constants */ +#define TMDS_PLL_EN (1 << 0) +#define TMDS_PLLRST (1 << 1) +#define TMDS_RAN_PAT_RST (1 << 7) +#define ICHCSEL (1 << 28) +/* FP_HORZ_STRETCH bit constants */ #define HORZ_STRETCH_RATIO_MASK 0xffff
@@ -562,4 +562,5 @@#define DAC_CRC_EN 0x00080000#define DAC_MASK_ALL (0xff << 24) +#define DAC_EXPAND_MODE (1 << 14)#define DAC_VGA_ADR_EN (1 << 13)#define DAC_RANGE_CNTL (3 << 0)
@@ -743,4 +743,13 @@#define DP_SRC_HOST_BYTEALIGN 0x00000400 +/* MPLL_CNTL bit constants */ +#define MPLL_RESET 0x00000001 + +/* MDLL_CKO bit constants */ +#define MDLL_CKO__MCKOA_RESET 0x00000002 + +/* VCLK_ECP_CNTL constants */ +#define PIXCLK_ALWAYS_ONb 0x00000040 +#define PIXCLK_DAC_ALWAYS_ONb 0x00000080/* masks */