R5000 secondary cache support

I have (re)implimented R5000 secondary cache support as a board cache with the attached patch. Comments are welcome.

/Brian

Index: include/asm-mips/mipsregs.h
===================================================================
RCS file: /cvs/linux-mips/include/asm-mips/mipsregs.h,v retrieving revision 1.1.1.1
retrieving revision 1.2

diff -u -r1.1.1.1 -r1.2
@@ -376,6 +376,7 @@
 #define CONF_CM_CMASK			7
 #define CONF_DB				(1 <<  4)
 #define CONF_IB				(1 <<  5)
+#define CONF_SE 			(1 << 12)
 #define CONF_SC				(1 << 17)
 #define CONF_AC                         (1 << 23)
 #define CONF_HALT                       (1 << 25)

Index: include/asm-mips/cacheops.h
===================================================================
RCS file: /cvs/linux-mips/include/asm-mips/cacheops.h,v retrieving revision 1.1.1.1
retrieving revision 1.2

diff -u -r1.1.1.1 -r1.2
@@ -35,6 +35,7 @@
 #define Hit_Writeback_Inv_D	0x15
 					/* 0x16 is unused */
 #define Hit_Writeback_Inv_SD	0x17
+#define Page_Invalidate		0x17
 #define Hit_Writeback_I		0x18
 #define Hit_Writeback_D		0x19
 					/* 0x1a is unused */

Index: arch/mips/mm/c-r4k.c
===================================================================
RCS file: /cvs/linux-mips/arch/mips/mm/c-r4k.c,v
retrieving revision 1.1.1.1
retrieving revision 1.3

diff -u -r1.1.1.1 -r1.3
@@ -1457,6 +1457,8 @@
 	_dma_cache_inv = r4k_dma_cache_inv_sc;
 }
 
+extern void r5k_sc_init(void);
+
 typedef int (*probe_func_t)(unsigned long);
 
 static inline void __init setup_scache(unsigned int config)

@@ -1469,7 +1471,13 @@
 	sc_present = probe_scache_kseg1(config);
 
 	if (sc_present) {
-		setup_scache_funcs();
+#ifdef CONFIG_CPU_R5000
+		if (mips_cpu.cputype == CPU_R5000) {
+			setup_noscache_funcs();
+			r5k_sc_init();
+		} else
+#endif
+			setup_scache_funcs();
 		return;
 	}
 

Index: arch/mips/mm/r5k-sc.c
===================================================================
RCS file: arch/mips/mm/r5k-sc.c

Index: arch/mips/mm/Makefile
===================================================================
RCS file: /cvs/linux-mips/arch/mips/mm/Makefile,v
retrieving revision 1.1.1.1
retrieving revision 1.2

diff -u -r1.1.1.1 -r1.2
@@ -20,7 +20,8 @@
 obj-$(CONFIG_CPU_R4300)		+= pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o
 obj-$(CONFIG_CPU_R4X00)		+= pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o
 obj-$(CONFIG_CPU_VR41XX)	+= pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o
-obj-$(CONFIG_CPU_R5000)		+= pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o
+obj-$(CONFIG_CPU_R5000)		+= pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o \
+				   r5k-sc.o
 obj-$(CONFIG_CPU_NEVADA)	+= pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o
 obj-$(CONFIG_CPU_R5432)		+= pg-r5432.o c-r5432.o tlb-r4k.o tlbex-r4k.o
 obj-$(CONFIG_CPU_RM7000)	+= pg-rm7k.o c-rm7k.o tlb-r4k.o tlbex-r4k.o

Index: arch/mips/config.in
===================================================================
RCS file: /cvs/linux-mips/arch/mips/config.in,v
retrieving revision 1.1.1.1
retrieving revision 1.5

diff -u -r1.1.1.1 -r1.5
@@ -382,6 +395,10 @@
 	 MIPS32	CONFIG_CPU_MIPS32 \
 	 MIPS64	CONFIG_CPU_MIPS64" R4x00
 
+if [ "$CONFIG_CPU_R5000"  = "y" ]; then
+   define_bool CONFIG_BOARD_SCACHE y
+if
+  
 if [ "$CONFIG_CPU_MIPS32" = "y" ]; then
    define_bool CONFIG_CPU_HAS_PREFETCH y
    bool '  Support for Virtual Tagged I-cache' CONFIG_VTAG_ICACHE