new CPUID bit
Northwood P4's have one more bit in the CPUID processor info set: bit
31. Intel calls the feature PBE (Pending Break Enable).
The attached patch for the current BK kernel adds the necessary entry.
Signature · 3 lines
--------------. ,-. 444 Castro Street Ulrich Drepper \ ,-----------------' \ Mountain View, CA 94041 USA Red Hat `--' drepper at redhat.com `---------------------------
home/drepper/kernel/linux-2.5/arch/i386/kernel/cpu/proc.c renamed from home/drepper/kernel/linux-2.5/arch/i386/kernel/cpu/proc.c-save +1 -1
@@ -22,7 +22,7 @@"fpu" ,"vme" ,"de" ,"pse" ,"tsc" ,"msr" ,"pae" ,"mce" ,"cx8" ,"apic" ,NULL ,"sep" ,"mtrr" ,"pge" ,"mca" ,"cmov" ,"pat" ,"pse36" ,"pn" ,"clflush" ,NULL ,"dts" ,"acpi" ,"mmx" , -"fxsr" ,"sse" ,"sse2" ,"ss" ,"ht" ,"tm" ,"ia64" ,NULL , +"fxsr" ,"sse" ,"sse2" ,"ss" ,"ht" ,"tm" ,"ia64" ,"pbe" ,/* AMD-defined */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
Ulrich> Northwood P4's have one more bit in the CPUID processor info Ulrich> set: bit 31. Intel calls the feature PBE (Pending Break Ulrich> Enable).
For the curious, from <http://www.aceshardware.com/forum?read=80030620>:
Adrian> Bit 31 is PBE (Pending Break Enable) which you can find in the Adrian> latest P4 instruction manual (document 24547106, page Adrian> 159-162). To quote:
24547106> Pending Break Enable. The processor supports the use of the 24547106> FERR#/PBE# pin when the processor is in the stop-clock state 24547106> (STPCLK# is asserted) to signal the processor that an 24547106> interrupt is pending and that the processor should return to 24547106> normal operation to handle the interrupt. Bit 10 (PBE 24547106> enable) in the IA32_MISC_ENABLE MSR enables this capability.
-JimC
Quoted 9 lines · James H. Cloos Jr.
Ulrich> Northwood P4's have one more bit in the CPUID processor info Ulrich> set: bit 31. Intel calls the feature PBE (Pending Break Ulrich> Enable).
For the curious, from <http://www.aceshardware.com/forum?read=80030620>:
Adrian> Bit 31 is PBE (Pending Break Enable) which you can find in the Adrian> latest P4 instruction manual (document 24547106, page Adrian> 159-162). To quote:
A better reference for this stuff is (IMHO) AP-485, the "Intel Processor Identification and the CPUID Instruction" application note. It's regularly updated, and in this particular case, its description of CPUID with EAX=1 differs from the IA32 Volume 2 manual (245471xx) in two ways:
- EBX bit 31 is called "SBF", Signal Break on FERR.
- ECX is defined to contain additional feature flags. Currently only one is defined: ECX bit 10 is the "Context ID" feature for putting the L1 D-cache in adaptive or shared mode, which matters for hyper-threaded CPUs.
Supporting the new ECX feature flags in the kernel will require some surgery, since the current code assumes x86_capability[0] is Intel, [1] is AMD,
[2] is Transmeta, and [3] is for conflicting or synthesized feature flags. We either shift AMD etc down one index and put ECX in [1], or add a new index
[4] for ECX, or kludge the few ECX-defined features in [3].
/Mikael
Quoted 10 lines · Mikael Pettersson
A better reference for this stuff is (IMHO) AP-485, the "Intel Processor Identification and the CPUID Instruction" application note. It's regularly updated, and in this particular case, its description of CPUID with EAX=1 differs from the IA32 Volume 2 manual (245471xx) in two ways:
- EBX bit 31 is called "SBF", Signal Break on FERR.
- ECX is defined to contain additional feature flags. Currently only one is defined: ECX bit 10 is the "Context ID" feature for putting the L1 D-cache in adaptive or shared mode, which matters for hyper-threaded CPUs.
Quoted 5 lines
Supporting the new ECX feature flags in the kernel will require some surgery, since the current code assumes x86_capability[0] is Intel, [1] is AMD,
[2] is Transmeta, and [3] is for conflicting or synthesized feature flags. We either shift AMD etc down one index and put ECX in [1], or add a new index
[4] for ECX, or kludge the few ECX-defined features in [3].
Or we change it so we end up with something like..
x86_capability[0].standard and x86_capability[0].extended
Dave
Signature · 2 lines
| Dave Jones. http://www.codemonkey.org.uk | SuSE Labs