uboot newbie - tqm823 and memory conf question
Hi everybody,
I hope, somebody could help me with my question - and it might be a little bit OT.
I have TQM823L-50 modules, which have a 26bit address / 32 bit I/O external bus and I want to hook up external programmable logic, which acts as as a SRAM interface.
This is all still theoretical, so no bread board yet.
If I understand the MPC823 book correctly there already a "canned" memory engine available to "talk" to an SRAM.
Now:
- To which CS is that hooked up to?
- What needs to be done to the boot-loader - ppcboot|u-boot?
I would really appreciate some help there, since I am just supposed to setup the board for our HW guys.
Thanks
P.S. If it's too OT, then I'm sorry and please ignore
Signature · 1 line
Thomas Maenner
Quoted 3 lines · In message <[email protected]> you wrote:
I have TQM823L-50 modules, which have a 26bit address / 32 bit I/O external bus and I want to hook up external programmable logic, which
...
Quoted 2 lines
If I understand the MPC823 book correctly there already a "canned" memory engine available to "talk" to an SRAM.
...
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- To which CS is that hooked up to?
That's completely your own choice.
Well, not completely. The TQM8xxL modules use:
CS0 / CS1 for the 2 flash banks
CS2 for SDRAM
CS3 for the CAN controllers (if fit)
So depending if you have CAN on your modules or not you can chose form CS4...CS7 or from CS3...CS7.
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- What needs to be done to the boot-loader - ppcboot|u-boot?
Strictly speaking, nothing. You can set up the memroy controller for this CS whenever you need it, i. e. for example in the Linux deriver's init routine. However, if you want to access the memory under U-Boot, you should at least add appropriate definitions for CFG_BR?_PRELIM and CFG_OR?_PRELIM to your board's config file.
Quoted 2 lines
I would really appreciate some help there, since I am just supposed to setup the board for our HW guys.
Good luck.
Best regards,
Wolfgang Denk
Signature · 3 lines
Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd at denx.de See us @ Embedded World, Nuremberg, Feb 18-20, Hall 12.0 Booth 12-442
Thanks!
Quoted 12 lines · Wolfgang Denk
Quoted 3 lines · In message <[email protected]> you wrote:
I have TQM823L-50 modules, which have a 26bit address / 32 bit I/O external bus and I want to hook up external programmable logic, which
...
Quoted 2 lines
If I understand the MPC823 book correctly there already a "canned" memory engine available to "talk" to an SRAM.
...
Quoted 1 line
- To which CS is that hooked up to?
That's completely your own choice.
Quoted 9 lines
Well, not completely. The TQM8xxL modules use:
CS0 / CS1 for the 2 flash banks
CS2 for SDRAM
CS3 for the CAN controllers (if fit)So depending if you have CAN on your modules or not you can chose form CS4...CS7 or from CS3...CS7.
Well then, how does the CPU "know" about that area?
Meaning:
- Is the Address area on that bus the actual physical range the CPU sees?
- Or, does it get mapped into the CPUs physical space via configuration?
- How does the CPU know, that it is SRAM or something else?
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- What needs to be done to the boot-loader - ppcboot|u-boot?
Strictly speaking, nothing. You can set up the memroy controller for this CS whenever you need it, i. e. for example in the Linux deriver's init routine. However, if you want to access the memory under U-Boot, you should at least add appropriate definitions for CFG_BR?_PRELIM and CFG_OR?_PRELIM to your board's config file.
OK, I need to setup the mem controller.
(I don't need access during "boot-loader" time)
I will search in the source there.
Is that then still possible to change the mem controller setup when the kernel is already coming up?? I hope so!
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I would really appreciate some help there, since I am just supposed to setup the board for our HW guys.
Good luck.
Yeah, I need that :-)
Thanks for your help
Tom
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Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd at denx.de See us @ Embedded World, Nuremberg, Feb 18-20, Hall 12.0 Booth 12-442-------------------------------------------------------
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Quoted 1 line · In message <[email protected]> you wrote:
Thanks!
You're welcome.
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Quoted 3 lines
So depending if you have CAN on your modules or not you can chose form CS4...CS7 or from CS3...CS7.
Well then, how does the CPU "know" about that area?
Ummm... please read the memory controller section of the MPC8xx User's Manual.
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Meaning:
- Is the Address area on that bus the actual physical range the CPU sees?
Yes.
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- Or, does it get mapped into the CPUs physical space via configuration?
Yes.
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- How does the CPU know, that it is SRAM or something else?
It doesn't know, and it doesn't need to know. It just goes through the memory controller registers to find a BRx/ORx pair that matches the physical address, and then it accesses the corresponding CS according to the other params in BRx/ORx.
Not that the scanning always starts at BR0/OR0, so if you define overlapping memory regions always the first one will win.
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OK, I need to setup the mem controller.
Right.
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I will search in the source there.
What for? Just add it to your Linux device driver's init() code.
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Is that then still possible to change the mem controller setup when the kernel is already coming up?? I hope so!
It is. You can change it any time you like. There are several cases wher eit is changed on the fly (for example, some of the FPGA boot commands in U-Boot will mdify the memory controller programming for the load operation of the FPGA(s), and return to the "normal" setting later.
Viele Gr??e,
Best regards,
Wolfgang Denk
Signature · 3 lines
Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd at denx.de See us @ Embedded World, Nuremberg, Feb 18-20, Hall 12.0 Booth 12-442
OK, thanks again!
Quoted 12 lines · Wolfgang Denk
Quoted 1 line · In message <[email protected]> you wrote:
Thanks!
You're welcome.
Quoted 4 lines
Quoted 3 lines
So depending if you have CAN on your modules or not you can chose form CS4...CS7 or from CS3...CS7.
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Well then, how does the CPU "know" about that area?
Ummm... please read the memory controller section of the MPC8xx User's Manual.
Found it! Chapter 15. Digesting it...
---snip---
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- How does the CPU know, that it is SRAM or something else?
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It doesn't know, and it doesn't need to know. It just goes through the memory controller registers to find a BRx/ORx pair that matches the physical address, and then it accesses the corresponding CS according to the other params in BRx/ORx.
Not that the scanning always starts at BR0/OR0, so if you define overlapping memory regions always the first one will win.
Good info.
---snip---
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I will search in the source there.
What for? Just add it to your Linux device driver's
init()code.
If the "when" almost doesn't matter, it could be done there.
---snip---
Thanks a lot Wolfgang for your help!
Have a successful show in Nuremberg!
Signature · 1 line
Thomas Maenner