speedstep-piix4 don't work

The latest patch posted on this mailing list, against 2.4.21-ac4, doesn't work on my Thinkpad X20.

The CPU is a Speedstep capable P3@600MHz, whose clockspeed varies from 260 to 600 depending on BIOS settings and AC power (as reported during testing with speedstep-detect and bootup). speedstep-detect also catches a single bit GPO change when switching from AC to battery on boot, with BIOS settings at automatic defaults.

GPOs changes from 0x767bbfe to 0x767fbbff after disconnecting the AC. This should be gpo_hilo=0.

Calling modprobe speedstep-piix4 gpo_hilo=0 leaves dmesg saying cpufreq: changed failed.

Using the old speedstep_bx module on poupinou with gpo_hilo=0 yields the following (success) output on dmesg:
gpo_hilo: 0x34
gpo_hilo_shift: 0x0
frequency_high: 600000
frequency_low: 500000

I'd like to use the autospeedstep daemon for neat powersaving-ness so any assistance and troubleshooting would be appreciated.

(Incidentally, the patch posted leaves out a dependency of speedstep-lib.o - so I added it to the arch/i386/kernel/Makefile)

Could you please send me the dmesg output, with SPEEDSTEP_DEBUG enabled both in speedstep-piix4.c and speedstep-lib.c please?

Also, I would be happy to see the output of speedtep-detect

Cheers,

Ducrot Bruno

--  Which is worse:  ignorance or apathy?
--  Don't know.  Don't care.

AC plugged in:
dmi_scan: return:
DMI 2.3 present.
47 structures occupying 1685 bytes.
DMI table at 0x000DC010.
BIOS Vendor: IBM
BIOS Version: IZET99WW (2.21 )
BIOS Release: 10/19/2001
System Vendor: IBM
Product Name: 266235F
Version: Not Available
Board Vendor: IBM
Board Name: 266235F
Board Version: Not Available
Trying Intel's int15 GSIC:
BIOS support GSIC call:

       signature: GSIC
       command port = 0x00b2
       command =      0x0082
       event port =   0x00c000b3
       flags =        0x07d00000

probing chipsets: Found PIIX4
pmbase at 0x1000
Dumping PM IO register for this southbridge:
PMCNTRL (0x1004): 0x1401

(0x1006):         0x0000
GPEN (0x100e):    0x0a00
PCNTRL (0x1010):  0x00001200
(0x1016):         0x0000
DEVSTS (0x101c):  0x00000000
GLBLEN (0x1020):  0x0400
(0x1022):         0x00000000
GLBCTL (0x1028):  0x03011f05
DEVCTL (0x102c):  0x00200000
GPIs: (0x1030):   0x12b03a
(0x1033):         0x00
GPOs: (0x1034):   0x767fbbfe
(0x1038):         0x3a 0xb0 0x12 0x00 0xfe 0xbb 0x7f 0x76

You need to boot on AC and battery and see if GPOs change. Then, see if one bit change in between, you have then to note the number of this bit. This will be the gpo_hilo= number kernel option for enabling the speedstep-piix4 module under Linux.

                                     ..28..24..20..16..12...8...4...0
       GPOs: (0x1034):   0x767fbbfe  01110110011111111011101111111110

AC out:
dmi_scan: return:
DMI 2.3 present.
47 structures occupying 1685 bytes.
DMI table at 0x000DC010.
BIOS Vendor: IBM
BIOS Version: IZET99WW (2.21 )
BIOS Release: 10/19/2001
System Vendor: IBM
Product Name: 266235F
Version: Not Available
Board Vendor: IBM
Board Name: 266235F
Board Version: Not Available
Trying Intel's int15 GSIC:
BIOS support GSIC call:

       signature: GSIC
       command port = 0x00b2
       command =      0x0082
       event port =   0x00c000b3
       flags =        0x07d00000

probing chipsets: Found PIIX4
pmbase at 0x1000
Dumping PM IO register for this southbridge:
PMCNTRL (0x1004): 0x1401

(0x1006):         0x0000
GPEN (0x100e):    0x0a00
PCNTRL (0x1010):  0x00001200
(0x1016):         0x0000
DEVSTS (0x101c):  0x00000000
GLBLEN (0x1020):  0x0400
(0x1022):         0x00000000
GLBCTL (0x1028):  0x07019705
DEVCTL (0x102c):  0x00200000
GPIs: (0x1030):   0x12b03a
(0x1033):         0x00
GPOs: (0x1034):   0x767fbbff
(0x1038):         0x3a 0xb0 0x12 0x00 0xff 0xbb 0x7f 0x76

You need to boot on AC and battery and see if GPOs change. Then, see if one bit change in between, you have then to note the number of this bit. This will be the gpo_hilo= number kernel option for enabling the speedstep-piix4 module under Linux.

                                     ..28..24..20..16..12...8...4...0
       GPOs: (0x1034):   0x767fbbff  01110110011111111011101111111111

dmesg:

cpufreq: Coppermine: MSR_IA32_EBL_CR_POWERON is 0x44080020, 0x0
cpufreq: Coppermine: MSR_IA32_PLATFORM ID is 0x0, 0x2540000
speedstep-lib: P3 - MSR_IA32_EBL_CR_POWERON: 0x44080020 0x0
speedstep-lib: P3 - MSR_IA32_EBL_CR_POWERON: 0x44080020 0x0
cntb before: 0x000000e1
cntb after:  0x000007e1
pcntrl before: 0x00001200
pcntrl after:  0x00001804
speedstep-lib: P3 - MSR_IA32_EBL_CR_POWERON: 0x44080020 0x0
cpufreq: change failed
speedstep-lib: P3 - MSR_IA32_EBL_CR_POWERON: 0x44080020 0x0
speedstep-lib: P3 - MSR_IA32_EBL_CR_POWERON: 0x44080020 0x0
cntb before: 0x000000e1
cntb after:  0x000007e1
pcntrl before: 0x00001200
pcntrl after:  0x00001804
speedstep-lib: P3 - MSR_IA32_EBL_CR_POWERON: 0x44080020 0x0
cpufreq: change failed
speedstep-lib: P3 - MSR_IA32_EBL_CR_POWERON: 0x44080020 0x0

I can not promise you anything, but can you try the patch attached?

This also add a little bit more debug output (just to check that I do it ok for gpo stuff) and the fix may be in the lines that look like:

	pcntrl |= 1 << 9;               /* CC_EN = 1 */
and
	pcntrl |= (0x3 << 1);

@@ -123,9 +123,11 @@
 	/* read state */
 	value = inb_p(pmbase + gpo_hilo_port);
 
+	dprintk(KERN_DEBUG "speedstep: reading %.2x from port %.4x\n", value, pmbase + gpo_hilo_port);
 	/* compute new state */
 	value &= ~(1 << gpo_hilo_shift);
 	value |= state << gpo_hilo_shift;
+	dprintk(KERN_DEBUG "speedstep: new gpo value: 0x%.2x\n", value);
 
 	/* disable bus master arbitration */
 	pm2_blk = inb(0x22);

@@ -139,12 +141,12 @@
 	pcntrl |= 1 << 12;              /* STPCLK_EN = 1 */
 	pcntrl |= 1 << 11;              /* SLEEP_EN = 1 */
 	pcntrl &= ~(1 << 10);           /* BURST_EN = 0 */
-	pcntrl &= ~(1 << 9);            /* CC_EN = 0 */
+	pcntrl |= 1 << 9;               /* CC_EN = 1 */
 	pcntrl &= ~(1 << 4);            /* THT_EN = 0 */
 
 	/* We may have to define a 'good' throttling duty ? */
 	pcntrl &= ~(0x7 << 1);
-	pcntrl |= (0x2 << 1);
+	pcntrl |= (0x3 << 1);
 
 	dprintk(KERN_DEBUG "pcntrl before: 0x%.8x\n", pcntrl_save);
 	dprintk(KERN_DEBUG "pcntrl after:  0x%.8x\n", pcntrl);

@@ -323,7 +325,7 @@
 
 	gpo_hilo_port = 0x34 + (gpo_hilo / 8);
 	gpo_hilo_shift = (gpo_hilo % 8);
-
+	dprintk(KERN_INFO "speedstep: gpo port: 0x%.2x shift: 0x%.2x\n", gpo_hilo_port, gpo_hilo_shift);
 	return cpufreq_register_driver(&speedstep_driver);
 }
 

Ducrot Bruno

--  Which is worse:  ignorance or apathy?
--  Don't know.  Don't care.

Ok. Could you remove the lines:

    145         /* We may have to define a 'good' throttling duty ? */
    146         pcntrl &= ~(0x7 << 1);
    147         pcntrl |= (0x3 << 1);
    148 

That will done exactly the same stuff as the old independant kernel module. If that still do not work, well I will be a little puzzled then, but give me still dmesg in any case.

Ducrot Bruno

--  Which is worse:  ignorance or apathy?
--  Don't know.  Don't care.

I'm a different user than the original one which opened this thread.

I'm using a Thinkpad T20 with P3 Coppermine 750 MHz with Linux 2.4.21-ac4 and the latest CPUFREQ patch including your last fixes for 2.4.21-ac4.

I've enabled SPEEDSTEP_DEBUG in speedstep-piix4.c and speedstep-lib.c and I've added some lines for debugging output. When I load the speedstep-piix4 module I get the following output:

(speedstep-detect says that gpo_hilo bit is 0)

cpufreq: Coppermine: MSR_IA32_EBL_CR_POWERON is 0x47480020, 0x0
cpufreq: Coppermine: MSR_IA32_PLATFORM ID is 0x0, 0x6b560000
speedstep-lib: P3 - MSR_IA32_EBL_CR_POWERON: 0x47480020 0x0
speedstep-lib: P3 - MSR_IA32_EBL_CR_POWERON: 0x47480020 0x0 freq_old = 750000
cntb before: 0x000030e1
cntb after: 0x000037e1
pcntrl before: 0x00003200
pcntrl after: 0x00001a00
speedstep-lib: P3 - MSR_IA32_EBL_CR_POWERON: 0x46c80020 0x0 freqs.new = 600000

              ^^^^^^
    This is speedstep_get_processor_frequency(speedstep_processor);
    called in function speedstep_set_state() immediatly after

      /* cleanup southbridge */
      pci_write_config_dword(speedstep_chipset_dev, 0x48, cntb_save);

      /* enable IRQs */
      local_irq_restore(flags);

     So the first transition from 750 MHz to 600 MHz seems to work
     correctly.

speedstep-lib: P3 - MSR_IA32_EBL_CR_POWERON: 0x46c80020 0x0
cpufreq: change to 0 MHz succeded
speedstep-lib: P3 - MSR_IA32_EBL_CR_POWERON: 0x46c80020 0x0
speedstep-lib: P3 - MSR_IA32_EBL_CR_POWERON: 0x46c80020 0x0 freq_old = 600000
cntb before: 0x000030e1
cntb after: 0x000037e1
pcntrl before: 0x00003200
pcntrl after: 0x00001a00
speedstep-lib: P3 - MSR_IA32_EBL_CR_POWERON: 0x46c80020 0x0 freqs.new = 600000
^^^^^^
But the second transition fails.

speedstep-lib: P3 - MSR_IA32_EBL_CR_POWERON: 0x46c80020 0x0
cpufreq: change failed
speedstep-lib: P3 - MSR_IA32_EBL_CR_POWERON: 0x46c80020 0x0 low_speed = high_speed = 600000

Any ideas? I still had no success with CPUFREQ on this T20 since I'm not using Linux 2.5.

Frank

## Dept. of Computer Science, Dresden University of Technology, Germany ##
## http://os.inf.tu-dresden.de/~fm3                                     ##

On Fri, Jul 11, 2003 at 05:11:09PM +0200, Frank Mehnert wrote:
Content-Description: signed data

Please test attached patch. (Shame on me).

Index: speedstep-piix4.c
===================================================================
RCS file: /mnt/src/cvsroot/cpufreq/linux/arch/i386/kernel/cpufreq/speedstep-piix4.c,v retrieving revision 1.6

diff -u -r1.6 speedstep-piix4.c
@@ -124,8 +124,9 @@
 	value = inb_p(pmbase + gpo_hilo_port);
 
 	/* compute new state */
-	value &= ~(1 << gpo_hilo_shift);
-	value |= state << gpo_hilo_shift;
+	value = state ? (value | (1 << gpo_hilo_shift)) : \
+		        (value & ~(1 << gpo_hilo_shift));
+
 
 	/* disable bus master arbitration */
 	pm2_blk = inb(0x22);

Ducrot Bruno

--  Which is worse:  ignorance or apathy?
--  Don't know.  Don't care.