(MIPS) Support for all dbau1x00 boards

Use different configurations for the boards from
AMD ( dbau1000, dbau1100 and dbau1500 ).

Only tested for dbau1000, but compiles for all three.

Users with dbau1100 and dbau1500 should check that the cpu is compatible with au1000.

* Patch by Thomas Lange 14 Oct 2003
Split dbau1x00 into dbau1000, dbau1100 and dbau1500 configs

/Thomas
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According to the Au1500 manual, differences between Au1500 and Au1000 are:

<quote>

The Au1500 processor does not have the following peripherals that are present on the Au1000 processor:

IrDA
UART1
UART2
SSI
I2S

The Au1500 processor has added these functions not present on the Au1000 processor:

PCI 2.2 compliant interface
Genereal-purpose I/O (GPIO): 32 total, 22 dedicated. (Au1000 has 32 total, 5 dedicated)

The NIC base address has changed from 0x010500000 to 0x11500000.

Some inputs to the interrupt controller have changed due to the addion/removal of blocks. Refer to the interrupt controller section for the Au1500 processor interrupt map.

A new CCA encoding has been added to the Au1500 processor. If CCA==4, all system bus accesses will be cacheline aligned, i.e. no cacheline wrapping is supported. When the PCI Cacheable Memory space is used, it must be mapped to CCA==4.

JTAG memory overlay of the PCI boot memory is not supported.

</quote>

As soon as my BDI2000 arrives I will begin more thorough testing on the Au1500.

Ed Okerson

Added, thanks. Sorry this took so long.

Best regards,

Wolfgang Denk

Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd at denx.de
The only person who always got his work done by Friday
                                                 was Robinson Crusoe.