clk: add BCM63268 timer clock and reset

drivers/clk/bcm/clk-bcm63268-timer.c new file +3 -0

new file mode 100644
index 000000000000..6a1fdd193cb5
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * BCM63268 Timer Clock and Reset Controller Driver

drivers/clk/bcm/clk-bcm63268-timer.c new file +6 -0

+
+static inline struct bcm63268_tclkrst_hw *
+to_bcm63268_timer_reset(struct reset_controller_dev *rcdev)
+{
+       return container_of(rcdev, struct bcm63268_tclkrst_hw, rcdev);
+}

drivers/clk/bcm/clk-bcm63268-timer.c new file +5 -0

+       spin_unlock_irqrestore(&reset->lock, flags);
+
+       return 0;
+}
+

drivers/clk/bcm/clk-bcm63268-timer.c new file +16 -0

+       if (!table)
+               return -EINVAL;
+
+       for (entry = table; entry->name; entry++)
+               maxbit = max(maxbit, entry->bit);
+       maxbit++;
+
+       hw = devm_kzalloc(&pdev->dev, struct_size(hw, data.hws, maxbit),
+                         GFP_KERNEL);
+       if (!hw)
+               return -ENOMEM;
+
+       platform_set_drvdata(pdev, hw);
+
+       spin_lock_init(&hw->lock);
+

drivers/clk/bcm/clk-bcm63268-timer.c new file +18 -0

+                                          hw->regs, entry->bit,
+                                          CLK_GATE_BIG_ENDIAN, &hw->lock);
+               if (IS_ERR(clk)) {
+                       ret = PTR_ERR(clk);
+                       goto out_err;
+               }
+
+               hw->data.hws[entry->bit] = clk;
+       }
+
+       ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+                                         &hw->data);
+       if (ret)
+               return ret;
+
+       hw->rcdev.of_node = dev->of_node;
+       hw->rcdev.ops = &bcm63268_timer_reset_ops;
+

drivers/clk/bcm/clk-bcm63268-timer.c new file +5 -0

+       }, {
+               /* sentinel */
+       }
+};
+

Quoting Álvaro Fernández Rojas (2023-03-21 13:10:22)

Quoted 9 lines

drivers/clk/bcm/clk-bcm63268-timer.c new file +3 -0

new file mode 100644
index 000000000000..6a1fdd193cb5
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * BCM63268 Timer Clock and Reset Controller Driver

[...]

Quoted 11 lines

drivers/clk/bcm/clk-bcm63268-timer.c new file +11 -0

+
+static inline struct bcm63268_tclkrst_hw *
+to_bcm63268_timer_reset(struct reset_controller_dev *rcdev)
+{
+       return container_of(rcdev, struct bcm63268_tclkrst_hw, rcdev);
+}
+
+static int bcm63268_timer_reset_update(struct reset_controller_dev *rcdev,
+                               unsigned long id, bool assert)
+{
+       struct bcm63268_tclkrst_hw *reset = to_bcm63268_timer_reset(rcdev);

drivers/clk/bcm/clk-bcm63268-timer.c line 90

Quoted 5 lines

drivers/clk/bcm/clk-bcm63268-timer.c new file +5 -0

+       unsigned long flags;
+       uint32_t val;
+
+       spin_lock_irqsave(&reset->lock, flags);
+       val = __raw_readl(reset->regs);

Use regular ol readl() here, unless you have some need for no barrires or byte swapping.

Quoted 22 lines

Quoting Álvaro Fernández Rojas (2023-03-21 13:10:22)

Quoted 9 lines

drivers/clk/bcm/clk-bcm63268-timer.c new file +3 -0

new file mode 100644
index 000000000000..6a1fdd193cb5
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * BCM63268 Timer Clock and Reset Controller Driver

[...]

Quoted 11 lines

drivers/clk/bcm/clk-bcm63268-timer.c new file +11 -0

+
+static inline struct bcm63268_tclkrst_hw *
+to_bcm63268_timer_reset(struct reset_controller_dev *rcdev)
+{
+       return container_of(rcdev, struct bcm63268_tclkrst_hw, rcdev);
+}
+
+static int bcm63268_timer_reset_update(struct reset_controller_dev *rcdev,
+                               unsigned long id, bool assert)
+{
+       struct bcm63268_tclkrst_hw *reset = to_bcm63268_timer_reset(rcdev);

Quoted 8 lines

drivers/clk/bcm/clk-bcm63268-timer.c line 90

Quoted 5 lines

drivers/clk/bcm/clk-bcm63268-timer.c new file +5 -0

+       unsigned long flags;
+       uint32_t val;
+
+       spin_lock_irqsave(&reset->lock, flags);
+       val = __raw_readl(reset->regs);

Use regular ol readl() here, unless you have some need for no barrires or byte swapping.

These SoCs are big-endian, require native endian register access and have no posted writes within their bus logic (UBUS) and require no barriers, hence the use of __raw_readl() and __raw_writel() is adequate.

Quoting Florian Fainelli (2023-03-21 16:00:29)

Quoted 32 lines · Stephen Boyd

Quoted 30 lines

Quoting Álvaro Fernández Rojas (2023-03-21 13:10:22)

Quoted 9 lines

drivers/clk/bcm/clk-bcm63268-timer.c new file +3 -0

new file mode 100644
index 000000000000..6a1fdd193cb5
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * BCM63268 Timer Clock and Reset Controller Driver

[...]

Quoted 6 lines

drivers/clk/bcm/clk-bcm63268-timer.c new file +6 -0

+
+static inline struct bcm63268_tclkrst_hw *
+to_bcm63268_timer_reset(struct reset_controller_dev *rcdev)
+{
+       return container_of(rcdev, struct bcm63268_tclkrst_hw, rcdev);
+}

drivers/clk/bcm/clk-bcm63268-timer.c line 90

Quoted 10 lines

drivers/clk/bcm/clk-bcm63268-timer.c new file +10 -0

+
+static int bcm63268_timer_reset_update(struct reset_controller_dev *rcdev,
+                               unsigned long id, bool assert)
+{
+       struct bcm63268_tclkrst_hw *reset = to_bcm63268_timer_reset(rcdev);
+       unsigned long flags;
+       uint32_t val;
+
+       spin_lock_irqsave(&reset->lock, flags);
+       val = __raw_readl(reset->regs);

Use regular ol readl() here, unless you have some need for no barrires or byte swapping.

Quoted 4 lines

These SoCs are big-endian, require native endian register access and have no posted writes within their bus logic (UBUS) and require no barriers, hence the use of __raw_readl() and __raw_writel() is adequate.

Use ioread32be() then?

Quoted 7 lines

Quoting Florian Fainelli (2023-03-21 16:00:29)

Quoted 5 lines

These SoCs are big-endian, require native endian register access and have no posted writes within their bus logic (UBUS) and require no barriers, hence the use of __raw_readl() and __raw_writel() is adequate.

Quoted 1 line

Use ioread32be() then?

BCM63xx drivers tend to use __raw_{read,write}l for consistency and to make it clear that no barriers, no endian swapping is necessary, I would prefer to remain consistent with that convention.

Quoting Florian Fainelli (2023-03-21 16:09:54)

Quoted 8 lines · Stephen Boyd

Quoted 7 lines

Quoting Florian Fainelli (2023-03-21 16:00:29)

Quoted 5 lines

These SoCs are big-endian, require native endian register access and have no posted writes within their bus logic (UBUS) and require no barriers, hence the use of __raw_readl() and __raw_writel() is adequate.

Quoted 5 lines

Quoted 1 line

Use ioread32be() then?

BCM63xx drivers tend to use __raw_{read,write}l for consistency and to make it clear that no barriers, no endian swapping is necessary, I would prefer to remain consistent with that convention.

Ok.

Is the clk device big-endian? Or the CPU is big-endian? SoC being big-endian sounds like the devices in the SoC are big-endian. I hope we never plop this device down with a CPU that's litle-endian.

Quoting Florian Fainelli (2023-03-21 16:09:54)

Quoted 8 lines · Stephen Boyd

Quoted 7 lines

Quoting Florian Fainelli (2023-03-21 16:00:29)

Quoted 5 lines

These SoCs are big-endian, require native endian register access and have no posted writes within their bus logic (UBUS) and require no barriers, hence the use of __raw_readl() and __raw_writel() is adequate.

Quoted 5 lines

Quoted 1 line

Use ioread32be() then?

BCM63xx drivers tend to use __raw_{read,write}l for consistency and to make it clear that no barriers, no endian swapping is necessary, I would prefer to remain consistent with that convention.

Ok.

Is the clk device big-endian? Or the CPU is big-endian? SoC being big-endian sounds like the devices in the SoC are big-endian. I hope we never plop this device down with a CPU that's litle-endian.

Broadcom BCM63268 has a timer clock and reset controller which has the following layout:

  #define POR_RESET_STATUS            (1 << 31)
  #define HW_RESET_STATUS             (1 << 30)
  #define SW_RESET_STATUS             (1 << 29)
  #define USB_REF_CLKEN               (1 << 18)
  #define UTO_EXTIN_CLKEN             (1 << 17)
  #define UTO_CLK50_SEL               (1 << 16)
  #define FAP2_PLL_CLKEN              (1 << 15)
  #define FAP2_PLL_FREQ_SHIFT         12
  #define FAP1_PLL_CLKEN              (1 << 11)
  #define FAP1_PLL_FREQ_SHIFT         8
  #define WAKEON_DSL                  (1 << 7)
  #define WAKEON_EPHY                 (1 << 6)
  #define DSL_ENERGY_DETECT_ENABLE    (1 << 4)

#define GPHY_1_ENERGY_DETECT_ENABLE (1 << 3)
#define EPHY_3_ENERGY_DETECT_ENABLE (1 << 2)
#define EPHY_2_ENERGY_DETECT_ENABLE (1 << 1)
#define EPHY_1_ENERGY_DETECT_ENABLE (1 << 0)

Also excuse me for the delay in the v3, but I totally forgot about this...

Quoting Álvaro Fernández Rojas (2023-03-21 13:10:18)

Quoted 20 lines

Broadcom BCM63268 has a timer clock and reset controller which has the following layout:

  #define POR_RESET_STATUS            (1 << 31)
  #define HW_RESET_STATUS             (1 << 30)
  #define SW_RESET_STATUS             (1 << 29)
  #define USB_REF_CLKEN               (1 << 18)
  #define UTO_EXTIN_CLKEN             (1 << 17)
  #define UTO_CLK50_SEL               (1 << 16)
  #define FAP2_PLL_CLKEN              (1 << 15)
  #define FAP2_PLL_FREQ_SHIFT         12
  #define FAP1_PLL_CLKEN              (1 << 11)
  #define FAP1_PLL_FREQ_SHIFT         8
  #define WAKEON_DSL                  (1 << 7)
  #define WAKEON_EPHY                 (1 << 6)
  #define DSL_ENERGY_DETECT_ENABLE    (1 << 4)

#define GPHY_1_ENERGY_DETECT_ENABLE (1 << 3)
#define EPHY_3_ENERGY_DETECT_ENABLE (1 << 2)
#define EPHY_2_ENERGY_DETECT_ENABLE (1 << 1)
#define EPHY_1_ENERGY_DETECT_ENABLE (1 << 0)

Quoted 1 line

Also excuse me for the delay in the v3, but I totally forgot about this...

Please don't send as a reply to a previous round. It makes applying the patch series more difficult and buries the new series deep down in the mail thread.