x86/mce: Add Zhaoxin MCE support
Subsystems (3)
PATCH v2 1/4 x86/mce: Add Zhaoxin MCE support
All Zhaoxin newer CPUs support MCE that compatible with Intel's "Machine-Check Architecture", so add support for Zhaoxin MCE in mce/core.c.
--- arch/x86/kernel/cpu/mce/core.c | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-)
arch/x86/kernel/cpu/mce/core.c +24 -6
@@ -488,8 +488,9 @@ int mce_usable_address(struct mce *m)if (!(m->status &MCI_STATUS_ADDRV ))return 0 ; -/* Checks after this one are Intel-specific: */ -if (boot_cpu_data.x86_vendor !=X86_VENDOR_INTEL ) +/* Checks after this one are Intel/Zhaoxin-specific: */ +if (boot_cpu_data.x86_vendor !=X86_VENDOR_INTEL && + boot_cpu_data.x86_vendor !=X86_VENDOR_ZHAOXIN )return 1 ;if (!(m->status &MCI_STATUS_MISCV ))
@@ -510,7 +511,8 @@ bool mce_is_memory_error(struct mce *m)if (m->cpuvendor ==X86_VENDOR_AMD || m->cpuvendor ==X86_VENDOR_HYGON ) {return amd_mce_is_memory_error (m); - }else if (m->cpuvendor ==X86_VENDOR_INTEL ) { + }else if (m->cpuvendor ==X86_VENDOR_INTEL || + m->cpuvendor ==X86_VENDOR_ZHAOXIN ) {/* * Intel SDM Volume 3B - 15.9.2 Compound Error Codes *
@@ -1697,6 +1699,21 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)if (c->x86 ==6 && c->x86_model ==45 ) quirk_no_way_out = quirk_sandybridge_ifu; } + +if (c->x86_vendor ==X86_VENDOR_ZHAOXIN ) { +/* +* All newer Zhaoxin CPUs support MCE broadcasting. Enable +* synchronization with a one second timeout. +*/ +if ((c->x86 ==6 && c->x86_model ==0x19 && + (c->x86_stepping >3 && c->x86_stepping <8 )) || + (c->x86 ==6 && c->x86_model ==0x1f ) || + c->x86 >6 ) { +if (cfg->monarch_timeout <0 ) + cfg->monarch_timeout =USEC_PER_SEC ; + } + } +if (cfg->monarch_timeout <0 ) cfg->monarch_timeout =0 ;if (cfg->bootlog !=0 )
@@ -2014,15 +2031,16 @@ static void mce_disable_error_reporting(void)static void vendor_disable_error_reporting (void ) {/* -* Don't clear on Intel or AMD or Hygon CPUs. Some of these MSRs -* are socket-wide. +* Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these +* MSRs are socket-wide. * Disabling them for just a single offlined CPU is bad, since it will * inhibit reporting for all shared resources on the socket like the * last level cache (LLC), the integrated memory controller (iMC), etc. */ if (boot_cpu_data.x86_vendor ==X86_VENDOR_INTEL || boot_cpu_data.x86_vendor ==X86_VENDOR_HYGON || - boot_cpu_data.x86_vendor ==X86_VENDOR_AMD ) + boot_cpu_data.x86_vendor ==X86_VENDOR_AMD || + boot_cpu_data.x86_vendor ==X86_VENDOR_ZHAOXIN )return ;mce_disable_error_reporting ();
Signature · 1 line
2.7.4
Borislav Petkov
maintainerQuoted 26 lines · Tony W Wang-oc
All Zhaoxin newer CPUs support MCE that compatible with Intel's "Machine-Check Architecture", so add support for Zhaoxin MCE in
mce/core.c.Signed-off-by Tony W Wang-oc <[email protected]>--- arch/x86/kernel/cpu/mce/core.c | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-)arch/x86/kernel/cpu/mce/core.c +3
-2@@ -488,8 +488,9 @@ int mce_usable_address(struct mce *m)if (!(m->status &MCI_STATUS_ADDRV ))return 0 ; -/* Checks after this one are Intel-specific: */ -if (boot_cpu_data.x86_vendor !=X86_VENDOR_INTEL ) +/* Checks after this one are Intel/Zhaoxin-specific: */ +if (boot_cpu_data.x86_vendor !=X86_VENDOR_INTEL && + boot_cpu_data.x86_vendor !=X86_VENDOR_ZHAOXIN )return 1 ;if (!(m->status &MCI_STATUS_MISCV ))
arch/x86/kernel/cpu/mce/core.c bool mce_is_memory_error(struct mce *m) · line 518
Quoted 9 lines
arch/x86/kernel/cpu/mce/core.c +2
-1@@ -510,7 +511,8 @@ bool mce_is_memory_error(struct mce *m)if (m->cpuvendor ==X86_VENDOR_AMD || m->cpuvendor ==X86_VENDOR_HYGON ) {return amd_mce_is_memory_error (m); - }else if (m->cpuvendor ==X86_VENDOR_INTEL ) { + }else if (m->cpuvendor ==X86_VENDOR_INTEL || + m->cpuvendor ==X86_VENDOR_ZHAOXIN ) {/* * Intel SDM Volume 3B - 15.9.2 Compound Error Codes *
Make that a switch-case for better readability pls.
Quoted 4 lines
arch/x86/kernel/cpu/mce/core.c +0
-0@@ -1697,6 +1699,21 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)if (c->x86 ==6 && c->x86_model ==45 ) quirk_no_way_out = quirk_sandybridge_ifu; }
arch/x86/kernel/cpu/mce/core.c static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) · line 1711
Quoted 10 lines
arch/x86/kernel/cpu/mce/core.c +10
-0+ +if (c->x86_vendor ==X86_VENDOR_ZHAOXIN ) { +/* +* All newer Zhaoxin CPUs support MCE broadcasting. Enable +* synchronization with a one second timeout. +*/ +if ((c->x86 ==6 && c->x86_model ==0x19 && + (c->x86_stepping >3 && c->x86_stepping <8 )) || + (c->x86 ==6 && c->x86_model ==0x1f ) || + c->x86 >6 ) {
Can this be simplified into maybe something like this:
if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f))
this is, of course, assuming that Zhaoxin doesn't do family < 6 and that the other steppings for model 0x19 don't matter because they don't exist or so...
Signature · 4 lines
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquetteQuoted 25 lines · Borislav Petkov
Quoted 24 lines · Tony W Wang-oc
All Zhaoxin newer CPUs support MCE that compatible with Intel's "Machine-Check Architecture", so add support for Zhaoxin MCE in
mce/core.c.Signed-off-by Tony W Wang-oc <[email protected]>--- arch/x86/kernel/cpu/mce/core.c | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-)arch/x86/kernel/cpu/mce/core.c +3
-2@@ -488,8 +488,9 @@ int mce_usable_address(struct mce *m)if (!(m->status &MCI_STATUS_ADDRV ))return 0 ; -/* Checks after this one are Intel-specific: */ -if (boot_cpu_data.x86_vendor !=X86_VENDOR_INTEL ) +/* Checks after this one are Intel/Zhaoxin-specific: */ +if (boot_cpu_data.x86_vendor !=X86_VENDOR_INTEL && + boot_cpu_data.x86_vendor !=X86_VENDOR_ZHAOXIN )return 1 ;
Quoted 13 lines
arch/x86/kernel/cpu/mce/core.c bool mce_is_memory_error(struct mce *m) · line 518
Quoted 11 lines
arch/x86/kernel/cpu/mce/core.c +2
-1if (!(m->status &MCI_STATUS_MISCV ))@@ -510,7 +511,8 @@ bool mce_is_memory_error(struct mce *m)if (m->cpuvendor ==X86_VENDOR_AMD || m->cpuvendor ==X86_VENDOR_HYGON ) {return amd_mce_is_memory_error (m); - }else if (m->cpuvendor ==X86_VENDOR_INTEL ) { + }else if (m->cpuvendor ==X86_VENDOR_INTEL || + m->cpuvendor ==X86_VENDOR_ZHAOXIN ) {/* * Intel SDM Volume 3B - 15.9.2 Compound Error Codes * Make that a switch-case for better readability pls.
Ok.
Quoted 19 lines
arch/x86/kernel/cpu/mce/core.c static int __mcheck_cpu_apply_quirks(struct
Quoted 2 lines
arch/x86/kernel/cpu/mce/core.c +0
-0@@ -1697,6 +1699,21 @@ static int __mcheck_cpu_apply_quirks(struct
cpuinfo_x86*c)arch/x86/kernel/cpu/mce/core.c static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) · line 1711
Quoted 13 lines
arch/x86/kernel/cpu/mce/core.c +10
-0if (c->x86 ==6 && c->x86_model ==45 ) quirk_no_way_out = quirk_sandybridge_ifu; } + +if (c->x86_vendor ==X86_VENDOR_ZHAOXIN ) { +/* +* All newer Zhaoxin CPUs support MCE broadcasting. Enable +* synchronization with a one second timeout. +*/ +if ((c->x86 ==6 && c->x86_model ==0x19 && + (c->x86_stepping >3 && c->x86_stepping <8 )) || + (c->x86 ==6 && c->x86_model ==0x1f ) || + c->x86 >6 ) {Can this be simplified into maybe something like this:
Quoted 6 lines
if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f))this is, of course, assuming that Zhaoxin doesn't do family < 6 and that the other steppings for model
0x19don't matter because they don't exist or so...
Yes, Zhaoxin doesn't do family<6, and the other steppings for model 0x19 doesn't have MCA. So will simplified like this:
if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f))
Sincerely
TonyWWang-oc