Skip to contentSkip to conversation

non maskable interrupt reentrancy fixes for OPAL

PATCH In review Nicholas Piggin 2 participants 4 messages May 1, 2017 – May 30, 2017 PowerPC

lore
Share & tools
lore

Nicholas Piggin

author reviewer
#0 lore raw

cover non maskable interrupt reentrancy fixes for OPAL

Hi,

These fixes are more minimal, and split up properly since last post. Also accounted for Ben's comment of using HSRRs rather than disabling RI for OPAL_CALL.

This will still increase cost of opal calls a bit due to new mtmsr in FIXUP_ENDIAN return.

I have a few more patches that reduce overhead quite a bit, but they won't be suitable for 4.12, so I'll send those out after merge window.

Thanks,
Nick

Nicholas Piggin (2):
powerpc/64s: Fix FIXUP_ENDIAN non-maskable interrupt reentrancy powerpc/64s: Fix OPAL_CALL non-maskable interrupt reentrancy

 arch/powerpc/boot/ppc_asm.h                    | 12 +++++++-----
 arch/powerpc/include/asm/ppc_asm.h             | 11 +++++++----
 arch/powerpc/platforms/powernv/opal-wrappers.S |  6 +++---
 3 files changed, 17 insertions(+), 12 deletions(-)
Signature · 1 line
2.11.0
author reviewer
#1 lore raw

PATCH 1/2 powerpc/64s: Fix FIXUP_ENDIAN non-maskable interrupt reentrancy

FIXUP_ENDIAN uses SRR[01] with MSR_RI=1, which gets corrupted if there is an interleaving system reset or machine check interrupt.

Set MSR_RI=0 before setting SRRs. The rfid will restore MSR.

Signed-off-by Nicholas Piggin <[email protected]>
---
 arch/powerpc/boot/ppc_asm.h        | 12 +++++++-----
 arch/powerpc/include/asm/ppc_asm.h | 11 +++++++----
 2 files changed, 14 insertions(+), 9 deletions(-)
arch/powerpc/boot/ppc_asm.h +7 -5
index b03373d8b386..68e388ee94fe 100644
@@ -67,13 +67,15 @@
 #define MSR_LE		0x0000000000000001
 
 #define FIXUP_ENDIAN						   \
-	tdi   0, 0, 0x48; /* Reverse endian of b . + 8		*/ \
-	b     $+36;	  /* Skip trampoline if endian is good	*/ \
-	.long 0x05009f42; /* bcl 20,31,$+4			*/ \
-	.long 0xa602487d; /* mflr r10				*/ \
-	.long 0x1c004a39; /* addi r10,r10,28			*/ \
+	tdi   0,0,0x48;	  /* Reverse endian of b . + 8		*/ \
+	b     $+44;	  /* Skip trampoline if endian is good	*/ \
 	.long 0xa600607d; /* mfmsr r11				*/ \
 	.long 0x01006b69; /* xori r11,r11,1			*/ \
+	.long 0x00004039; /* li r10,0				*/ \
+	.long 0x6401417d; /* mtmsrd r10,1			*/ \
+	.long 0x05009f42; /* bcl 20,31,$+4			*/ \
+	.long 0xa602487d; /* mflr r10				*/ \
+	.long 0x14004a39; /* addi r10,r10,20			*/ \
 	.long 0xa6035a7d; /* mtsrr0 r10				*/ \
 	.long 0xa6037b7d; /* mtsrr1 r11				*/ \
 	.long 0x2400004c  /* rfid				*/
arch/powerpc/include/asm/ppc_asm.h +7 -4
index 359c44341761..6baeeb9acd0d 100644
@@ -770,15 +770,18 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #else
 #define FIXUP_ENDIAN						   \
 	tdi   0,0,0x48;	  /* Reverse endian of b . + 8		*/ \
-	b     $+36;	  /* Skip trampoline if endian is good	*/ \
-	.long 0x05009f42; /* bcl 20,31,$+4			*/ \
-	.long 0xa602487d; /* mflr r10				*/ \
-	.long 0x1c004a39; /* addi r10,r10,28			*/ \
+	b     $+44;	  /* Skip trampoline if endian is good	*/ \
 	.long 0xa600607d; /* mfmsr r11				*/ \
 	.long 0x01006b69; /* xori r11,r11,1			*/ \
+	.long 0x00004039; /* li r10,0				*/ \
+	.long 0x6401417d; /* mtmsrd r10,1			*/ \
+	.long 0x05009f42; /* bcl 20,31,$+4			*/ \
+	.long 0xa602487d; /* mflr r10				*/ \
+	.long 0x14004a39; /* addi r10,r10,20			*/ \
 	.long 0xa6035a7d; /* mtsrr0 r10				*/ \
 	.long 0xa6037b7d; /* mtsrr1 r11				*/ \
 	.long 0x2400004c  /* rfid				*/
+
 #endif /* !CONFIG_PPC_BOOK3E */
 
 #endif /*  __ASSEMBLY__ */
Signature · 1 line
2.11.0
#2 lore raw

Re: [1/2] powerpc/64s: Fix FIXUP_ENDIAN non-maskable interrupt reentrancy

Quoted 6 lines · Nicholas Piggin

FIXUP_ENDIAN uses SRR[01] with MSR_RI=1, which gets corrupted if there is an interleaving system reset or machine check interrupt.

Set MSR_RI=0 before setting SRRs. The rfid will restore MSR.

Signed-off-by Nicholas Piggin <[email protected]>

Series applied to powerpc next, thanks.

https://git.kernel.org/powerpc/c/f1fe5252018075e18d7f0c0e23ee17

cheers

author reviewer
#3 lore raw

PATCH 2/2 powerpc/64s: Fix OPAL_CALL non-maskable interrupt reentrancy

In reply to Nicholas Piggin

OPAL_CALL uses SRR[01] with MSR_RI=1, which gets corrupted if there is an interleaving system reset or machine check interrupt.

Use HSRR[01] instead, which does not require MSR_RI=0.

Signed-off-by Nicholas Piggin <[email protected]>
---
 arch/powerpc/platforms/powernv/opal-wrappers.S | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
arch/powerpc/platforms/powernv/opal-wrappers.S +3 -3
index f620572f891f..4ca6c26a56d5 100644
@@ -99,10 +99,10 @@ opal_return:
 	lwz	r4,8(r1);
 	ld	r5,PPC_LR_STKOFF(r1);
 	ld	r6,PACASAVEDMSR(r13);
-	mtspr	SPRN_SRR0,r5;
-	mtspr	SPRN_SRR1,r6;
 	mtcr	r4;
-	rfid
+	mtspr	SPRN_HSRR0,r5;
+	mtspr	SPRN_HSRR1,r6;
+	hrfid
 
 opal_real_call:
 	mfcr	r11
Signature · 1 line
2.11.0