MPC5200: Remove CSBOOT / CS0 configuration from start.S

Hello,

the attached patch fixes the problem that the current start.S for MPC5200 contains code to initialize CSBOOT / CS0 timing, bus width and other configuration.

       lis     r3,     0x00047800 at h
       ori     r3, r3, 0x00047800 at l
       stw     r3, 0x300(r4)           /* set timing, CS0/boot conf reg */

Right now that only works because all U-Boot supported MPC5200 boards are very Lite5200 (aka IceCube 5200) like. Once there is a board which's Flash is is connected in 24 bits address, 8 bits data, non-multiplexed mode this will break.

Additionally, the patch removes enabling of the IPBI wait states. This is not needed because IP bus is not configured to run with > 66 MHz in U-Boot and if needed this should be done always and not only when performing a low boot.

Interesting enough U-Boot already has a solution for setting tuned CS0 timings. This is done using the CFG_BOOTCS_CFG define which is applied in cpu/mpc5xxx/cpu_init.c.

Regards
Mark Jonas

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Dear Mark,

Thanks, applied.

Best regards,

Wolfgang Denk

Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd at denx.de
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