mf visibility
What is the meaning of memory access visibility (i.e. mf, rel, acq)? Are memory access with deferred response phase visible? For non-deferred responses which bus phase determines visibility (i.e. bus phase prior to data phase)?
If there is a more appropriatte news group please let me know.
- mario
Quoted 5 lines · Mario Smarduch
What is the meaning of memory access visibility (i.e. mf, rel, acq)? Are memory access with deferred response phase visible? For non-deferred responses which bus phase determines visibility (i.e. bus phase prior to data phase)?
On the Itanium 2 processor these ordering constraints are enforced at the L2 level (while deciding which requests to issue from the L2 OzQ). Below this level I presume all requests are treated equally and are issued in-order to L3 and to the bus. Given a shared bus topology, as soon as the request is issued on the bus it can be considered to have been observed by other agents (assuming each agent then then maintains order while processing the requests). I think the response phase (whether it is deferred or not) is not relevant.
Quoted 2 lines
If there is a more appropriatte news group please let me know.
This is the sort of question that would be on-topic for ia64-technical, the new mailing list I set up recently [1].
Matt
[1] https://gelato.unsw.edu.au/mailman/listinfo/ia64-technical