- Spell fixes - adress to address
Subsystems (10)
PATCH 1/1 - Spell fixes - adress to address
Fixed some typos. From adress to address. Only touched comments in English.
Daniel Andersen
--
arch/mips/mm/pg-r4k.c +1 -1
@@ -59,7 +59,7 @@/* * An address fits into a single register so it's safe to use 64-bit registers -* if we have 64-bit adresses. +* if we have 64-bit addresses. */ #define cpu_has_64bit_registers cpu_has_64bit_addresses
arch/x86_64/kernel/head.S +1 -1
@@ -18,7 +18,7 @@ #include <asm/msr.h> #include <asm/cache.h> -/* we are not able to switch in one step to the final KERNEL ADRESS SPACE +/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE * because we need identity-mapped pages on setup so define __START_KERNEL to * 0x100000 for this stage *
Documentation/networking/bonding.txt +1 -1
@@ -216,7 +216,7 @@ Specifies the ip addresses to use when arp_interval is > 0. These are the targets of the ARP request sent to determine the health of the link to the targets. Specify these values in ddd.ddd.ddd.ddd - format. Multiple ip adresses must be seperated by a comma. At least + format. Multiple ip addresses must be seperated by a comma. At least one ip address needs to be given for ARP monitoring to work. The maximum number of targets that can be specified is set at 16.
drivers/media/common/saa7146_core.c +1 -1
@@ -359,7 +359,7 @@ } dev->revision &=0xf ; -/* remap the memory from virtual to physical adress */ +/* remap the memory from virtual to physical address */ adr =pci_resource_start (pci,0 ); len =pci_resource_len (pci,0 );
drivers/media/video/tea6420.c +1 -1
@@ -5,7 +5,7 @@ The tea6420 is a bus controlled audio-matrix with 5 stereo inputs, 4 stereo outputs and gain control for each output. - It is cascadable, i.e. it can be found at the adresses 0x98 + It is cascadable, i.e. it can be found at the addresses 0x98 and 0x9a on the i2c-bus. For detailed informations download the specifications directly
drivers/mtd/nand/autcpu12.c +3 -3
@@ -20,7 +20,7 @@* * 02-12-2002 TG Cleanup of module params * -* 02-20-2002 TG adjusted for different rd/wr adress support +* 02-20-2002 TG adjusted for different rd/wr address support * added support for read device ready/busy line * added page_cache *
@@ -149,7 +149,7 @@ goto out; } -/* map physical adress */ +/* map physical address */ autcpu12_fio_base=(unsigned long )ioremap (autcpu12_fio_pbase,SZ_1K );if (!autcpu12_fio_base){printk ("Ioremap autcpu12 SmartMedia Card failed\n" );
@@ -221,7 +221,7 @@/* Release resources, unregister device */ nand_release (autcpu12_mtd); -/* unmap physical adress */ +/* unmap physical address */ iounmap ((void *)autcpu12_fio_base);/* Free the MTD device structure */
drivers/mtd/nand/edb7312.c +1 -1
@@ -142,7 +142,7 @@return -ENOMEM ; } -/* map physical adress */ +/* map physical address */ ep7312_fio_base = (unsigned long )ioremap (ep7312_fio_pbase,SZ_1K );if (!ep7312_fio_base) {printk ("ioremap EDB7312 NAND flash failed\n" );
drivers/net/bonding/bond_main.c +1 -1
@@ -4105,7 +4105,7 @@/* * in XOR mode, we determine the output device by performing xor on -* the source and destination hw adresses. If this device is not +* the source and destination hw addresses. If this device is not * enabled, find the next slave following this xor slave. */ static int bond_xmit_xor (struct sk_buff *skb,struct net_device *bond_dev)
fs/freevxfs/vxfs_immed.c +1 -1
@@ -54,7 +54,7 @@ };/* -* Adress space operations for immed files and directories. +* Address space operations for immed files and directories. */ struct address_space_operations vxfs_immed_aops = { .readpage = vxfs_immed_readpage,
include/asm-arm/arch-pxa/pxa-regs.h +1 -1
@@ -953,7 +953,7 @@#define ICSR0 __REG(0x40800014)/* ICP Status Register 0 */ #define ICSR1 __REG(0x40800018)/* ICP Status Register 1 */ -#define ICCR0_AME (1 << 7)/* Adress match enable */ +#define ICCR0_AME (1 << 7)/* Address match enable */ #define ICCR0_TIE (1 << 6)/* Transmit FIFO interrupt enable */ #define ICCR0_RIE (1 << 5)/* Recieve FIFO interrupt enable */ #define ICCR0_RXE (1 << 4)/* Receive enable */
include/asm-m68knommu/m5249sim.h +2 -2
@@ -43,10 +43,10 @@#define MCFSIM_CSAR1 0x8c/* CS 1 Address reg (r/w) */ #define MCFSIM_CSMR1 0x90/* CS 1 Mask reg (r/w) */ #define MCFSIM_CSCR1 0x96/* CS 1 Control reg (r/w) */ -#define MCFSIM_CSAR2 0x98/* CS 2 Adress reg (r/w) */ +#define MCFSIM_CSAR2 0x98/* CS 2 Address reg (r/w) */ #define MCFSIM_CSMR2 0x9c/* CS 2 Mask reg (r/w) */ #define MCFSIM_CSCR2 0xa2/* CS 2 Control reg (r/w) */ -#define MCFSIM_CSAR3 0xa4/* CS 3 Adress reg (r/w) */ +#define MCFSIM_CSAR3 0xa4/* CS 3 Address reg (r/w) */ #define MCFSIM_CSMR3 0xa8/* CS 3 Mask reg (r/w) */ #define MCFSIM_CSCR3 0xae/* CS 3 Control reg (r/w) */
include/asm-m68knommu/m5307sim.h +6 -6
@@ -64,22 +64,22 @@#define MCFSIM_CSMR7 0xda/* CS 7 Mask reg (r/w) */ #define MCFSIM_CSCR7 0xde/* CS 7 Control reg (r/w) */ #else -#define MCFSIM_CSAR2 0x98/* CS 2 Adress reg (r/w) */ +#define MCFSIM_CSAR2 0x98/* CS 2 Address reg (r/w) */ #define MCFSIM_CSMR2 0x9c/* CS 2 Mask reg (r/w) */ #define MCFSIM_CSCR2 0xa2/* CS 2 Control reg (r/w) */ -#define MCFSIM_CSAR3 0xa4/* CS 3 Adress reg (r/w) */ +#define MCFSIM_CSAR3 0xa4/* CS 3 Address reg (r/w) */ #define MCFSIM_CSMR3 0xa8/* CS 3 Mask reg (r/w) */ #define MCFSIM_CSCR3 0xae/* CS 3 Control reg (r/w) */ -#define MCFSIM_CSAR4 0xb0/* CS 4 Adress reg (r/w) */ +#define MCFSIM_CSAR4 0xb0/* CS 4 Address reg (r/w) */ #define MCFSIM_CSMR4 0xb4/* CS 4 Mask reg (r/w) */ #define MCFSIM_CSCR4 0xba/* CS 4 Control reg (r/w) */ -#define MCFSIM_CSAR5 0xbc/* CS 5 Adress reg (r/w) */ +#define MCFSIM_CSAR5 0xbc/* CS 5 Address reg (r/w) */ #define MCFSIM_CSMR5 0xc0/* CS 5 Mask reg (r/w) */ #define MCFSIM_CSCR5 0xc6/* CS 5 Control reg (r/w) */ -#define MCFSIM_CSAR6 0xc8/* CS 6 Adress reg (r/w) */ +#define MCFSIM_CSAR6 0xc8/* CS 6 Address reg (r/w) */ #define MCFSIM_CSMR6 0xcc/* CS 6 Mask reg (r/w) */ #define MCFSIM_CSCR6 0xd2/* CS 6 Control reg (r/w) */ -#define MCFSIM_CSAR7 0xd4/* CS 7 Adress reg (r/w) */ +#define MCFSIM_CSAR7 0xd4/* CS 7 Address reg (r/w) */ #define MCFSIM_CSMR7 0xd8/* CS 7 Mask reg (r/w) */ #define MCFSIM_CSCR7 0xde/* CS 7 Control reg (r/w) */ #endif /* CONFIG_OLDMASK */
include/asm-m68knommu/m5407sim.h +6 -6
@@ -48,22 +48,22 @@#define MCFSIM_CSMR1 0x90/* CS 1 Mask reg (r/w) */ #define MCFSIM_CSCR1 0x96/* CS 1 Control reg (r/w) */ -#define MCFSIM_CSAR2 0x98/* CS 2 Adress reg (r/w) */ +#define MCFSIM_CSAR2 0x98/* CS 2 Address reg (r/w) */ #define MCFSIM_CSMR2 0x9c/* CS 2 Mask reg (r/w) */ #define MCFSIM_CSCR2 0xa2/* CS 2 Control reg (r/w) */ -#define MCFSIM_CSAR3 0xa4/* CS 3 Adress reg (r/w) */ +#define MCFSIM_CSAR3 0xa4/* CS 3 Address reg (r/w) */ #define MCFSIM_CSMR3 0xa8/* CS 3 Mask reg (r/w) */ #define MCFSIM_CSCR3 0xae/* CS 3 Control reg (r/w) */ -#define MCFSIM_CSAR4 0xb0/* CS 4 Adress reg (r/w) */ +#define MCFSIM_CSAR4 0xb0/* CS 4 Address reg (r/w) */ #define MCFSIM_CSMR4 0xb4/* CS 4 Mask reg (r/w) */ #define MCFSIM_CSCR4 0xba/* CS 4 Control reg (r/w) */ -#define MCFSIM_CSAR5 0xbc/* CS 5 Adress reg (r/w) */ +#define MCFSIM_CSAR5 0xbc/* CS 5 Address reg (r/w) */ #define MCFSIM_CSMR5 0xc0/* CS 5 Mask reg (r/w) */ #define MCFSIM_CSCR5 0xc6/* CS 5 Control reg (r/w) */ -#define MCFSIM_CSAR6 0xc8/* CS 6 Adress reg (r/w) */ +#define MCFSIM_CSAR6 0xc8/* CS 6 Address reg (r/w) */ #define MCFSIM_CSMR6 0xcc/* CS 6 Mask reg (r/w) */ #define MCFSIM_CSCR6 0xd2/* CS 6 Control reg (r/w) */ -#define MCFSIM_CSAR7 0xd4/* CS 7 Adress reg (r/w) */ +#define MCFSIM_CSAR7 0xd4/* CS 7 Address reg (r/w) */ #define MCFSIM_CSMR7 0xd8/* CS 7 Mask reg (r/w) */ #define MCFSIM_CSCR7 0xde/* CS 7 Control reg (r/w) */
include/linux/mtd/nand.h +1 -1
@@ -26,7 +26,7 @@* 10-24-2000 SJH Added prototype for 'nand_scan' function * 10-29-2001 TG changed nand_chip structure to support * hardwarespecific function for accessing control lines -* 02-21-2002 TG added support for different read/write adress and +* 02-21-2002 TG added support for different read/write address and * ready/busy line access function * 02-26-2002 TG added chip_delay to nand_chip structure to optimize * command delay times for different chips
sound/parisc/harmony.c +5 -5
@@ -30,7 +30,7 @@* Harmony chipset 'modus operandi'. * - This chipset is found in some HP 32bit workstations, like 712, or B132 class. * most of controls are done through registers. Register are found at a fixed offset -* from the hard physical adress, given in struct dev by register_parisc_driver. +* from the hard physical address, given in struct dev by register_parisc_driver. * * Playback and recording use 4kb pages (dma or not, depending on the machine). *
@@ -39,12 +39,12 @@* Bits 2 and 10 of DSTATUS register are '1' when harmony needs respectively * a new page for recording and playing. * Interrupt are disabled/enabled by writing to bit 32 of DSTATUS. -* Adresses of next page to be played is put in PNXTADD register, next page +* Addresses of next page to be played is put in PNXTADD register, next page * to be recorded is put in RNXTADD. There is 2 read-only registers, PCURADD and -* RCURADD that provides adress of current page. +* RCURADD that provides address of current page. * * Harmony has no way to controll full duplex or half duplex mode. It means -* that we always need to provide adresses of playback and capture data, even +* that we always need to provide addresses of playback and capture data, even * when this is not needed. That's why we statically alloc one graveyard * buffer (to put recorded data in play-only mode) and a silence buffer. *
@@ -328,7 +328,7 @@/* * interruption routine: -* The interrupt routine must provide adresse of next physical pages +* The interrupt routine must provide addresse of next physical pages * used by harmony */ static int snd_card_harmony_interrupt (int irq,void *dev,struct pt_regs *regs)