clocksource: sh_cmt: Add R-car Gen3 CMT0/1 support
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cover clocksource: sh_cmt: Add R-car Gen3 CMT0/1 support
From: Bui Duc Phuc <[email protected]>
Hi,
These are my first patches which will be added CMT driver for support R-car Gen3 series (r8a7795 and r8a7796).
Please consider these patches.
Best regards.
Bui Duc Phuc (8):
devicetree: binding: R-car Gen3 CMT0 and CMT1 bindings
ARM64: dts: r8a7795: Add CMT device to DT
ARM64: dts: r8a7796: Add CMT device to DT
clk: renesas: r8a7795: Add CMT clocks
clk: renesas: r8a7796: Add CMT clocks
clocksource: sh_cmt: Support separate R-car Gen3 CMT0/1
clocksource: Kconfig: Modify CMT config support 64bit
ARM64: defconfig: Enable SH_TIMER_CMT config option
.../devicetree/bindings/timer/renesas,cmt.txt | 2 ++ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 30 ++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 30 ++++++++++++++++++++++ arch/arm64/configs/defconfig | 1 + drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 +++ drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 +++ drivers/clocksource/Kconfig | 2 +- drivers/clocksource/sh_cmt.c | 21 +++++++++++++-- 8 files changed, 91 insertions(+), 3 deletions(-)
Signature · 1 line
2.7.4
PATCH 1/8 devicetree: binding: R-car Gen3 CMT0 and CMT1 bindings
From: Bui Duc Phuc <[email protected]>
Add documentation for new separate CMT0 and CMT1 DT compatible strings for R-Car Gen3.
--- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/timer/renesas,cmt.txt +2 -0
@@ -52,6 +52,8 @@ Required Properties: (CMT[01] on r8a73a4, r8a7790 and r8a7791) This is a fallback for the renesas,cmt-48-r8a73a4, renesas,cmt-48-r8a7790 and renesas,cmt-48-r8a7791 entries. + - "renesas,cmt-48-gen3" for third generation 48-bit CMT + (CMT[01] on r8a7795 and r8a7796) - reg: base address and length of the registers block for the timer module. - interrupts: interrupt-specifier for the timer, one per channel.
Signature · 1 line
2.7.4
PATCH 1/8 devicetree: binding: R-car Gen3 CMT0 and CMT1 bindings
Hi Phuc-san,
Quoted 13 lines · On Fri, Sep 9, 2016 at 1:43 PM, <[email protected]> wrote:
Add documentation for new separate CMT0 and CMT1 DT compatible strings for R-Car Gen3.
Signed-off-by Bui Duc Phuc <[email protected]>--- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 2 ++ 1 file changed, 2 insertions(+)Documentation/devicetree/bindings/timer/renesas,cmt.txt +0
-0
Documentation/devicetree/bindings/timer/renesas,cmt.txt Required Properties: · line 56
Quoted 5 lines
Documentation/devicetree/bindings/timer/renesas,cmt.txt +2
-0@@ -52,6 +52,8 @@ Required Properties: (CMT[01] on r8a73a4, r8a7790 and r8a7791) This is a fallback for the renesas,cmt-48-r8a73a4, renesas,cmt-48-r8a7790 and renesas,cmt-48-r8a7791 entries. + - "renesas,cmt-48-gen3" for third generation 48-bit CMT + (CMT[01] on r8a7795 and r8a7796)
I think the plan was to get rid of the renesas,cmt-48-* bindings, as they do not allow to differentiate between CMT0 and CMT1, which have different feature sets.
Cfr. Magnus' series "clocksource: sh_cmt: DT binding rework V4"
(https://lkml.org/lkml/2016/3/14/433).
Magnus: What's the status of your series?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH 1/8 devicetree: binding: R-car Gen3 CMT0 and CMT1 bindings
Dear Geert,
Quoted 8 lines
I think the plan was to get rid of the renesas,cmt-48-* bindings, as they do not allow to differentiate between CMT0 and CMT1, which have different feature sets.
Cfr. Magnus' series "clocksource:
sh_cmt: DT binding rework V4"
(https://lkml.org/lkml/2016/3/14/433).Magnus: What's the status of your series?
Thank for your comments. I will update in V2.
I am still waiting for Magnus's comments, but from my point of view,Magnus's patches seem
support 32 bit counter only, they are not suitable for 48bit counter. According to hardware manual, there has to be registers ( CMCSRH, CMCNTH,CMCORH) set for 48 bit counter,
but I do not see the registers ( CMCSRH, CMCNTH,CMCORH) in Magnus's patches.
Signature · 3 lines
Regards, Bui Duc Phuc
PATCH 2/8 ARM64: dts: r8a7795: Add CMT device to DT
In reply to bd-phuc at jinso.co.jpFrom: Bui Duc Phuc <[email protected]>
Add the CMT0 and CMT1 counters to the r8a7795 device tree
--- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
arch/arm64/boot/dts/renesas/r8a7795.dtsi +30 -0
@@ -312,6 +312,36 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; + cmt0: timer at e60f0000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + renesas,channels-mask = <0x60>; + }; + + cmt1: timer at e6130000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + renesas,channels-mask = <0xff>; + }; + cpg: clock-controller at e6150000 { compatible = "renesas,r8a7795-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>;
Signature · 1 line
2.7.4
PATCH 3/8 ARM64: dts: r8a7796: Add CMT device to DT
In reply to bd-phuc at jinso.co.jpFrom: Bui Duc Phuc <[email protected]>
Add the CMT0 and CMT1 counters to the r8a7796 device tree
--- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
arch/arm64/boot/dts/renesas/r8a7796.dtsi +30 -0
@@ -98,6 +98,36 @@ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; + cmt0: timer at e60f0000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + + renesas,channels-mask = <0x60>; + }; + + cmt1: timer at e6130000 { + compatible = "renesas,cmt-48-gen3"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + + renesas,channels-mask = <0xff>; + }; + wdt0: watchdog at e6020000 { compatible = "renesas,r8a7796-wdt", "renesas,rcar-gen3-wdt";
Signature · 1 line
2.7.4
PATCH 4/8 clk: renesas: r8a7795: Add CMT clocks
In reply to bd-phuc at jinso.co.jpFrom: Bui Duc Phuc <[email protected]>
This patch adds CMT module clocks for r8a7795 SoC.
--- drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++++ 1 file changed, 4 insertions(+)
drivers/clk/renesas/r8a7795-cpg-mssr.c +4 -0
@@ -123,6 +123,10 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {DEF_MOD ("sys-dmac2" ,217 ,R8A7795_CLK_S3D1 ),DEF_MOD ("sys-dmac1" ,218 ,R8A7795_CLK_S3D1 ),DEF_MOD ("sys-dmac0" ,219 ,R8A7795_CLK_S3D1 ), +DEF_MOD ("cmt3" ,300 ,R8A7795_CLK_R ), +DEF_MOD ("cmt2" ,301 ,R8A7795_CLK_R ), +DEF_MOD ("cmt1" ,302 ,R8A7795_CLK_R ), +DEF_MOD ("cmt0" ,303 ,R8A7795_CLK_R ),DEF_MOD ("scif2" ,310 ,R8A7795_CLK_S3D4 ),DEF_MOD ("sdif3" ,311 ,R8A7795_CLK_SD3 ), DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
Signature · 1 line
2.7.4
PATCH 4/8 clk: renesas: r8a7795: Add CMT clocks
Quoted 5 lines · On Fri, Sep 9, 2016 at 1:43 PM, <[email protected]> wrote:
From: Bui Duc Phuc <[email protected]>
This patch adds CMT module clocks for r8a7795 SoC.
Signed-off-by Bui Duc Phuc <[email protected]>
(will queue in clk-renesas-for-v4.9)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH 4/8 clk: renesas: r8a7795: Add CMT clocks
Dear Geert
Thank you for your review.
Quoted 4 lines
Reviewed-by Geert Uytterhoeven <[email protected]>(will queue in clk-renesas-for-v4.9)
Signature · 3 lines
Regards, Bui Duc Phuc
PATCH 5/8 clk: renesas: r8a7796: Add CMT clocks
In reply to bd-phuc at jinso.co.jpFrom: Bui Duc Phuc <[email protected]>
This patch adds CMT module clocks for r8a7796 SoC.
--- drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 ++++ 1 file changed, 4 insertions(+)
drivers/clk/renesas/r8a7796-cpg-mssr.c +4 -0
@@ -97,6 +97,10 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { };static const struct mssr_mod_clk r8a7796_mod_clks[]__initconst = { +DEF_MOD ("cmt3" ,300 ,R8A7796_CLK_R ), +DEF_MOD ("cmt2" ,301 ,R8A7796_CLK_R ), +DEF_MOD ("cmt1" ,302 ,R8A7796_CLK_R ), +DEF_MOD ("cmt0" ,303 ,R8A7796_CLK_R ),DEF_MOD ("scif2" ,310 ,R8A7796_CLK_S3D4 ),DEF_MOD ("intc-ap" ,408 ,R8A7796_CLK_S3D1 ), };
Signature · 1 line
2.7.4
PATCH 5/8 clk: renesas: r8a7796: Add CMT clocks
Quoted 5 lines · On Fri, Sep 9, 2016 at 1:43 PM, <[email protected]> wrote:
From: Bui Duc Phuc <[email protected]>
This patch adds CMT module clocks for r8a7796 SoC.
Signed-off-by Bui Duc Phuc <[email protected]>
(will queue in clk-renesas-for-v4.9)
drivers/clk/renesas/r8a7796-cpg-mssr.c static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { · line 103
Quoted 10 lines
drivers/clk/renesas/r8a7796-cpg-mssr.c +4
-0@@ -97,6 +97,10 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { };static const struct mssr_mod_clk r8a7796_mod_clks[]__initconst = { +DEF_MOD ("cmt3" ,300 ,R8A7796_CLK_R ), +DEF_MOD ("cmt2" ,301 ,R8A7796_CLK_R ), +DEF_MOD ("cmt1" ,302 ,R8A7796_CLK_R ), +DEF_MOD ("cmt0" ,303 ,R8A7796_CLK_R ),
BTW, I've dropped the spaces before the TABs (also in the r8a7795 patch).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH 5/8 clk: renesas: r8a7796: Add CMT clocks
Dear Geert
Thank you for your review.
Quoted 3 lines
Reviewed-by Geert Uytterhoeven <[email protected]>(will queue in clk-renesas-for-v4.9)
Thank you for helping me.
Quoted 3 lines
BTW, I've dropped the spaces before the TABs (also in the r8a7795 patch).
Signature · 3 lines
Regards, Bui Duc Phuc
PATCH 6/8 clocksource: sh_cmt: Support separate R-car Gen3 CMT0/1
In reply to bd-phuc at jinso.co.jpFrom: Bui Duc Phuc <[email protected]>
Add support for the new R-Car Gen3 CMT0 and CMT1 bindings.
--- drivers/clocksource/sh_cmt.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-)
drivers/clocksource/sh_cmt.c +19 -2
@@ -69,6 +69,7 @@ enum sh_cmt_model {SH_CMT_32BIT_FAST ,SH_CMT_48BIT ,SH_CMT_48BIT_GEN2 , + SH_CMT_48BIT_GEN3, }; struct sh_cmt_info {
@@ -230,6 +231,16 @@ static const struct sh_cmt_info sh_cmt_info[] = { .read_count = sh_cmt_read32, .write_count = sh_cmt_write32, }, + [SH_CMT_48BIT_GEN3] = { + .model = SH_CMT_48BIT_GEN3, + .width = 32, + .overflow_bit = SH_CMT32_CMCSR_CMF, + .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), + .read_control = sh_cmt_read32, + .write_control = sh_cmt_write32, + .read_count = sh_cmt_read32, + .write_count = sh_cmt_write32, + }, };#define CMCSR 0/* channel register */
@@ -864,6 +875,7 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, ch->cmt = cmt; ch->index = index; ch->hwidx = hwidx; + ch->timer_bit = hwidx;/* * Compute the address of the channel control register block. For the
@@ -888,6 +900,12 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,case SH_CMT_48BIT_GEN2 : ch->iostart = cmt->mapbase + ch->hwidx *0x100 ; ch->ioctrl = ch->iostart +0x10 ; + ch->timer_bit =0 ; +break ; +case SH_CMT_48BIT_GEN3 : + ch->iostart = cmt->mapbase + ch->hwidx *0x100 ; + ch->ioctrl = ch->iostart +0x10 ; + ch->timer_bit =0 ;break ; }
@@ -899,8 +917,6 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, ch->match_value = ch->max_match_value;raw_spin_lock_init (&ch->lock); - ch->timer_bit = cmt->info->model ==SH_CMT_48BIT_GEN2 ?0 : ch->hwidx; - ret =sh_cmt_register (ch,dev_name (&cmt->pdev->dev), clockevent, clocksource);if (ret) {
@@ -944,6 +960,7 @@ static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { { .compatible = "renesas,cmt-32-fast", .data = &sh_cmt_info[SH_CMT_32BIT_FAST] }, { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] }, { .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT_48BIT_GEN2] }, + { .compatible = "renesas,cmt-48-gen3", .data = &sh_cmt_info[SH_CMT_48BIT_GEN3] }, { } };MODULE_DEVICE_TABLE (of, sh_cmt_of_table);
Signature · 1 line
2.7.4
PATCH 6/8 clocksource: sh_cmt: Support separate R-car Gen3 CMT0/1
Hi Bui Duc,
Thank you for the patch.
Quoted 77 lines · On Friday 09 Sep 2016 20:43:12 [email protected] wrote:
From: Bui Duc Phuc <[email protected]>
Add support for the new R-Car Gen3 CMT0 and CMT1 bindings.
Signed-off-by Bui Duc Phuc <[email protected]>--- drivers/clocksource/sh_cmt.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-)drivers/clocksource/sh_cmt.c +18
-2@@ -69,6 +69,7 @@ enum sh_cmt_model {SH_CMT_32BIT_FAST ,SH_CMT_48BIT ,SH_CMT_48BIT_GEN2 , + SH_CMT_48BIT_GEN3, }; struct sh_cmt_info {@@ -230,6 +231,16 @@ static const struct sh_cmt_info sh_cmt_info[] = { .read_count = sh_cmt_read32, .write_count = sh_cmt_write32, }, + [SH_CMT_48BIT_GEN3] = { + .model = SH_CMT_48BIT_GEN3, + .width = 32, + .overflow_bit = SH_CMT32_CMCSR_CMF, + .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), + .read_control = sh_cmt_read32, + .write_control = sh_cmt_write32, + .read_count = sh_cmt_read32, + .write_count = sh_cmt_write32, + }, };#define CMCSR 0/* channel register */ @@ -864,6 +875,7 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, ch->cmt = cmt; ch->index = index; ch->hwidx = hwidx; + ch->timer_bit = hwidx;/* * Compute the address of the channel control register block. For the @@ -888,6 +900,12 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, case SH_CMT_48BIT_GEN2: ch->iostart = cmt->mapbase + ch->hwidx * 0x100; ch->ioctrl = ch->iostart +0x10 ; + ch->timer_bit =0 ; +break ; +case SH_CMT_48BIT_GEN3 : + ch->iostart = cmt->mapbase + ch->hwidx *0x100 ; + ch->ioctrl = ch->iostart +0x10 ; + ch->timer_bit =0 ;break ; }@@ -899,8 +917,6 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, ch->match_value = ch->max_match_value;raw_spin_lock_init (&ch->lock); - ch->timer_bit = cmt->info->model ==SH_CMT_48BIT_GEN2 ?0 : ch->hwidx; - ret =sh_cmt_register (ch,dev_name (&cmt->pdev->dev), clockevent, clocksource);if (ret) {@@ -944,6 +960,7 @@ static const struct of_device_id sh_cmt_of_table[]__maybe_unused = { { .compatible ="renesas,cmt-32-fast" , .data = &sh_cmt_info[SH_CMT_32BIT_FAST ] }, { .compatible ="renesas,cmt-48" , .data = &sh_cmt_info[SH_CMT_48BIT ] }, { .compatible = "renesas,cmt-48-gen2", .data =&sh_cmt_info[SH_CMT_48BIT_GEN2] },
drivers/clocksource/sh_cmt.c +1
-0+ { .compatible = "renesas,cmt-48-gen3", .data =
Quoted 1 line
&sh_cmt_info[SH_CMT_48BIT_GEN3] },
Given that the Gen2 and Gen3 CMT seem identical based on the above code, how about just using SH_CMT_48BIT_GEN2 here ? You wouldn't need any of the above changes.
Quoted 3 lines
{ }
};
MODULE_DEVICE_TABLE(of, sh_cmt_of_table);
Signature · 3 lines
Regards, Laurent Pinchart
PATCH 7/8 clocksource: Kconfig: Modify CMT config support 64bit
In reply to bd-phuc at jinso.co.jpFrom: Bui Duc Phuc <[email protected]>
Modify CMT config to support 64bit
--- drivers/clocksource/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clocksource/Kconfig +1 -1
@@ -408,7 +408,7 @@ config SYS_SUPPORTS_EM_STI bool config SH_TIMER_CMT - bool "Renesas CMT timer driver" if COMPILE_TEST + bool "Renesas CMT timer driver" if ( ARM64 || COMPILE_TEST ) depends on GENERIC_CLOCKEVENTS depends on HAS_IOMEM default SYS_SUPPORTS_SH_CMT
Signature · 1 line
2.7.4
PATCH 7/8 clocksource: Kconfig: Modify CMT config support 64bit
Quoted 14 lines · bd-phuc at jinso.co.jp
From: Bui Duc Phuc <[email protected]>
Modify CMT config to support 64bit
Signed-off-by Bui Duc Phuc <[email protected]>--- drivers/clocksource/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/clocksource/Kconfig +0
-0
drivers/clocksource/Kconfig config SYS_SUPPORTS_EM_STI · line 411
Quoted 5 lines
drivers/clocksource/Kconfig +1
-1@@ -408,7 +408,7 @@ config SYS_SUPPORTS_EM_STI bool config SH_TIMER_CMT - bool "Renesas CMT timer driver" if COMPILE_TEST + bool "Renesas CMT timer driver" if ( ARM64 || COMPILE_TEST )
Parens not needed and the spaces after/before them even less so.
[...]
MBR, Sergei
PATCH 7/8 clocksource: Kconfig: Modify CMT config support 64bit
Hi Sergei
Thanks for your comment.
Quoted 4 lines
Quoted 1 line
+ bool "Renesas CMT timer driver" if ( ARM64 ||
COMPILE_TEST)Parens not needed and the spaces after/before them even less so.
OK
I will update in V2
Thanks & best regards.
Bui Duc Phuc
PATCH 7/8 clocksource: Kconfig: Modify CMT config support 64bit
In reply to bd-phuc at jinso.co.jpHi Bui Duc,
Thank you for the patch.
Quoted 14 lines · On Friday 09 Sep 2016 20:43:13 [email protected] wrote:
From: Bui Duc Phuc <[email protected]>
Modify CMT config to support 64bit
Signed-off-by Bui Duc Phuc <[email protected]>--- drivers/clocksource/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/clocksource/Kconfig +0
-0
drivers/clocksource/Kconfig config SYS_SUPPORTS_EM_STI · line 411
Quoted 5 lines
drivers/clocksource/Kconfig +1
-1@@ -408,7 +408,7 @@ config SYS_SUPPORTS_EM_STI bool config SH_TIMER_CMT - bool "Renesas CMT timer driver" if COMPILE_TEST + bool "Renesas CMT timer driver" if ( ARM64 || COMPILE_TEST )
I think you should instead add
select SH_TIMER_CMT
to the config ARCH_RENESAS section in arch/arm64/Kconfig.platforms
Quoted 3 lines
drivers/clocksource/Kconfig +0
-0depends on GENERIC_CLOCKEVENTS depends on HAS_IOMEM default SYS_SUPPORTS_SH_CMT
Signature · 3 lines
Regards, Laurent Pinchart
PATCH 7/8 clocksource: Kconfig: Modify CMT config support 64bit
Hi Laurent
Thank you for your comments.
Quoted 5 lines
I think you should instead add
select
SH_TIMER_CMTto the config
ARCH_RENESASsection inarch/arm64/Kconfig.platforms
I will update in V2.
Signature · 3 lines
Regards, Bui Duc Phuc
PATCH 8/8 ARM64: defconfig: Enable SH_TIMER_CMT config option
In reply to bd-phuc at jinso.co.jpFrom: Bui Duc Phuc <[email protected]>
Enable SH CMT driver for R-car Gen3 : SH_TIMER_CMT
--- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+)
arch/arm64/configs/defconfig +1 -0
@@ -3,6 +3,7 @@ CONFIG_POSIX_MQUEUE=y CONFIG_AUDIT=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_SH_TIMER_CMT=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_TASKSTATS=y
Signature · 1 line
2.7.4