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Support for NEC VR4133 in 2.6

PATCH In review Manish Lachwani 3 participants 3 messages Nov 18, 2004 – Nov 19, 2004 MIPS

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Manish Lachwani

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PATCH 1/1 Support for NEC VR4133 in 2.6

Hi Ralf

Attached patch implements support for NEC VR4133 and NEC Rockhopper in 2.6. Currently there is no ethernet driver for the ports on the CMB-VR4133.

The board has been booted with the Onboard PcNet32 network interface and with an Intel EEPRO100 PCI NIC card.

Please review ...

Thanks
Manish Lachwani

Source: MontaVista Software, Inc. | http://www.mvista.com | Manish Lachwani <[email protected]>
Type: Enhancement
Disposition: Submitted to Linux-MIPS
Description:

	Support for NEC VR4133 and NEC CMB-VR4133 in 2.6.10 kernel
arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c new file +256 -0
Index: linux/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
===================================================================
@@ -0,0 +1,256 @@
+/*
+ * arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
+ *
+ * Initialize for ALi M1535+(included M5229 and M5237).
+ *
+ * Author: Yoichi Yuasa <[email protected], or [email protected]> and
+ *         Alex Sapkov <[email protected]>
+ *
+ * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for NEC-CMBVR4133 in 2.6
+ * Author: Manish Lachwani ([email protected])
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/serial.h>
+
+#include <asm/vr41xx/cmbvr4133.h>
+#include <linux/pci.h>
+#include <asm/io.h>
+
+#define CONFIG_PORT(port)	((port) ? 0x3f0 : 0x370)
+#define DATA_PORT(port)		((port) ? 0x3f1 : 0x371)
+#define INDEX_PORT(port)	CONFIG_PORT(port)
+
+#define ENTER_CONFIG_MODE(port)				\
+	do {						\
+		outb_p(0x51, CONFIG_PORT(port));	\
+		outb_p(0x23, CONFIG_PORT(port));	\
+	} while(0)
+
+#define SELECT_LOGICAL_DEVICE(port, dev_no)		\
+	do {						\
+		outb_p(0x07, INDEX_PORT(port));		\
+		outb_p((dev_no), DATA_PORT(port));	\
+	} while(0)
+
+#define WRITE_CONFIG_DATA(port,index,data)		\
+	do {						\
+		outb_p((index), INDEX_PORT(port));	\
+		outb_p((data), DATA_PORT(port));	\
+	} while(0)
+
+#define EXIT_CONFIG_MODE(port)	outb(0xbb, CONFIG_PORT(port))
+
+#define PCI_CONFIG_ADDR	KSEG1ADDR(0x0f000c18)
+#define PCI_CONFIG_DATA	KSEG1ADDR(0x0f000c14)
+
+#ifdef CONFIG_BLK_DEV_FD
+
+void __devinit ali_m1535plus_fdc_init(int port)
+{
+	ENTER_CONFIG_MODE(port);
+	SELECT_LOGICAL_DEVICE(port, 0);		/* FDC */
+	WRITE_CONFIG_DATA(port, 0x30, 0x01);	/* FDC: enable */
+	WRITE_CONFIG_DATA(port, 0x60, 0x03);	/* I/O port base: 0x3f0 */
+	WRITE_CONFIG_DATA(port, 0x61, 0xf0);
+	WRITE_CONFIG_DATA(port, 0x70, 0x06);	/* IRQ: 6 */
+	WRITE_CONFIG_DATA(port, 0x74, 0x02);	/* DMA: channel 2 */
+	WRITE_CONFIG_DATA(port, 0xf0, 0x08);
+	WRITE_CONFIG_DATA(port, 0xf1, 0x00);
+	WRITE_CONFIG_DATA(port, 0xf2, 0xff);
+	WRITE_CONFIG_DATA(port, 0xf4, 0x00);
+	EXIT_CONFIG_MODE(port);
+}
+
+#endif
+
+void __devinit ali_m1535plus_parport_init(int port)
+{
+	ENTER_CONFIG_MODE(port);
+	SELECT_LOGICAL_DEVICE(port, 3);		/* Parallel Port */
+	WRITE_CONFIG_DATA(port, 0x30, 0x01);
+	WRITE_CONFIG_DATA(port, 0x60, 0x03);	/* I/O port base: 0x378 */
+	WRITE_CONFIG_DATA(port, 0x61, 0x78);
+	WRITE_CONFIG_DATA(port, 0x70, 0x07);	/* IRQ: 7 */
+	WRITE_CONFIG_DATA(port, 0x74, 0x04);	/* DMA: None */
+	WRITE_CONFIG_DATA(port, 0xf0, 0x8c);	/* IRQ polarity: Active Low */
+	WRITE_CONFIG_DATA(port, 0xf1, 0xc5);
+	EXIT_CONFIG_MODE(port);
+}
+
+#ifdef CONFIG_PC_KEYB
+
+void __devinit ali_m1535plus_keyboard_init(int port)
+{
+	ENTER_CONFIG_MODE(port);
+	SELECT_LOGICAL_DEVICE(port, 7);		/* KEYBOARD */
+	WRITE_CONFIG_DATA(port, 0x30, 0x01);	/* KEYBOARD: eable */
+	WRITE_CONFIG_DATA(port, 0x70, 0x01);	/* IRQ: 1 */
+	WRITE_CONFIG_DATA(port, 0x72, 0x0c);	/* PS/2 Mouse IRQ: 12 */
+	WRITE_CONFIG_DATA(port, 0xf0, 0x00);
+	EXIT_CONFIG_MODE(port);
+}
+
+#endif
+
+void __devinit ali_m1535plus_hotkey_init(int port)
+{
+	ENTER_CONFIG_MODE(port);
+	SELECT_LOGICAL_DEVICE(port, 0xc);	/* HOTKEY */
+	WRITE_CONFIG_DATA(port, 0x30, 0x00);
+	WRITE_CONFIG_DATA(port, 0xf0, 0x35);
+	WRITE_CONFIG_DATA(port, 0xf1, 0x14);
+	WRITE_CONFIG_DATA(port, 0xf2, 0x11);
+	WRITE_CONFIG_DATA(port, 0xf3, 0x71);
+	WRITE_CONFIG_DATA(port, 0xf5, 0x05);
+	EXIT_CONFIG_MODE(port);
+}
+
+void ali_m1535plus_init(struct pci_dev *dev)
+{
+	pci_write_config_byte(dev, 0x40, 0x18); /* PCI Interface Control */
+	pci_write_config_byte(dev, 0x41, 0xc0); /* PS2 keyb & mouse enable */
+	pci_write_config_byte(dev, 0x42, 0x41); /* ISA bus cycle control */
+	pci_write_config_byte(dev, 0x43, 0x00); /* ISA bus cycle control 2 */
+	pci_write_config_byte(dev, 0x44, 0x5d); /* IDE enable & IRQ 14 */
+	pci_write_config_byte(dev, 0x45, 0x0b); /* PCI int polling mode */
+	pci_write_config_byte(dev, 0x47, 0x00); /* BIOS chip select control */
+
+	/* IRQ routing */
+	pci_write_config_byte(dev, 0x48, 0x03); /* INTA IRQ10, INTB disable */
+	pci_write_config_byte(dev, 0x49, 0x00); /* INTC and INTD disable */
+	pci_write_config_byte(dev, 0x4a, 0x00); /* INTE and INTF disable */
+	pci_write_config_byte(dev, 0x4b, 0x90); /* Audio IRQ11, Modem disable */
+
+	pci_write_config_word(dev, 0x50, 0x4000); /* Parity check IDE enable */
+	pci_write_config_word(dev, 0x52, 0x0000); /* USB & RTC disable */
+	pci_write_config_word(dev, 0x54, 0x0002); /* ??? no info */
+	pci_write_config_word(dev, 0x56, 0x0002); /* PCS1J signal disable */
+
+	pci_write_config_byte(dev, 0x59, 0x00); /* PCSDS */
+	pci_write_config_byte(dev, 0x5a, 0x00);
+	pci_write_config_byte(dev, 0x5b, 0x00);
+	pci_write_config_word(dev, 0x5c, 0x0000);
+	pci_write_config_byte(dev, 0x5e, 0x00);
+	pci_write_config_byte(dev, 0x5f, 0x00);
+	pci_write_config_word(dev, 0x60, 0x0000);
+
+	pci_write_config_byte(dev, 0x6c, 0x00);
+	pci_write_config_byte(dev, 0x6d, 0x48); /* ROM address mapping */
+	pci_write_config_byte(dev, 0x6e, 0x00); /* ??? what for? */
+
+	pci_write_config_byte(dev, 0x70, 0x12); /* Serial IRQ control */
+	pci_write_config_byte(dev, 0x71, 0xEF); /* DMA channel select */
+	pci_write_config_byte(dev, 0x72, 0x03); /* USB IDSEL */
+	pci_write_config_byte(dev, 0x73, 0x00); /* ??? no info */
+
+	/*
+	 * IRQ setup ALi M5237 USB Host Controller
+	 * IRQ: 9
+	 */
+	pci_write_config_byte(dev, 0x74, 0x01); /* USB IRQ9 */
+
+	pci_write_config_byte(dev, 0x75, 0x1f); /* IDE2 IRQ 15  */
+	pci_write_config_byte(dev, 0x76, 0x80); /* ACPI disable */
+	pci_write_config_byte(dev, 0x77, 0x40); /* Modem disable */
+	pci_write_config_dword(dev, 0x78, 0x20000000); /* Pin select 2 */
+	pci_write_config_byte(dev, 0x7c, 0x00); /* Pin select 3 */
+	pci_write_config_byte(dev, 0x81, 0x00); /* ID read/write control */
+	pci_write_config_byte(dev, 0x90, 0x00); /* PCI PM block control */
+	pci_write_config_word(dev, 0xa4, 0x0000); /* PMSCR */
+
+#ifdef CONFIG_BLK_DEV_FD
+	ali_m1535plus_fdc_init(1);
+#endif
+
+#ifdef CONFIG_PC_KEYB
+	ali_m1535plus_keyboard_init(1);
+	ali_m1535plus_hotkey_init(1);
+#endif
+}
+
+static inline void ali_config_writeb(u8 reg, u8 val, int devfn)
+{
+	u32 data;
+	int shift;
+
+	writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
+        data = readl(PCI_CONFIG_DATA);
+
+	shift = (reg & 3) << 3;
+	data &= ~(0xff << shift);
+	data |= (((u32)val) << shift);
+
+	writel(data, PCI_CONFIG_DATA);
+}
+
+static inline u8 ali_config_readb(u8 reg, int devfn)
+{
+	u32 data;
+
+	writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
+	data = readl(PCI_CONFIG_DATA);
+
+	return (u8)(data >> ((reg & 3) << 3));
+}
+
+static inline u16 ali_config_readw(u8 reg, int devfn)
+{
+	u32 data;
+
+	writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
+	data = readl(PCI_CONFIG_DATA);
+
+	return (u16)(data >> ((reg & 2) << 3));
+}
+
+int vr4133_rockhopper = 0;
+void __init ali_m5229_preinit(void)
+{
+	if (ali_config_readw(PCI_VENDOR_ID,16) == PCI_VENDOR_ID_AL &&
+	    ali_config_readw(PCI_DEVICE_ID,16) == PCI_DEVICE_ID_AL_M1533) {
+		printk(KERN_INFO "Found an NEC Rockhopper \n");
+		vr4133_rockhopper = 1;
+		/*
+		 * Enable ALi M5229 IDE Controller (both channels)
+		 * IDSEL: A27
+		 */
+		ali_config_writeb(0x58, 0x4c, 16);
+	}
+}
+
+void __init ali_m5229_init(struct pci_dev *dev)
+{
+	/*
+	 * Enable Primary/Secondary Channel Cable Detect 40-Pin
+	 */
+	pci_write_config_word(dev, 0x4a, 0xc023);
+
+	/*
+	 * Set only the 3rd byteis for the master IDE's cycle and
+	 * enable Internal IDE Function
+	 */
+	pci_write_config_byte(dev, 0x50, 0x23); /* Class code attr register */
+
+	pci_write_config_byte(dev, 0x09, 0xff); /* Set native mode & stuff */
+	pci_write_config_byte(dev, 0x52, 0x00); /* use timing registers */
+	pci_write_config_byte(dev, 0x58, 0x02); /* Primary addr setup timing */
+	pci_write_config_byte(dev, 0x59, 0x22); /* Primary cmd block timing */
+	pci_write_config_byte(dev, 0x5a, 0x22); /* Pr drv 0 R/W timing */
+	pci_write_config_byte(dev, 0x5b, 0x22); /* Pr drv 1 R/W timing */
+	pci_write_config_byte(dev, 0x5c, 0x02); /* Sec addr setup timing */
+	pci_write_config_byte(dev, 0x5d, 0x22); /* Sec cmd block timing */
+	pci_write_config_byte(dev, 0x5e, 0x22); /* Sec drv 0 R/W timing */
+	pci_write_config_byte(dev, 0x5f, 0x22); /* Sec drv 1 R/W timing */
+	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
+	pci_write_config_word(dev, PCI_COMMAND,
+	                           PCI_COMMAND_PARITY | PCI_COMMAND_MASTER |
+				   PCI_COMMAND_IO);
+}
+
arch/mips/vr41xx/nec-cmbvr4133/init.c new file +81 -0

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arch/mips/vr41xx/nec-cmbvr4133/setup.c new file +127 -0

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arch/mips/vr41xx/nec-cmbvr4133/irq.c new file +114 -0

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arch/mips/vr41xx/nec-cmbvr4133/Makefile new file +8 -0
Index: linux/arch/mips/vr41xx/nec-cmbvr4133/Makefile
===================================================================
@@ -0,0 +1,8 @@
+#
+# Makefile for the NEC-CMBVR4133
+#
+
+obj-y				:= init.o setup.o
+
+obj-$(CONFIG_PCI)		+= m1535plus.o
+obj-$(CONFIG_ROCKHOPPER)	+= irq.o
arch/mips/Makefile +6 -0
Index: linux/arch/mips/Makefile
===================================================================
@@ -486,6 +486,12 @@
 cflags-$(CONFIG_MACH_VR41XX)	+= -Iinclude/asm-mips/mach-vr41xx
 
 #
+# NEC VR4133
+#
+core-$(CONFIG_NEC_CMBVR4133)	+= arch/mips/vr41xx/nec-cmbvr4133/
+load-$(CONFIG_NEC_CMBVR4133)	+= 0xffffffff80100000
+
+#
 # ZAO Networks Capcella (VR4131)
 #
 core-$(CONFIG_ZAO_CAPCELLA)	+= arch/mips/vr41xx/zao-capcella/
include/asm-mips/vr41xx/cmbvr4133.h new file +93 -0

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arch/mips/vr41xx/common/vr4133.c new file +75 -0

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include/asm-mips/vr41xx/vr4133.h new file +25 -0
Index: linux/include/asm-mips/vr41xx/vr4133.h
===================================================================
@@ -0,0 +1,25 @@
+/*
+ * include/asm-mips/vr41xx/vr4133.h
+ *
+ * Include file for NEC VR4133.
+ *
+ * Author: Alex Sapkov <[email protected]> or <[email protected]>
+ *
+ * 2004 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __NEC_VR4133_H
+#define __NEC_VR4133_H
+/*
+ * Clock Mask Unit
+ */
+extern void vr4133_clock_ether0_supply(void);
+extern void vr4133_clock_ether1_supply(void);
+extern void vr4133_clock_ceu_supply(void);
+extern void vr4133_clock_ether0_mask(void);
+extern void vr4133_clock_ether1_mask(void);
+extern void vr4133_clock_ceu_mask(void);
+
+#endif /* __NEC_VR4133_H */
arch/mips/Kconfig +15 -0
Index: linux/arch/mips/Kconfig
===================================================================
@@ -69,6 +69,21 @@
 config MACH_VR41XX
 	bool "Support for NEC VR41XX-based machines"
 
+config NEC_CMBVR4133
+	bool "Support for NEC CMB-VR4133"
+	depends on MACH_VR41XX
+	select CPU_VR41XX
+	select DMA_NONCOHERENT
+	select IRQ_CPU
+	select HW_HAS_PCI
+	select PCI_VR41XX
+
+config ROCKHOPPER
+	bool "Support for Rockhopper baseboard"
+	depends on NEC_CMBVR4133
+	select I8259
+	select HAVE_STD_PC_SERIAL_PORT
+
 config CASIO_E55
 	bool "Support for CASIO CASSIOPEIA E-10/15/55/65"
 	depends on MACH_VR41XX
include/asm-mips/bootinfo.h +1 -0
Index: linux/include/asm-mips/bootinfo.h
===================================================================
@@ -195,6 +195,7 @@
 #define  MACH_CASIO_E55		5	/* CASIO CASSIOPEIA E-10/15/55/65 */
 #define  MACH_TANBAC_TB0226	6	/* TANBAC TB0226 (Mbase) */
 #define  MACH_TANBAC_TB0229	7	/* TANBAC TB0229 (VR4131DIMM) */
+#define  MACH_NEC_CMBVR4133	8	/* CMB VR4133 Board */
 
 #define MACH_GROUP_HP_LJ	20	/* Hewlett Packard LaserJet	*/
 #define  MACH_HP_LASERJET	1
arch/mips/pci/Makefile +1 -0
Index: linux/arch/mips/pci/Makefile
===================================================================
@@ -17,6 +17,7 @@
 obj-$(CONFIG_MIPS_NILE4)	+= ops-nile4.o
 obj-$(CONFIG_MIPS_TX3927)	+= ops-jmr3927.o
 obj-$(CONFIG_PCI_VR41XX)	+= ops-vr41xx.o pci-vr41xx.o
+obj-$(CONFIG_NEC_CMBVR4133)	+= fixup-vr4133.o
 
 #
 # These are still pretty much in the old state, watch, go blind.
arch/mips/vr41xx/common/Makefile +1 -0
Index: linux/arch/mips/vr41xx/common/Makefile
===================================================================
@@ -6,5 +6,6 @@
 obj-$(CONFIG_SERIAL_8250)	+= serial.o
 obj-$(CONFIG_VRC4171)		+= vrc4171.o
 obj-$(CONFIG_VRC4173)		+= vrc4173.o
+obj-$(NEC_CMBVR4133)		+= vr4133.o
 
 EXTRA_AFLAGS := $(CFLAGS)
arch/mips/pci/fixup-vr4133.c new file +214 -0

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arch/mips/pci/pci-vr41xx.h +6 -0
Index: linux/arch/mips/pci/pci-vr41xx.h
===================================================================
@@ -18,6 +18,8 @@
  *  You should have received a copy of the GNU General Public License
  *  along with this program; if not, write to the Free Software
  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *  Support for NEC VR4133 in 2.6 - Manish Lachwani ([email protected])
  */
 #ifndef __PCI_VR41XX_H
 #define __PCI_VR41XX_H

@@ -127,6 +129,10 @@
 #define PCI_MASTER_MEM1_ADDRESS_MASK		0x7c000000U
 #define PCI_MASTER_MEM1_PCI_BASE_ADDRESS	0x10000000U
 
+#define PCI_MASTER_MEM2_BUS_BASE_ADDRESS	0x14000000U
+#define PCI_MASTER_MEM2_ADDRESS_MASK		0x7e000000U
+#define PCI_MASTER_MEM2_PCI_BASE_ADDRESS	0x14000000U
+
 #define PCI_TARGET_MEM1_ADDRESS_MASK		0x08000000U
 #define PCI_TARGET_MEM1_BUS_BASE_ADDRESS	0x00000000U
arch/mips/pci/pci-vr41xx.c +25 -0
Index: linux/arch/mips/pci/pci-vr41xx.c
===================================================================
@@ -19,6 +19,8 @@
  *  You should have received a copy of the GNU General Public License
  *  along with this program; if not, write to the Free Software
  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *  Support for NEC VR4133 in 2.6 - Manish Lachwani ([email protected])
  */
 /*
  * Changes:

@@ -43,6 +45,12 @@
 	.pci_base_address	= PCI_MASTER_MEM1_PCI_BASE_ADDRESS,
 };
 
+static struct pci_master_address_conversion pci_master_memory2 = {
+	.bus_base_address	= PCI_MASTER_MEM2_BUS_BASE_ADDRESS,
+	.address_mask		= PCI_MASTER_MEM2_ADDRESS_MASK,
+	.pci_base_address	= PCI_MASTER_MEM2_PCI_BASE_ADDRESS,
+};
+
 static struct pci_target_address_conversion pci_target_memory1 = {
 	.address_mask		= PCI_TARGET_MEM1_ADDRESS_MASK,
 	.bus_base_address	= PCI_TARGET_MEM1_BUS_BASE_ADDRESS,

@@ -76,6 +84,22 @@
 	.flags  = IORESOURCE_IO,
 };
 
+#ifdef CONFIG_ROCKHOPPER
+static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = {
+	.master_memory1				= &pci_master_memory1,
+	.master_memory2				= &pci_master_memory2,
+	.target_memory1				= &pci_target_memory1,
+	.master_io				= &pci_master_io,
+	.exclusive_access			= CANNOT_LOCK_FROM_DEVICE,
+	.wait_time_limit_from_irdy_to_trdy	= 0,
+	.mailbox				= &pci_mailbox,
+	.target_window1				= &pci_target_window1,
+	.master_latency_timer			= 0x80,
+	.retry_limit				= 0,
+	.arbiter_priority_control		= PCI_ARBITRATION_MODE_FAIR,
+	.take_away_gnt_mode			= PCI_TAKE_AWAY_GNT_DISABLE,
+};
+#else
 static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = {
 	.master_memory1				= &pci_master_memory1,
 	.target_memory1				= &pci_target_memory1,

@@ -89,6 +113,7 @@
 	.arbiter_priority_control		= PCI_ARBITRATION_MODE_FAIR,
 	.take_away_gnt_mode			= PCI_TAKE_AWAY_GNT_DISABLE,
 };
+#endif
 
 static struct pci_controller vr41xx_pci_controller = {
 	.pci_ops        = &vr41xx_pci_ops,
arch/mips/vr41xx/common/serial.c +7 -7
Index: linux/arch/mips/vr41xx/common/serial.c
===================================================================
@@ -52,17 +52,17 @@
  #define TMICTX			0x10
  #define TMICMODE		0x20
 
-#define SIU_BASE_TYPE1		0x0c000000UL	/* VR4111 and VR4121 */
-#define SIU_BASE_TYPE2		0x0f000800UL	/* VR4122, VR4131 and VR4133 */
+#define SIU_BASE_TYPE1		KSEG1ADDR(0x0c000000)	/* VR4111 and VR4121 */
+#define SIU_BASE_TYPE2		KSEG1ADDR(0x0f000800)	/* VR4122, VR4131 and VR4133 */
 #define SIU_SIZE		0x8UL
 
-#define SIU_BASE_BAUD		1152000
+#define SIU_BASE_BAUD		115200
 
 /* VR4122, VR4131 and VR4133 DSIU Registers */
-#define DSIU_BASE		0x0f000820UL
+#define DSIU_BASE		KSEG1ADDR(0x0f000820)
 #define DSIU_SIZE		0x8UL
 
-#define DSIU_BASE_BAUD		1152000
+#define DSIU_BASE_BAUD	 	115200
 
 int vr41xx_serial_ports = 0;
 

@@ -132,7 +132,7 @@
 	}
 	port.regshift = 0;
 	port.iotype = UPIO_MEM;
-	port.membase = ioremap(port.mapbase, SIU_SIZE);
+	port.membase = (unsigned char *)port.mapbase;
 	if (port.membase != NULL) {
 		if (early_serial_setup(&port) == 0) {
 			vr41xx_supply_clock(SIU_CLOCK);

@@ -164,7 +164,7 @@
 	port.mapbase = DSIU_BASE;
 	port.regshift = 0;
 	port.iotype = UPIO_MEM;
-	port.membase = ioremap(port.mapbase, DSIU_SIZE);
+	port.membase = (unsigned char *)port.mapbase;
 	if (port.membase != NULL) {
 		if (early_serial_setup(&port) == 0) {
 			vr41xx_supply_clock(DSIU_CLOCK);
#1 lore raw

Hi Manish,

I have a few comment ;p

Quoted 53 lines · On Thu, 18 Nov 2004 11:52:19 -0800 Manish Lachwani…

Hi Ralf

Attached patch implements support for NEC VR4133 and NEC Rockhopper in 2.6. Currently there is no ethernet driver for the ports on the CMB-VR4133.

The board has been booted with the Onboard PcNet32 network interface and with an Intel EEPRO100 PCI NIC card.

Please review ...

Thanks
Manish Lachwani

Index: linux/arch/mips/vr41xx/nec-cmbvr4133/init.c
===================================================================

arch/mips/vr41xx/nec-cmbvr4133/init.c new file +35 -0
@@ -0,0 +1,81 @@
+/*
+ * arch/mips/vr41xx/nec-cmbvr4133/init.c
+ *
+ * PROM library initialisation code for NEC CMB-VR4133 board.
+ *
+ * Author: Yoichi Yuasa <[email protected], or [email protected]> and
+ *         Jun Sun <[email protected], or [email protected]> and
+ *         Alex Sapkov <[email protected]>
+ *
+ * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for NEC-CMBVR4133 in 2.6 
+ * Manish Lachwani ([email protected])
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+
+#ifdef CONFIG_ROCKHOPPER
+#include <asm/io.h>
+#include <linux/pci.h>
+
+#define PCICONFDREG	0xaf000c14
+#define PCICONFAREG	0xaf000c18
+#endif
+
+const char *get_system_type(void)
+{
+	return "NEC CMB-VR4133";

arch/mips/vr41xx/nec-cmbvr4133/init.c line 45

Quoted 10 lines
arch/mips/vr41xx/nec-cmbvr4133/init.c new file +10 -0
+}
+
+void __init bus_error_init(void)
+{
+	/* Do Nothing */
+}
+
+#ifdef CONFIG_ROCKHOPPER
+void disable_pcnet(void)
+{

We don't need bus_error_init().
I think that we should move get_system_type() and disable_pcnet() to setup.c.

Quoted 4 lines

Index: linux/arch/mips/vr41xx/nec-cmbvr4133/setup.c
===================================================================

arch/mips/vr41xx/nec-cmbvr4133/setup.c new file +0 -0

<snip>

Quoted 9 lines
arch/mips/vr41xx/nec-cmbvr4133/setup.c new file +9 -0
+void vr41xx_restart(char *command)
+{
+	change_c0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL));
+	change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+	flush_cache_all();
+	write_c0_wired(0);
+	__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
+}
+

arch/mips/vr41xx/nec-cmbvr4133/setup.c line 76

Quoted 10 lines
arch/mips/vr41xx/nec-cmbvr4133/setup.c new file +10 -0
+void vr41xx_halt(void)
+{
+	printk(KERN_NOTICE "\n** You can safely turn off the power\n");
+	while (1);
+}
+                                                                                             
+void vr41xx_power_off(void)
+{
+	vr41xx_halt();
+}

We don't need these functions. We already have these in common part.

<snip>

arch/mips/vr41xx/nec-cmbvr4133/setup.c line 94

Quoted 8 lines
arch/mips/vr41xx/nec-cmbvr4133/setup.c new file +8 -0
+static int __init nec_cmbvr4133_setup(void)
+{
+#ifdef CONFIG_ROCKHOPPER
+	extern void disable_pcnet(void);
+
+	disable_pcnet();
+#endif
+	set_io_port_base(IO_PORT_BASE);

We don't need set_io_port_base().
It already set in common part.

<snip>

arch/mips/vr41xx/nec-cmbvr4133/setup.c line 101

Quoted 3 lines
arch/mips/vr41xx/nec-cmbvr4133/setup.c new file +3 -0
+	_machine_restart = vr41xx_restart;
+	_machine_halt = vr41xx_halt;
+	_machine_power_off = vr41xx_power_off;

We don't need these.

arch/mips/vr41xx/nec-cmbvr4133/setup.c line 103

Quoted 1 line
arch/mips/vr41xx/nec-cmbvr4133/setup.c new file +1 -0
+	late_time_init = vr4133_serial_init;

This should just only do vr4133_serial_init().
This function don't need to late_time_init.

Quoted 7 lines

Index: linux/include/asm-mips/vr41xx/cmbvr4133.h
===================================================================

include/asm-mips/vr41xx/cmbvr4133.h new file +2 -0
@@ -0,0 +1,93 @@
+/*
+ * include/asm-mips/vr41xx/cmbvr4133.h

<snip>

Quoted 19 lines
include/asm-mips/vr41xx/cmbvr4133.h new file +19 -0
+/*
+ * Board specific address mapping
+ */
+#define VR41XX_PCI_MEM1_BASE		0x10000000
+#define VR41XX_PCI_MEM1_SIZE		0x04000000
+#define VR41XX_PCI_MEM1_MASK		0x7c000000
+
+#define VR41XX_PCI_MEM2_BASE		0x14000000
+#define VR41XX_PCI_MEM2_SIZE		0x02000000
+#define VR41XX_PCI_MEM2_MASK		0x7e000000
+
+#define VR41XX_PCI_IO_BASE		0x16000000
+#define VR41XX_PCI_IO_SIZE		0x02000000
+#define VR41XX_PCI_IO_MASK		0x7e000000
+
+#define VR41XX_PCI_IO_START		0x01000000
+#define VR41XX_PCI_IO_END		0x01ffffff
+
+#define VR41XX_PCI_MEM_START		0x12000000

include/asm-mips/vr41xx/cmbvr4133.h line 52

Quoted 10 lines
include/asm-mips/vr41xx/cmbvr4133.h new file +10 -0
+#define VR41XX_PCI_MEM_END		0x15ffffff
+
+#define IO_PORT_BASE			KSEG1ADDR(VR41XX_PCI_IO_BASE)
+#define IO_PORT_RESOURCE_START		0
+#define IO_PORT_RESOURCE_END		VR41XX_PCI_IO_SIZE
+#define IO_MEM1_RESOURCE_START		VR41XX_PCI_MEM1_BASE
+#define IO_MEM1_RESOURCE_END		(VR41XX_PCI_MEM1_BASE + VR41XX_PCI_MEM1_SIZE)
+#define IO_MEM2_RESOURCE_START		VR41XX_PCI_MEM2_BASE
+#define IO_MEM2_RESOURCE_END		(VR41XX_PCI_MEM2_BASE + VR41XX_PCI_MEM2_SIZE)
+

We don't need these definitions.
These definitions are not used.

arch/mips/vr41xx/common/vr4133.c

Quoted 5 lines

Index: linux/arch/mips/vr41xx/common/vr4133.c
===================================================================

arch/mips/vr41xx/common/vr4133.c new file +0 -0
@@ -0,0 +1,75 @@

We don't need these functions. We already have these in common part.

include/asm-mips/vr41xx/vr4133.h

Quoted 5 lines

Index: linux/include/asm-mips/vr41xx/vr4133.h
===================================================================

include/asm-mips/vr41xx/vr4133.h new file +0 -0
@@ -0,0 +1,25 @@

Same, we don't need it.

Quoted 74 lines

Index: linux/arch/mips/pci/pci-vr41xx.h
===================================================================

arch/mips/pci/pci-vr41xx.h +6 -0
@@ -18,6 +18,8 @@
  *  You should have received a copy of the GNU General Public License
  *  along with this program; if not, write to the Free Software
  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *  Support for NEC VR4133 in 2.6 - Manish Lachwani ([email protected])
  */
 #ifndef __PCI_VR41XX_H
 #define __PCI_VR41XX_H

@@ -127,6 +129,10 @@
 #define PCI_MASTER_MEM1_ADDRESS_MASK		0x7c000000U
 #define PCI_MASTER_MEM1_PCI_BASE_ADDRESS	0x10000000U
 
+#define PCI_MASTER_MEM2_BUS_BASE_ADDRESS	0x14000000U
+#define PCI_MASTER_MEM2_ADDRESS_MASK		0x7e000000U
+#define PCI_MASTER_MEM2_PCI_BASE_ADDRESS	0x14000000U
+
 #define PCI_TARGET_MEM1_ADDRESS_MASK		0x08000000U
 #define PCI_TARGET_MEM1_BUS_BASE_ADDRESS	0x00000000U

Index: linux/arch/mips/pci/pci-vr41xx.c
===================================================================

arch/mips/pci/pci-vr41xx.c +24 -0
@@ -19,6 +19,8 @@
  *  You should have received a copy of the GNU General Public License
  *  along with this program; if not, write to the Free Software
  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *  Support for NEC VR4133 in 2.6 - Manish Lachwani ([email protected])
  */
 /*
  * Changes:

@@ -43,6 +45,12 @@
 	.pci_base_address	= PCI_MASTER_MEM1_PCI_BASE_ADDRESS,
 };
 
+static struct pci_master_address_conversion pci_master_memory2 = {
+	.bus_base_address	= PCI_MASTER_MEM2_BUS_BASE_ADDRESS,
+	.address_mask		= PCI_MASTER_MEM2_ADDRESS_MASK,
+	.pci_base_address	= PCI_MASTER_MEM2_PCI_BASE_ADDRESS,
+};
+
 static struct pci_target_address_conversion pci_target_memory1 = {
 	.address_mask		= PCI_TARGET_MEM1_ADDRESS_MASK,
 	.bus_base_address	= PCI_TARGET_MEM1_BUS_BASE_ADDRESS,

@@ -76,6 +84,22 @@
 	.flags  = IORESOURCE_IO,
 };
 
+#ifdef CONFIG_ROCKHOPPER
+static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = {
+	.master_memory1				= &pci_master_memory1,
+	.master_memory2				= &pci_master_memory2,
+	.target_memory1				= &pci_target_memory1,
+	.master_io				= &pci_master_io,
+	.exclusive_access			= CANNOT_LOCK_FROM_DEVICE,
+	.wait_time_limit_from_irdy_to_trdy	= 0,
+	.mailbox				= &pci_mailbox,
+	.target_window1				= &pci_target_window1,
+	.master_latency_timer			= 0x80,
+	.retry_limit				= 0,
+	.arbiter_priority_control		= PCI_ARBITRATION_MODE_FAIR,
+	.take_away_gnt_mode			= PCI_TAKE_AWAY_GNT_DISABLE,
+};
+#else
 static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = {
 	.master_memory1				= &pci_master_memory1,
 	.target_memory1				= &pci_target_memory1,

arch/mips/pci/pci-vr41xx.c line 119

Quoted 7 lines
arch/mips/pci/pci-vr41xx.c +1 -0
@@ -89,6 +113,7 @@
 	.arbiter_priority_control		= PCI_ARBITRATION_MODE_FAIR,
 	.take_away_gnt_mode			= PCI_TAKE_AWAY_GNT_DISABLE,
 };
+#endif
 
 static struct pci_controller vr41xx_pci_controller = {
 	.pci_ops        = &vr41xx_pci_ops,

Since pci_master_memory2 was the area which is not used, it was deleted. If you need this area, please let me know a reason.

Quoted 6 lines

Index: linux/arch/mips/vr41xx/common/serial.c
===================================================================

arch/mips/vr41xx/common/serial.c +0 -0
@@ -52,17 +52,17 @@
  #define TMICTX			0x10

arch/mips/vr41xx/common/serial.c line 59

Quoted 10 lines
arch/mips/vr41xx/common/serial.c +3 -3
  #define TMICMODE		0x20
 
-#define SIU_BASE_TYPE1		0x0c000000UL	/* VR4111 and VR4121 */
-#define SIU_BASE_TYPE2		0x0f000800UL	/* VR4122, VR4131 and VR4133 */
+#define SIU_BASE_TYPE1		KSEG1ADDR(0x0c000000)	/* VR4111 and VR4121 */
+#define SIU_BASE_TYPE2		KSEG1ADDR(0x0f000800)	/* VR4122, VR4131 and VR4133 */
 #define SIU_SIZE		0x8UL
 
-#define SIU_BASE_BAUD		1152000
+#define SIU_BASE_BAUD		115200

SIU base baud is 1152000. This change is wrong.

arch/mips/vr41xx/common/serial.c line 65

Quoted 7 lines
arch/mips/vr41xx/common/serial.c +2 -2
 /* VR4122, VR4131 and VR4133 DSIU Registers */
-#define DSIU_BASE		0x0f000820UL
+#define DSIU_BASE		KSEG1ADDR(0x0f000820)
 #define DSIU_SIZE		0x8UL
 
-#define DSIU_BASE_BAUD		1152000
+#define DSIU_BASE_BAUD	 	115200

DSIU base baud is 1152000. This change is wrong.

Quoted 13 lines
arch/mips/vr41xx/common/serial.c +1 -1
 int vr41xx_serial_ports = 0;
 

@@ -132,7 +132,7 @@
 	}
 	port.regshift = 0;
 	port.iotype = UPIO_MEM;
-	port.membase = ioremap(port.mapbase, SIU_SIZE);
+	port.membase = (unsigned char *)port.mapbase;
 	if (port.membase != NULL) {
 		if (early_serial_setup(&port) == 0) {
 			vr41xx_supply_clock(SIU_CLOCK);

arch/mips/vr41xx/common/serial.c line 170

Quoted 8 lines
arch/mips/vr41xx/common/serial.c +1 -1
@@ -164,7 +164,7 @@
 	port.mapbase = DSIU_BASE;
 	port.regshift = 0;
 	port.iotype = UPIO_MEM;
-	port.membase = ioremap(port.mapbase, DSIU_SIZE);
+	port.membase = (unsigned char *)port.mapbase;
 	if (port.membase != NULL) {
 		if (early_serial_setup(&port) == 0) {
 			vr41xx_supply_clock(DSIU_CLOCK);

These changes are same meaning.
We don't need these.

Yoichi

#2 lore raw

Hi Yoichi,

Thanks for the comments. My comments below:

Quoted 110 lines · Yoichi Yuasa

Hi Manish,

I have a few comment ;p

Quoted 53 lines · On Thu, 18 Nov 2004 11:52:19 -0800 Manish Lachwani…

Hi Ralf

Attached patch implements support for NEC VR4133 and NEC Rockhopper in 2.6. Currently there is no ethernet driver for the ports on the CMB-VR4133.

The board has been booted with the Onboard PcNet32 network interface and with an Intel EEPRO100 PCI NIC card.

Please review ...

Thanks
Manish Lachwani

Index: linux/arch/mips/vr41xx/nec-cmbvr4133/init.c
===================================================================

arch/mips/vr41xx/nec-cmbvr4133/init.c new file +35 -0
@@ -0,0 +1,81 @@
+/*
+ * arch/mips/vr41xx/nec-cmbvr4133/init.c
+ *
+ * PROM library initialisation code for NEC CMB-VR4133 board.
+ *
+ * Author: Yoichi Yuasa <[email protected], or [email protected]> and
+ *         Jun Sun <[email protected], or [email protected]> and
+ *         Alex Sapkov <[email protected]>
+ *
+ * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for NEC-CMBVR4133 in 2.6 
+ * Manish Lachwani ([email protected])
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+
+#ifdef CONFIG_ROCKHOPPER
+#include <asm/io.h>
+#include <linux/pci.h>
+
+#define PCICONFDREG	0xaf000c14
+#define PCICONFAREG	0xaf000c18
+#endif
+
+const char *get_system_type(void)
+{
+	return "NEC CMB-VR4133";

arch/mips/vr41xx/nec-cmbvr4133/init.c line 45

Quoted 10 lines
arch/mips/vr41xx/nec-cmbvr4133/init.c new file +10 -0
+}
+
+void __init bus_error_init(void)
+{
+	/* Do Nothing */
+}
+
+#ifdef CONFIG_ROCKHOPPER
+void disable_pcnet(void)
+{

We don't need bus_error_init().
I think that we should move get_system_type() and disable_pcnet() to setup.c.

Quoted 4 lines

Index: linux/arch/mips/vr41xx/nec-cmbvr4133/setup.c
===================================================================

arch/mips/vr41xx/nec-cmbvr4133/setup.c new file +0 -0

<snip>

Quoted 9 lines
arch/mips/vr41xx/nec-cmbvr4133/setup.c new file +9 -0
+void vr41xx_restart(char *command)
+{
+	change_c0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL));
+	change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+	flush_cache_all();
+	write_c0_wired(0);
+	__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
+}
+

arch/mips/vr41xx/nec-cmbvr4133/setup.c line 76

Quoted 10 lines
arch/mips/vr41xx/nec-cmbvr4133/setup.c new file +10 -0
+void vr41xx_halt(void)
+{
+	printk(KERN_NOTICE "\n** You can safely turn off the power\n");
+	while (1);
+}
+                                                                                             
+void vr41xx_power_off(void)
+{
+	vr41xx_halt();
+}

We don't need these functions. We already have these in common part.

<snip>

Quoted 12 lines

arch/mips/vr41xx/nec-cmbvr4133/setup.c line 94

Quoted 8 lines
arch/mips/vr41xx/nec-cmbvr4133/setup.c new file +8 -0
+static int __init nec_cmbvr4133_setup(void)
+{
+#ifdef CONFIG_ROCKHOPPER
+	extern void disable_pcnet(void);
+
+	disable_pcnet();
+#endif
+	set_io_port_base(IO_PORT_BASE);

We don't need set_io_port_base().
It already set in common part.

We need to do set_io_port_base() here else it will cause a TLB exception and fall back into the PROM.

Quoted 11 lines

<snip>

arch/mips/vr41xx/nec-cmbvr4133/setup.c line 101

Quoted 3 lines
arch/mips/vr41xx/nec-cmbvr4133/setup.c new file +3 -0
+	_machine_restart = vr41xx_restart;
+	_machine_halt = vr41xx_halt;
+	_machine_power_off = vr41xx_power_off;

We don't need these.

Quoted 5 lines

arch/mips/vr41xx/nec-cmbvr4133/setup.c line 103

Quoted 1 line
arch/mips/vr41xx/nec-cmbvr4133/setup.c new file +1 -0
+	late_time_init = vr4133_serial_init;

This should just only do vr4133_serial_init().
This function don't need to late_time_init.

We need to call vr4133_serial_init() after console_init(). Hence, this change. The idea is that late_time_init() will be called after console_init() in init/main.c

Quoted 181 lines
Quoted 9 lines

Index: linux/include/asm-mips/vr41xx/cmbvr4133.h
===================================================================

include/asm-mips/vr41xx/cmbvr4133.h new file +2 -0
@@ -0,0 +1,93 @@
+/*
+ * include/asm-mips/vr41xx/cmbvr4133.h

<snip>

Quoted 19 lines
include/asm-mips/vr41xx/cmbvr4133.h new file +19 -0
+/*
+ * Board specific address mapping
+ */
+#define VR41XX_PCI_MEM1_BASE		0x10000000
+#define VR41XX_PCI_MEM1_SIZE		0x04000000
+#define VR41XX_PCI_MEM1_MASK		0x7c000000
+
+#define VR41XX_PCI_MEM2_BASE		0x14000000
+#define VR41XX_PCI_MEM2_SIZE		0x02000000
+#define VR41XX_PCI_MEM2_MASK		0x7e000000
+
+#define VR41XX_PCI_IO_BASE		0x16000000
+#define VR41XX_PCI_IO_SIZE		0x02000000
+#define VR41XX_PCI_IO_MASK		0x7e000000
+
+#define VR41XX_PCI_IO_START		0x01000000
+#define VR41XX_PCI_IO_END		0x01ffffff
+
+#define VR41XX_PCI_MEM_START		0x12000000

include/asm-mips/vr41xx/cmbvr4133.h line 52

Quoted 10 lines
include/asm-mips/vr41xx/cmbvr4133.h new file +10 -0
+#define VR41XX_PCI_MEM_END		0x15ffffff
+
+#define IO_PORT_BASE			KSEG1ADDR(VR41XX_PCI_IO_BASE)
+#define IO_PORT_RESOURCE_START		0
+#define IO_PORT_RESOURCE_END		VR41XX_PCI_IO_SIZE
+#define IO_MEM1_RESOURCE_START		VR41XX_PCI_MEM1_BASE
+#define IO_MEM1_RESOURCE_END		(VR41XX_PCI_MEM1_BASE + VR41XX_PCI_MEM1_SIZE)
+#define IO_MEM2_RESOURCE_START		VR41XX_PCI_MEM2_BASE
+#define IO_MEM2_RESOURCE_END		(VR41XX_PCI_MEM2_BASE + VR41XX_PCI_MEM2_SIZE)
+

We don't need these definitions.
These definitions are not used.

arch/mips/vr41xx/common/vr4133.c

Quoted 5 lines

Index: linux/arch/mips/vr41xx/common/vr4133.c
===================================================================

arch/mips/vr41xx/common/vr4133.c new file +0 -0
@@ -0,0 +1,75 @@

We don't need these functions. We already have these in common part.

include/asm-mips/vr41xx/vr4133.h

Quoted 5 lines

Index: linux/include/asm-mips/vr41xx/vr4133.h
===================================================================

include/asm-mips/vr41xx/vr4133.h new file +0 -0
@@ -0,0 +1,25 @@

Same, we don't need it.

Quoted 74 lines

Index: linux/arch/mips/pci/pci-vr41xx.h
===================================================================

arch/mips/pci/pci-vr41xx.h +6 -0
@@ -18,6 +18,8 @@
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *  Support for NEC VR4133 in 2.6 - Manish Lachwani ([email protected])
 */
 #ifndef __PCI_VR41XX_H
 #define __PCI_VR41XX_H

@@ -127,6 +129,10 @@
 #define PCI_MASTER_MEM1_ADDRESS_MASK		0x7c000000U
 #define PCI_MASTER_MEM1_PCI_BASE_ADDRESS	0x10000000U
 
+#define PCI_MASTER_MEM2_BUS_BASE_ADDRESS	0x14000000U
+#define PCI_MASTER_MEM2_ADDRESS_MASK		0x7e000000U
+#define PCI_MASTER_MEM2_PCI_BASE_ADDRESS	0x14000000U
+
 #define PCI_TARGET_MEM1_ADDRESS_MASK		0x08000000U
 #define PCI_TARGET_MEM1_BUS_BASE_ADDRESS	0x00000000U

Index: linux/arch/mips/pci/pci-vr41xx.c
===================================================================

arch/mips/pci/pci-vr41xx.c +24 -0
@@ -19,6 +19,8 @@
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *  Support for NEC VR4133 in 2.6 - Manish Lachwani ([email protected])
 */
 /*
 * Changes:

@@ -43,6 +45,12 @@
 	.pci_base_address	= PCI_MASTER_MEM1_PCI_BASE_ADDRESS,
 };
 
+static struct pci_master_address_conversion pci_master_memory2 = {
+	.bus_base_address	= PCI_MASTER_MEM2_BUS_BASE_ADDRESS,
+	.address_mask		= PCI_MASTER_MEM2_ADDRESS_MASK,
+	.pci_base_address	= PCI_MASTER_MEM2_PCI_BASE_ADDRESS,
+};
+
 static struct pci_target_address_conversion pci_target_memory1 = {
 	.address_mask		= PCI_TARGET_MEM1_ADDRESS_MASK,
 	.bus_base_address	= PCI_TARGET_MEM1_BUS_BASE_ADDRESS,

@@ -76,6 +84,22 @@
 	.flags  = IORESOURCE_IO,
 };
 
+#ifdef CONFIG_ROCKHOPPER
+static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = {
+	.master_memory1				= &pci_master_memory1,
+	.master_memory2				= &pci_master_memory2,
+	.target_memory1				= &pci_target_memory1,
+	.master_io				= &pci_master_io,
+	.exclusive_access			= CANNOT_LOCK_FROM_DEVICE,
+	.wait_time_limit_from_irdy_to_trdy	= 0,
+	.mailbox				= &pci_mailbox,
+	.target_window1				= &pci_target_window1,
+	.master_latency_timer			= 0x80,
+	.retry_limit				= 0,
+	.arbiter_priority_control		= PCI_ARBITRATION_MODE_FAIR,
+	.take_away_gnt_mode			= PCI_TAKE_AWAY_GNT_DISABLE,
+};
+#else
 static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = {
 	.master_memory1				= &pci_master_memory1,
 	.target_memory1				= &pci_target_memory1,

arch/mips/pci/pci-vr41xx.c line 119

Quoted 7 lines
arch/mips/pci/pci-vr41xx.c +1 -0
@@ -89,6 +113,7 @@
 	.arbiter_priority_control		= PCI_ARBITRATION_MODE_FAIR,
 	.take_away_gnt_mode			= PCI_TAKE_AWAY_GNT_DISABLE,
 };
+#endif
 
 static struct pci_controller vr41xx_pci_controller = {
 	.pci_ops        = &vr41xx_pci_ops,

Since pci_master_memory2 was the area which is not used, it was deleted. If you need this area, please let me know a reason.

Quoted 6 lines

Index: linux/arch/mips/vr41xx/common/serial.c
===================================================================

arch/mips/vr41xx/common/serial.c +0 -0
@@ -52,17 +52,17 @@
 #define TMICTX			0x10

arch/mips/vr41xx/common/serial.c line 59

Quoted 10 lines
arch/mips/vr41xx/common/serial.c +3 -3
 #define TMICMODE		0x20
 
-#define SIU_BASE_TYPE1		0x0c000000UL	/* VR4111 and VR4121 */
-#define SIU_BASE_TYPE2		0x0f000800UL	/* VR4122, VR4131 and VR4133 */
+#define SIU_BASE_TYPE1		KSEG1ADDR(0x0c000000)	/* VR4111 and VR4121 */
+#define SIU_BASE_TYPE2		KSEG1ADDR(0x0f000800)	/* VR4122, VR4131 and VR4133 */
 #define SIU_SIZE		0x8UL
 
-#define SIU_BASE_BAUD		1152000
+#define SIU_BASE_BAUD		115200

SIU base baud is 1152000. This change is wrong.

Quoted 5 lines
arch/mips/vr41xx/common/serial.c +1 -1
 /* VR4122, VR4131 and VR4133 DSIU Registers */
-#define DSIU_BASE		0x0f000820UL
+#define DSIU_BASE		KSEG1ADDR(0x0f000820)
 #define DSIU_SIZE		0x8UL
Quoted 5 lines

arch/mips/vr41xx/common/serial.c line 65

Quoted 2 lines
arch/mips/vr41xx/common/serial.c +1 -1
-#define DSIU_BASE_BAUD		1152000
+#define DSIU_BASE_BAUD	 	115200

DSIU base baud is 1152000. This change is wrong.

My bad

Quoted 19 lines
Quoted 19 lines
arch/mips/vr41xx/common/serial.c +2 -2
 int vr41xx_serial_ports = 0;
 

@@ -132,7 +132,7 @@
 	}
 	port.regshift = 0;
 	port.iotype = UPIO_MEM;
-	port.membase = ioremap(port.mapbase, SIU_SIZE);
+	port.membase = (unsigned char *)port.mapbase;
 	if (port.membase != NULL) {
 		if (early_serial_setup(&port) == 0) {
 			vr41xx_supply_clock(SIU_CLOCK);

@@ -164,7 +164,7 @@
 	port.mapbase = DSIU_BASE;
 	port.regshift = 0;
 	port.iotype = UPIO_MEM;
-	port.membase = ioremap(port.mapbase, DSIU_SIZE);
+	port.membase = (unsigned char *)port.mapbase;
Quoted 8 lines

arch/mips/vr41xx/common/serial.c line 170

Quoted 4 lines
arch/mips/vr41xx/common/serial.c +0 -0
 	if (port.membase != NULL) {
 		if (early_serial_setup(&port) == 0) {
 			vr41xx_supply_clock(DSIU_CLOCK);

These changes are same meaning.
We don't need these.

I will look at the remaining changes which are unnecessary and generate a new patch

Thanks
Manish Lachwani

Quoted 4 lines

Yoichi