Avoid compile warnings on Sibyte using 2.6.10-rc3

PATCH In review Manish Lachwani 3 participants 7 messages Dec 15, 2004 – Dec 16, 2004 MIPS

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Manish Lachwani

author

2004-12-15 23:57 UTC #0 lore raw

PATCH 1/1 Avoid compile warnings on Sibyte using 2.6.10-rc3

Hi Ralf,

The attached patch is needed to prevent the compilation warnings that occur when using 2.6.10-rc3 on Sibyte. Please review

Thanks
Manish Lachwani

asm-mips/cpu-features.h renamed from asm-mips/cpu-features.h.orig +2 -0

@@ -92,8 +92,10 @@
 #define cpu_icache_snoops_remote_store	(cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
 #endif
 #else
+#ifndef cpu_icache_snoops_remote_store
 #define cpu_icache_snoops_remote_store	1
 #endif
+#endif
 
 /*
  * Certain CPUs may throw bizarre exceptions if not the whole cacheline

Steven J. Hill

2004-12-16 03:07 UTC #1 lore raw

Quoted 4 lines · Manish Lachwani

The attached patch is needed to prevent the compilation warnings that occur when using 2.6.10-rc3 on Sibyte. Please review

I don't ever see any warning associated with this. Can you provide a little more information?

-Steve

Manish Lachwani

author

2004-12-16 03:28 UTC #2 lore raw

Quoted 11 lines · Steven J. Hill

Quoted 3 lines · Manish Lachwani
The attached patch is needed to prevent the compilation warnings that occur when using 2.6.10-rc3 on Sibyte. Please review
I don't ever see any warning associated with this. Can you provide a little more information?
-Steve

Hi Steve,

When did you last sync with CVS? There was a change introduced : http://www.linux-mips.org/cvsweb/linux/include/asm-mips/mach-sibyte/cpu-feature-overrides.h.diff?r1=1.1&r2=1.2

There is another #define in include/asm-mips/

#ifdef CONFIG_SMP
#ifndef cpu_icache_snoops_remote_store
#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) #endif
#else
#define cpu_icache_snoops_remote_store 1
#endif

And if running Sibyte in UP mode, cpu_icache_snoops_remote_store is redefined

Thanks
Manish

Steven J. Hill

2004-12-16 03:44 UTC #3 lore raw

Quoted 3 lines · Manish Lachwani

When did you last sync with CVS? There was a change introduced :

Literally 10 minutes ago and I did a fresh compile.

Quoted 2 lines

And if running Sibyte in UP mode, cpu_icache_snoops_remote_store is redefined

I do not run in UP mode, so that is why I did not see it. I suggest a different version attached. How does that work for you?

-Steve

Index: cpu-features.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips/cpu-features.h,v retrieving revision 1.9

cpu-features.h +2 -2

diff -u -r1.9 cpu-features.h
@@ -87,13 +87,13 @@
  * that did the store so we can't optimize this into only doing the flush on
  * the local CPU.
  */
-#ifdef CONFIG_SMP
 #ifndef cpu_icache_snoops_remote_store
+#ifdef CONFIG_SMP
 #define cpu_icache_snoops_remote_store	(cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
-#endif
 #else
 #define cpu_icache_snoops_remote_store	1
 #endif
+#endif
 
 /*
  * Certain CPUs may throw bizarre exceptions if not the whole cacheline

Manish Lachwani

author

2004-12-16 03:50 UTC #4 lore raw

Quoted 31 lines · Steven J. Hill

Quoted 2 lines · Manish Lachwani
When did you last sync with CVS? There was a change introduced :
Literally 10 minutes ago and I did a fresh compile.
Quoted 2 lines
And if running Sibyte in UP mode, cpu_icache_snoops_remote_store is redefined
I do not run in UP mode, so that is why I did not see it. I suggest a different version attached. How does that work for you?
-Steve
------------------------------------------------------------------------
Index: cpu-features.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips/cpu-features.h,v retrieving revision 1.9
diff -u -r1.9 cpu-features.h
cpu-features.h +0 -1
@@ -87,13 +87,13 @@
 * that did the store so we can't optimize this into only doing the flush on
 * the local CPU.
 */
-#ifdef CONFIG_SMP
 #ifndef cpu_icache_snoops_remote_store

cpu-features.h line 99

Quoted 10 lines

cpu-features.h +2 -1

+#ifdef CONFIG_SMP
 #define cpu_icache_snoops_remote_store	(cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
-#endif
 #else
 #define cpu_icache_snoops_remote_store	1
 #endif
+#endif
 
 /*
 * Certain CPUs may throw bizarre exceptions if not the whole cacheline

Looks good to me

Thanks
Manish Lachwani

Manish Lachwani

author

2004-12-16 03:54 UTC #5 lore raw

In reply to Steven J. Hill

On a side note, I think this problem will appear on other arches as well when running in UP mode.

Thanks
Manish Lachwani

Quoted 41 lines · Steven J. Hill

Quoted 2 lines · Manish Lachwani
When did you last sync with CVS? There was a change introduced :
Literally 10 minutes ago and I did a fresh compile.
Quoted 2 lines
And if running Sibyte in UP mode, cpu_icache_snoops_remote_store is redefined
I do not run in UP mode, so that is why I did not see it. I suggest a different version attached. How does that work for you?
-Steve
------------------------------------------------------------------------
Index: cpu-features.h
===================================================================
RCS file: /home/cvs/linux/include/asm-mips/cpu-features.h,v retrieving revision 1.9
diff -u -r1.9 cpu-features.h
cpu-features.h +2 -2
@@ -87,13 +87,13 @@
 * that did the store so we can't optimize this into only doing the flush on
 * the local CPU.
 */
-#ifdef CONFIG_SMP
 #ifndef cpu_icache_snoops_remote_store
+#ifdef CONFIG_SMP
 #define cpu_icache_snoops_remote_store	(cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
-#endif
 #else
 #define cpu_icache_snoops_remote_store	1
 #endif
+#endif
 
 /*
 * Certain CPUs may throw bizarre exceptions if not the whole cacheline

Maciej W. Rozycki

2004-12-16 03:58 UTC #6 lore raw

In reply to Steven J. Hill

Quoted 2 lines · Steven J. Hill

I do not run in UP mode, so that is why I did not see it. I suggest a different version attached. How does that work for you?

This begs for indentation. ;-)

Maciej