2.6.x libata fixes
PATCH 1/1 2.6.x libata fixes
Please do a
bk pull bk://gkernel.bkbits.net/libata-2.6
This will update the following files:
drivers/scsi/ahci.c | 2 -- drivers/scsi/libata-scsi.c | 7 ++++++- drivers/scsi/sata_sil.c | 32 +++++++++++++++++++++++++++++++- 3 files changed, 37 insertions(+), 4 deletions(-)
through these ChangeSets:
<carlos.pardo:siliconimage.com>:
o sata_sil: Fix FIFO PCI Bus Arbitration
Brett Russ:
o libata: support descriptor sense in ctrl page
Jason Gaston:
o SATA AHCI correction Intel ICH7R
Jeff Garzik:
o [libata sata_sil] Don't presume PCI cache-line-size reg is > 0
drivers/scsi/ahci.c +0 -2
@@ -253,8 +253,6 @@ board_ahci }, /* ICH7 */ {PCI_VENDOR_ID_INTEL ,0x27c5 ,PCI_ANY_ID ,PCI_ANY_ID ,0 ,0 , board_ahci }, /* ICH7M */ - { PCI_VENDOR_ID_INTEL, 0x27c2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, - board_ahci }, /* ICH7R */ { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, board_ahci }, /* ICH7R */ { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
drivers/scsi/libata-scsi.c +6 -1
@@ -1038,7 +1038,12 @@static unsigned int ata_msense_ctl_mode (u8 **ptr_io,const u8 *last) { -const u8 page[] = {0xa ,0xa ,2 ,0 ,0 ,0 ,0 ,0 ,0xff ,0xff ,0 ,30 }; +const u8 page[] = {0xa ,0xa ,6 ,0 ,0 ,0 ,0 ,0 ,0xff ,0xff ,0 ,30 }; + +/* byte 2: set the descriptor format sense data bit (bit 2) +* since we need to support returning this format for SAT +* commands and any SCSI commands against a 48b LBA device. +*/ ata_msense_push (ptr_io, last, page,sizeof (page));return sizeof (page);
drivers/scsi/sata_sil.c +31 -1
@@ -38,12 +38,21 @@#include <linux/libata.h> #define DRV_NAME "sata_sil" -#define DRV_VERSION "0.8" +#define DRV_VERSION "0.9"enum { sil_3112 =0 , sil_3114 =1 , +SIL_FIFO_R0 =0x40 , +SIL_FIFO_W0 =0x41 , +SIL_FIFO_R1 =0x44 , +SIL_FIFO_W1 =0x45 , +SIL_FIFO_R2 =0x240 , +SIL_FIFO_W2 =0x241 , +SIL_FIFO_R3 =0x244 , +SIL_FIFO_W3 =0x245 , +SIL_SYSCFG =0x48 ,SIL_MASK_IDE0_INT = (1 <<22 ),SIL_MASK_IDE1_INT = (1 <<23 ),
@@ -199,6 +208,13 @@MODULE_DEVICE_TABLE (pci, sil_pci_tbl);MODULE_VERSION (DRV_VERSION ); +static unsigned char sil_get_device_cache_line (struct pci_dev *pdev) +{ +u8 cache_line =0 ; +pci_read_config_byte (pdev,PCI_CACHE_LINE_SIZE , &cache_line); +return cache_line; +} +static void sil_post_set_mode (struct ata_port *ap) {struct ata_host_set *host_set = ap->host_set;
@@ -341,6 +357,7 @@unsigned int i;int pci_dev_busy =0 ;u32 tmp, irq_mask; +u8 cls;if (!printed_version++) printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
@@ -404,6 +421,19 @@ probe_ent->port[i].scr_addr = base + sil_port[i].scr;ata_std_ports (&probe_ent->port[i]); } + +/* Initialize FIFO PCI bus arbitration */ + cls =sil_get_device_cache_line (pdev); +if (cls) { + cls >>=3 ; + cls++;/* cls = (line_size/8)+1 */ +writeb (cls, mmio_base +SIL_FIFO_R0 ); +writeb (cls, mmio_base +SIL_FIFO_W0 ); +writeb (cls, mmio_base +SIL_FIFO_R1 ); +writeb (cls, mmio_base +SIL_FIFO_W2 ); + }else + printk(KERN_WARNING DRV_NAME "(%s): cache line size not set. Driver may not function\n", +pci_name (pdev));if (ent->driver_data == sil_3114) { irq_mask =SIL_MASK_4PORT ;