FCC Ethernet PlatformDevice support for 82xx

diff -Nru a/arch/ppc/syslib/cpm2_common.c b/arch/ppc/syslib/cpm2_common.c
@@ -112,6 +112,62 @@
 		*bp |= CPM_BRG_DIV16;
 }
 
+void cpm2_cmd(uint cmd)
+{
+	cpmp->cp_cpcr = cmd | CPM_CR_FLG;
+	while(cpmp->cp_cpcr & CPM_CR_FLG)
+		cpu_relax();
+	
+}
+
+s_iop* cpm2_pin_read(enum ioports port)
+{	
+	s_iop* iop;
+	iop = (s_iop*)(&cpm2_immr->im_ioport);
+	return &iop[port];
+}
+
+void cpm2_pin_program(enum ioports port, int set, u32 par, u32 odr, u32 dir, u32 sor, u32 dat)
+{
+	s_iop *ioport = cpm2_pin_read(port);
+
+	pr_debug("Modified: iop[%d]: par %x odr %x dir %x sor %x dat %x\n",
+		par,odr,dir,sor,dat);
+	
+	if(set)
+	{
+		if(dir)
+			ioport->pdir |= dir;
+		if(par)
+			ioport->ppar  |= par;
+		if(par)
+			ioport->podr |= odr;
+		if(sor)
+			ioport->psor |= sor;
+		if(dat)
+			ioport->pdat |= dat;
+	} else {
+		if(dir)
+			ioport->pdir &= ~dir;
+		if(par)
+			ioport->ppar  &= ~par;
+		if(odr)
+			ioport->podr &= ~odr;
+		if(sor)
+			ioport->psor &= ~sor;
+		if(dat)
+			ioport->pdat &= ~dat;
+	}
+}
+
+void cpm2_cpmux_alter_fcr(u32 set, u32 clear)
+{
+	u32 tmpval = cpm2_immr->im_cpmux.cmx_fcr;
+	tmpval &= ~clear;
+	tmpval |= set;
+	cpm2_immr->im_cpmux.cmx_fcr = tmpval;
+}
+
 /*
  * dpalloc / dpfree bits.
  */

diff -Nru a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h
@@ -75,6 +75,11 @@
 #define CPM_CR_START_IDMA	((ushort)0x0009)
 #define CPM_CR_STOP_IDMA	((ushort)0x000b)
 
+#define CPM_MCN_HDLC		0x00
+#define CPM_MCN_ATM		0x0A
+#define CPM_MCN_ETHERNET	0x0C
+#define CPM_MCN_TRANSPARENT	0x0F
+
 #define mk_cr_cmd(PG, SBC, MCN, OP) \
 	((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
 

@@ -116,6 +121,7 @@
 extern void *cpm_dpram_addr(uint offset);
 extern void cpm_setbrg(uint brg, uint rate);
 extern void cpm2_fastbrg(uint brg, uint rate, int div16);
+extern void cpm2_cmd(uint cmd);
 
 /* Buffer descriptors used by many of the CPM protocols.
 */

@@ -1038,6 +1044,28 @@
 #define CMXSCR_TS4CS_CLK6  0x00000005   /* SCC4 Tx Clock Source is CLK6 */
 #define CMXSCR_TS4CS_CLK7  0x00000006   /* SCC4 Tx Clock Source is CLK7 */
 #define CMXSCR_TS4CS_CLK8  0x00000007   /* SCC4 Tx Clock Source is CLK8 */
+
+/* IOport stuff*/
+
+enum ioports{
+	PORTA,
+	PORTB,
+	PORTC,
+	PORTD,
+};
+
+typedef struct single_ioport{
+	u32	pdir;
+	u32	ppar;
+	u32	psor;
+	u32	podr;
+	u32	pdat;
+	u8	res1[12];
+}s_iop;	
+
+void cpm2_pin_program(enum ioports port, int set, u32 par, u32 odr, u32 dir, u32 sor, u32 dat);
+void cpm2_cpmux_alter_fcr(u32 set, u32 clear);
+s_iop* cpm2_pin_read(enum ioports port);
 
 #endif /* __CPM2__ */
 #endif /* __KERNEL__ */