ppc32: add Freescale MPC885ADS board support
PATCH 1/1 ppc32: add Freescale MPC885ADS board support
This patch adds the Freescale MPC885ADS board to 2.6.12-rc6. The supported devices are two SMC UARTs and 10Mbit ethernet on SCC3.
FEC is not supported as the "combined FCC/FEC ethernet driver" driver by Pantelis Antoniou (first posted to this list on May 9; I'll call it "fs_enet" for short) should replace the current FEC driver.
On MPC885ADS SCC ethernet PHY defaults to the full duplex mode upon reset. SCC is set to half duplex by default. This inconsistency is not handled by this patch for the following reasons:
- ethernet works anyway (the statistics should look terrible though)
- we are working on a patch to add SCC ehternet support to the fs_enet driver, and will revisit this full/half duplex issue when moving the board to the new ethernet driver and platform devices.
Signed-off-by Yuri Shpilevsky <[email protected]>
Signed-off-by Andrei Konovalov <[email protected]>
arch/ppc/8xx_io/enet.c +34 -8
@@ -714,16 +714,24 @@ static int __init scc_enet_init(void) immap->im_ioport.iop_pcdat &= ~PC_ENET_LBK ;/* Disable Loopback */ #endif /* PC_ENET_LBK */ -/* Configure port C pins to enable CLSN and RENA. +#ifdef PE_ENET_TCLK +/* Configure port E for TCLK and RCLK. */ - immap->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN |PC_ENET_RENA ); - immap->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN |PC_ENET_RENA ); - immap->im_ioport.iop_pcso |= (PC_ENET_CLSN |PC_ENET_RENA ); - + cp->cp_pepar |= (PE_ENET_TCLK |PE_ENET_RCLK ); + cp->cp_pedir &= ~(PE_ENET_TCLK |PE_ENET_RCLK ); + cp->cp_peso &= ~(PE_ENET_TCLK |PE_ENET_RCLK ); +#else /* Configure port A for TCLK and RCLK. */ immap->im_ioport.iop_papar |= (PA_ENET_TCLK |PA_ENET_RCLK ); immap->im_ioport.iop_padir &= ~(PA_ENET_TCLK |PA_ENET_RCLK ); +#endif + +/* Configure port C pins to enable CLSN and RENA. +*/ + immap->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN |PC_ENET_RENA ); + immap->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN |PC_ENET_RENA ); + immap->im_ioport.iop_pcso |= (PC_ENET_CLSN |PC_ENET_RENA );/* Configure Serial Interface clock routing. * First, clear all SCC bits to zero, then set the ones we want.
@@ -896,14 +904,18 @@ static int __init scc_enet_init(void)/* It is now OK to enable the Ethernet transmitter. * Unfortunately, there are board implementation differences here. */ -#if (!defined (PB_ENET_TENA ) && defined (PC_ENET_TENA )) +#if (!defined (PB_ENET_TENA ) && defined (PC_ENET_TENA ) && !defined (PE_ENET_TENA )) immap->im_ioport.iop_pcpar |=PC_ENET_TENA ; immap->im_ioport.iop_pcdir &= ~PC_ENET_TENA ; -#elif ( defined (PB_ENET_TENA ) && !defined (PC_ENET_TENA )) +#elif ( defined (PB_ENET_TENA ) && !defined (PC_ENET_TENA ) && !defined (PE_ENET_TENA )) cp->cp_pbpar |=PB_ENET_TENA ; cp->cp_pbdir |=PB_ENET_TENA ; +#elif ( !defined (PB_ENET_TENA ) && !defined (PC_ENET_TENA ) && defined (PE_ENET_TENA )) + cp->cp_pepar |=PE_ENET_TENA ; + cp->cp_pedir &= ~PE_ENET_TENA ; + cp->cp_peso |=PE_ENET_TENA ;#else -#error Configuration Error: define exactly ONE of PB_ENET_TENA, PC_ENET_TENA +#error Configuration Error: define exactly ONE of PB_ENET_TENA, PC_ENET_TENA, PE_ENET_TENA#endif #if defined(CONFIG_RPXLITE ) || defined(CONFIG_RPXCLASSIC )
@@ -956,6 +968,19 @@ static int __init scc_enet_init(void)return err; } +#ifdef CONFIG_MPC885ADS + +/* Deassert PHY reset and enable the PHY. +*/ + *((volatile uint *)BCSR4 ) |=BCSR4_ETH10_RST ; + *((volatile uint *)BCSR1 ) |=BCSR1_ETHEN ; + +/* On MPC885ADS SCC ethernet PHY defaults to the full duplex mode +* upon reset. SCC is set to half duplex by default. So this +* inconsistency should be better fixed by the software. +*/ +#endif +/* And last, enable the transmit and receive processing. */ sccp->scc_gsmrl |= (SCC_GSMRL_ENR |SCC_GSMRL_ENT );
@@ -969,3 +994,4 @@ static int __init scc_enet_init(void) }module_init (scc_enet_init); +
arch/ppc/configs/mpc885ads_defconfig +622 -0
622 lines not on this page · raw message
arch/ppc/Kconfig +8 -0
@@ -379,6 +379,14 @@ config BSEIP config FADS bool "FADS" +config MPC885ADS + bool "MPC885ADS" + help + Freescale Semiconductor MPC885 Application Development System (ADS). + Also known as DUET. + The MPC885ADS is meant to serve as a platform for s/w and h/w + development around the MPC885 processor family. + config TQM823L bool "TQM823L" help
arch/ppc/platforms/mpc885ads.h +92 -0
92 lines not on this page · raw message
arch/ppc/syslib/m8xx_setup.c +1 -1
@@ -369,7 +369,7 @@ m8xx_map_io(void)#if defined(CONFIG_HTDMSOUND ) || defined(CONFIG_RPXTOUCH ) || defined(CONFIG_FB_RPX )io_block_mapping (HIOX_CSR_ADDR ,HIOX_CSR_ADDR ,HIOX_CSR_SIZE , _PAGE_IO);#endif -#ifdef CONFIG_FADS +#if defined(CONFIG_FADS ) || defined(CONFIG_MPC885ADS )io_block_mapping (BCSR_ADDR ,BCSR_ADDR ,BCSR_SIZE , _PAGE_IO);#endif #ifdef CONFIG_PCI
drivers/serial/cpm_uart/cpm_uart_cpm1.c +17 -1
@@ -94,12 +94,28 @@ void smc1_lineif(struct uart_cpm_port *p ((immap_t *)IMAP_ADDR )->im_ioport.iop_paodr &= ~iobits; } +#ifdef CONFIG_MPC885ADS +/* Enable SMC1 transceivers */ + *((volatile uint *)BCSR1 ) &= ~BCSR1_RS232EN_1 ; +#endif + pinfo->brg =1 ; }void smc2_lineif (struct uart_cpm_port *pinfo) { -/* XXX SMC2: insert port configuration here */ +#ifdef CONFIG_MPC885ADS +volatile cpm8xx_t *cp = cpmp; + + cp->cp_pepar |=0x00000c00 ; + cp->cp_pedir &=0x00000c00 ; + cp->cp_peso &= ~0x00000400 ; + cp->cp_peso |=0x00000800 ; + +/* Enable SMC2 transceivers */ + *((volatile uint *)BCSR1 ) &= ~BCSR1_RS232EN_2 ; +#endif + pinfo->brg =2 ; }
include/asm-ppc/mpc8xx.h +4 -0
@@ -68,6 +68,10 @@#include <platforms/lantec.h> #endif +#if defined(CONFIG_MPC885ADS ) +#include <platforms/mpc885ads.h> +#endif +/* Currently, all 8xx boards that support a processor to PCI/ISA bridge * use the same memory map. */