ppc32: 8xx pq platform system descriptions

Added ppc_sys device and system definitions for PowerQUICC I devices.

Sincerely,
Vitaly

@@ -34,7 +34,8 @@ ifeq ($(CONFIG_40x),y)
 obj-$(CONFIG_PCI)		+= indirect_pci.o pci_auto.o ppc405_pci.o
 endif
 endif
-obj-$(CONFIG_8xx)		+= m8xx_setup.o ppc8xx_pic.o $(wdt-mpc8xx-y)
+obj-$(CONFIG_8xx)		+= m8xx_setup.o ppc8xx_pic.o $(wdt-mpc8xx-y) \
+				   ppc_sys.o mpc8xx_devices.o mpc8xx_sys.o
 ifeq ($(CONFIG_8xx),y)
 obj-$(CONFIG_PCI)		+= qspan_pci.o i8259.o
 endif

@@ -133,6 +133,16 @@ irq_canonicalize(int irq)
 #define	SIU_IRQ7	(14)
 #define	SIU_LEVEL7	(15)
 
+#define MPC8xx_INT_FEC1		SIU_LEVEL1
+#define MPC8xx_INT_FEC2		SIU_LEVEL3
+
+#define MPC8xx_INT_SCC1		(CPM_IRQ_OFFSET + CPMVEC_SCC1)
+#define MPC8xx_INT_SCC2		(CPM_IRQ_OFFSET + CPMVEC_SCC2)
+#define MPC8xx_INT_SCC3		(CPM_IRQ_OFFSET + CPMVEC_SCC3)
+#define MPC8xx_INT_SCC4		(CPM_IRQ_OFFSET + CPMVEC_SCC4)
+#define MPC8xx_INT_SMC1		(CPM_IRQ_OFFSET + CPMVEC_SMC1)
+#define MPC8xx_INT_SMC2		(CPM_IRQ_OFFSET + CPMVEC_SMC2)
+
 /* The internal interrupts we can configure as we see fit.
  * My personal preference is CPM at level 2, which puts it above the
  * MBX PCI/ISA/IDE interrupts.

@@ -101,6 +101,22 @@ extern unsigned char __res[];
 
 struct pt_regs;
 
+enum ppc_sys_devices {
+	MPC8xx_CPM_FEC1,
+	MPC8xx_CPM_FEC2,
+	MPC8xx_CPM_I2C,
+	MPC8xx_CPM_SCC1,
+	MPC8xx_CPM_SCC2,
+	MPC8xx_CPM_SCC3,
+	MPC8xx_CPM_SCC4,
+	MPC8xx_CPM_SPI,
+	MPC8xx_CPM_MCC1,
+	MPC8xx_CPM_MCC2,
+	MPC8xx_CPM_SMC1,
+	MPC8xx_CPM_SMC2,
+	MPC8xx_CPM_USB,
+};
+
 #endif /* !__ASSEMBLY__ */
 #endif /* CONFIG_8xx */
 #endif /* __CONFIG_8xx_DEFS */

@@ -25,6 +25,8 @@
 #include <asm/mpc83xx.h>
 #elif defined(CONFIG_85xx)
 #include <asm/mpc85xx.h>
+#elif defined(CONFIG_8xx)
+#include <asm/mpc8xx.h>
 #elif defined(CONFIG_PPC_MPC52xx)
 #include <asm/mpc52xx.h>
 #elif defined(CONFIG_MPC10X_BRIDGE)

+/* access ports */
+#define setbits32(_addr, _v) out_be32(&(_addr), in_be32(&(_addr)) | (_v)) +#define clrbits32(_addr, _v) out_be32(&(_addr), in_be32(&(_addr)) & ~(_v)) +
+#define setbits16(_addr, _v) out_be16(&(_addr), in_be16(&(_addr)) | (_v)) +#define clrbits16(_addr, _v) out_be16(&(_addr), in_be16(&(_addr)) & ~(_v)) +

Needs to go.

+#define MPC8xx_INT_FEC1 SIU_LEVEL1
+#define MPC8xx_INT_FEC2 SIU_LEVEL3
+

+#define MPC8xx_INT_SCC1        (CPM_IRQ_OFFSET + CPMVEC_SCC1)
+#define MPC8xx_INT_SCC2        (CPM_IRQ_OFFSET + CPMVEC_SCC2)
+#define MPC8xx_INT_SCC3        (CPM_IRQ_OFFSET + CPMVEC_SCC3)
+#define MPC8xx_INT_SCC4        (CPM_IRQ_OFFSET + CPMVEC_SCC4)
+#define MPC8xx_INT_SMC1        (CPM_IRQ_OFFSET + CPMVEC_SMC1)
+#define MPC8xx_INT_SMC2        (CPM_IRQ_OFFSET + CPMVEC_SMC2)

Marcelo, we should look at what effect moving CPMVEC_* out of commproc.h into irq.h and cleaning things up has on the world.

- kumar

Vitaly, Kumar,

Have a few questions:

- Do you have any plans on actually using device model information by drivers (as was done in the mpc8xxx/gianfar) on m8xx? Its not very clear to me what are the the practical advantages of that?

- I don't know whether its possible to retrieve 8xx CPUID information (if there is any). Can't find anything in the manual.

It may be nice if we can do that. We have to be careful about sharing CPM drivers between the 8xx and CPM2 (82xx/83xx/85xx). It's tempting, but I still believe the differences outweigh the similarities. The overhead of trying to use common drivers would be quite costly on the 8xx.

We really can't. The PVR only represents the processor core information, and for the most part they are all the same. It used to be we could use the CPM microcode version, but these are now nearly the same. Some attempts have been made to probe for CPM peripherals that don't exist, but it seems on some parts the CPM is the same and the signals just aren't bonded out of the chip.

For the most part, the person doing the kernel configuration just simply has to know what part they are using. You have to select the proper peripherals, and you need the board support for the IO pin routing. In an embedded environment where resources still need to be carefully managed, I don't think this is unrealistic.

Thanks.

	-- Dan