Cleanup of arm920t/start.s

U-Boot-Users Paolo Broggini 2 participants 3 messages Oct 13, 2005 Arm/actions semi architecture

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Paolo Broggini

author

2005-10-13 08:31 UTC #0 lore raw

Dear all,
I would like to cleanup the file cpu/arm920t/start.S by moving the s3c24x0 specific code to their respective boards lowlevel_init.S
Are there any particular reasons why this code should stay in start.S ?
If I submit a patch, the smdk24x0 boards maintainers (or anybody else) can test it ? (I don't have the HW)

Best regards
-P.Broggini

Wolfgang Denk

2005-10-13 08:46 UTC #1 lore raw

Quoted 4 lines · In message <[email protected]> you wrote:

I would like to cleanup the file cpu/arm920t/start.S by moving the s3c24x0 specific code to their respective boards lowlevel_init.S
Are there any particular reasons why this code should stay in start.S ?

Never change a running system without need?

Quoted 2 lines

If I submit a patch, the smdk24x0 boards maintainers (or anybody else) can test it ? (I don't have the HW)

I can (and will) test SMDK2400.

Best regards,

Wolfgang Denk

Signature · 5 lines

Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
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Paolo Broggini

author

2005-10-13 12:38 UTC #2 lore raw

Wolfgang Denk ha scritto:

Quoted 5 lines

Quoted 1 line
Are there any particular reasons why this code should stay in start.S ?
Never change a running system without need?

Yeah, though not technical is an important one indeed ;-)
But since a SoC structure has been created I thought it was nice to have all the independent files cleaned. Just give it a try! Anyway I'll fully understand if you prefer not to touch a running system.

Best regards
-P.Broggini

Signed-off-by Paolo Broggini <[email protected]>

CHANGELOG:
Cleanup of cpu/arm920t/start.S, S3C24x0 specific code moved into boards depended lowlevel_init.s Affected boards: sdmk2400, sdmk2410, vcma9, trab Patch by Paolo Broggini, 13 Oct 2005

board/mpl/vcma9/lowlevel_init.S +28 -0

@@ -34,6 +34,10 @@
 
  /* some parameters for the board */
 
+#define pWTCON		0x53000000
+#define INTMSK		0x4A000008	/* Interupt-Controller base addresses */
+#define INTSUBMSK	0x4A00001C
+#define CLKDIVN	0x4C000014	/* clock divisor register */
  #define BWSCON		0x48000000
  #define PLD_BASE	0x2C000000
  #define SDRAM_REG	0x2C000106

@@ -132,6 +136,30 @@ _TEXT_BASE:
 
  .globl lowlevel_init
  lowlevel_init:
+
+	/*
+	 * Watchdog disable
+	 */
+	ldr     r0, =pWTCON
+	mov     r1, #0x0
+	str     r1, [r0]
+
+	/*
+	 * mask all IRQs by setting all bits in the INTMR - default
+	 */
+	mov	r1, #0xffffffff
+	ldr	r0, =INTMSK
+	str	r1, [r0]
+	ldr	r1, =0x3ff
+	ldr	r0, =INTSUBMSK
+	str	r1, [r0]
+
+	/* FCLK:HCLK:PCLK = 1:2:4 */
+	/* default FCLK is 120 MHz ! */
+	ldr	r0, =CLKDIVN
+	mov	r1, #3
+	str	r1, [r0]
+
  	/* memory control configuration */
  	/* make r0 relative the current location so that it */
  	/* reads SMRDATA out of FLASH rather than memory ! */

board/smdk2400/lowlevel_init.S +27 -2

@@ -44,9 +44,13 @@
   *
   */
 
+#define pWTCON		0x15300000
+#define INTMSK		0x14400008	/* Interupt-Controller base addresses */
+#define CLKDIVN	0x14800014	/* clock divisor register */
+
  /* memory controller */
-#define BWSCON 0x14000000
-#define BANKCON3 0x14000010	/* for cs8900, ethernet */
+#define BWSCON		0x14000000
+#define BANKCON3 	0x14000010	/* for cs8900, ethernet */
 
  /* Bank0 */
  #define B0_Tacs	0x0	/* 0 clk */

@@ -127,6 +131,27 @@ _TEXT_BASE:
 
  .globl lowlevel_init
  lowlevel_init:
+
+	/*
+	 * Watchdog disable
+	 */
+	ldr     r0, =pWTCON
+	mov     r1, #0x0
+	str     r1, [r0]
+
+	/*
+	 * mask all IRQs by setting all bits in the INTMR - default
+	 */
+	mov	r1, #0xffffffff
+	ldr	r0, =INTMSK
+	str	r1, [r0]
+
+	/* FCLK:HCLK:PCLK = 1:2:4 */
+	/* default FCLK is 120 MHz ! */
+	ldr	r0, =CLKDIVN
+	mov	r1, #3
+	str	r1, [r0]
+
  	/* memory control configuration */
  	/* make r0 relative the current location so that it */
  	/* reads SMRDATA out of FLASH rather than memory ! */

board/smdk2410/lowlevel_init.S +29 -1

@@ -42,7 +42,11 @@
   *
   */
 
-#define BWSCON	0x48000000
+#define pWTCON		0x53000000
+#define INTMSK		0x4A000008	/* Interupt-Controller base addresses */
+#define INTSUBMSK	0x4A00001C
+#define CLKDIVN	0x4C000014	/* clock divisor register */
+#define BWSCON		0x48000000
 
  /* BWSCON */
  #define DW8		 	(0x0)

@@ -131,6 +135,30 @@ _TEXT_BASE:
 
  .globl lowlevel_init
  lowlevel_init:
+
+	/*
+	 * Watchdog disable
+	 */
+	ldr     r0, =pWTCON
+	mov     r1, #0x0
+	str     r1, [r0]
+
+	/*
+	 * mask all IRQs by setting all bits in the INTMR - default
+	 */
+	mov	r1, #0xffffffff
+	ldr	r0, =INTMSK
+	str	r1, [r0]
+	ldr	r1, =0x3ff
+	ldr	r0, =INTSUBMSK
+	str	r1, [r0]
+
+	/* FCLK:HCLK:PCLK = 1:2:4 */
+	/* default FCLK is 120 MHz ! */
+	ldr	r0, =CLKDIVN
+	mov	r1, #3
+	str	r1, [r0]
+
  	/* memory control configuration */
  	/* make r0 relative the current location so that it */
  	/* reads SMRDATA out of FLASH rather than memory ! */

board/trab/lowlevel_init.S +25 -0

@@ -44,6 +44,10 @@
   *
   */
 
+#define pWTCON		0x15300000
+#define INTMSK		0x14400008	/* Interupt-Controller base addresses */
+#define CLKDIVN	0x14800014	/* clock divisor register */
+
  /* memory controller */
  #define BWSCON 0x14000000

@@ -142,6 +146,27 @@ _TEXT_BASE:
 
  .globl lowlevel_init
  lowlevel_init:
+
+	/*
+	 * Watchdog disable
+	 */
+	ldr     r0, =pWTCON
+	mov     r1, #0x0
+	str     r1, [r0]
+
+	/*
+	 * mask all IRQs by setting all bits in the INTMR - default
+	 */
+	mov	r1, #0xffffffff
+	ldr	r0, =INTMSK
+	str	r1, [r0]
+
+	/* FCLK:HCLK:PCLK = 1:2:4 */
+	/* default FCLK is 120 MHz ! */
+	ldr	r0, =CLKDIVN
+	mov	r1, #3
+	str	r1, [r0]
+
  	/* memory control configuration */
  	/* make r0 relative the current location so that it */
  	/* reads SMRDATA out of FLASH rather than memory ! */

cpu/arm920t/start.S +2 ~~-38~~

@@ -1,8 +1,8 @@
  /*
   *  armboot - Startup Code for ARM920 CPU-core
   *
- *  Copyright (c) 2001	Marius Grger <[email protected]>
- *  Copyright (c) 2002	Alex Zpke <[email protected]>
+ *  Copyright (c) 2001	Marius Grger <[email protected]>
+ *  Copyright (c) 2002	Alex Zpke <[email protected]>
   *  Copyright (c) 2002	Gary Jennejohn <[email protected]>
   *
   * See file CREDITS for list of people who contributed to this

@@ -116,42 +116,6 @@ reset:
  	orr	r0,r0,#0xd3
  	msr	cpsr,r0
 
-/* turn off the watchdog */
-#if defined(CONFIG_S3C2400)
-# define pWTCON		0x15300000
-# define INTMSK		0x14400008	/* Interupt-Controller base addresses */
-# define CLKDIVN	0x14800014	/* clock divisor register */
-#elif defined(CONFIG_S3C2410)
-# define pWTCON		0x53000000
-# define INTMSK		0x4A000008	/* Interupt-Controller base addresses */
-# define INTSUBMSK	0x4A00001C
-# define CLKDIVN	0x4C000014	/* clock divisor register */
-#endif
-
-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
-	ldr     r0, =pWTCON
-	mov     r1, #0x0
-	str     r1, [r0]
-
-	/*
-	 * mask all IRQs by setting all bits in the INTMR - default
-	 */
-	mov	r1, #0xffffffff
-	ldr	r0, =INTMSK
-	str	r1, [r0]
-# if defined(CONFIG_S3C2410)
-	ldr	r1, =0x3ff
-	ldr	r0, =INTSUBMSK
-	str	r1, [r0]
-# endif
-
-	/* FCLK:HCLK:PCLK = 1:2:4 */
-	/* default FCLK is 120 MHz ! */
-	ldr	r0, =CLKDIVN
-	mov	r1, #3
-	str	r1, [r0]
-#endif	/* CONFIG_S3C2400 || CONFIG_S3C2410 */
-
  	/*
  	 * we do sys-critical inits only at reboot,
  	 * not when booting from ram!