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PNX8550 NAND flash driver]

PATCH New Vladimir A. Barinov 1 participant 1 message Dec 20, 2005

Subsystems (3)
Memory technology devices (MTD) MIPS NAND flash
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Vladimir A. Barinov

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PATCH 1/1 PNX8550 NAND flash driver]

Hi,

Quoted 4 lines · Vladimir A. Barinov

Hi All,

Attached patch is NAND flash driver for PNX8550 based platforms. Any comments and suggestions are highly appreciated.

Sorry, but this patch is not complete. It's needed to add include/../nand.h file.

Attachment is the recasted variant (removing "volatile u16 *" usage, "prink" usage changes and some cosmetic changes) with nand.h part.

Vladimir

Signed-off-by [email protected]
 drivers/mtd/nand/Kconfig             |    6 
 drivers/mtd/nand/Makefile            |    1 
 drivers/mtd/nand/pnx8550.c           |  694 +++++++++++++++++++++++++++++++++++
 include/asm-mips/mach-pnx8550/nand.h |   22 +
 4 files changed, 721 insertions(+), 2 deletions(-)
drivers/mtd/nand/Kconfig +6 -0
Index: linux-2.6.15_0/drivers/mtd/nand/Kconfig
===================================================================
@@ -90,6 +90,12 @@ config MTD_NAND_S3C2410
 	  No board specfic support is done by this driver, each board
 	  must advertise a platform_device for the driver to attach.
 
+config MTD_NAND_PNX8550
+	tristate "NAND Flash support for PNX8550"
+	depends on PNX8550 && MTD_NAND
+	help
+	  This enables the NAND flash controller on the PNX8550.
+
 config MTD_NAND_S3C2410_DEBUG
 	bool "S3C2410 NAND driver debug"
 	depends on MTD_NAND_S3C2410
drivers/mtd/nand/pnx8550.c new file +694 -0

694 lines not on this page · raw message

drivers/mtd/nand/Makefile +1 -0
Index: linux-2.6.15_0/drivers/mtd/nand/Makefile
===================================================================
@@ -18,5 +18,6 @@ obj-$(CONFIG_MTD_NAND_H1900)		+= h1910.o
 obj-$(CONFIG_MTD_NAND_RTC_FROM4)	+= rtc_from4.o
 obj-$(CONFIG_MTD_NAND_SHARPSL)		+= sharpsl.o
 obj-$(CONFIG_MTD_NAND_NANDSIM)		+= nandsim.o
+obj-$(CONFIG_MTD_NAND_PNX8550)		+= pnx8550.o
 
 nand-objs = nand_base.o nand_bbt.o
include/asm-mips/mach-pnx8550/nand.h +20 -2
Index: linux-2.6.15_0/include/asm-mips/mach-pnx8550/nand.h
===================================================================
@@ -4,10 +4,14 @@
 #define PNX8550_NAND_BASE_ADDR   0x10000000
 #define PNX8550_PCIXIO_BASE	 0xBBE40000
 
+#define PNX8550_BASE10_ADDR      *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x050)
+#define PNX8550_BASE14_ADDR      *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x054)
+#define PNX8550_BASE18_ADDR      *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x058)
 #define PNX8550_DMA_EXT_ADDR     *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x800)
 #define PNX8550_DMA_INT_ADDR     *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x804)
 #define PNX8550_DMA_TRANS_SIZE   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x808)
 #define PNX8550_DMA_CTRL         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x80c)
+#define PNX8550_XIO_CTRL         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x810)
 #define PNX8550_XIO_SEL0         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x814)
 #define PNX8550_GPXIO_ADDR       *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x820)
 #define PNX8550_GPXIO_WR         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x824)

@@ -21,6 +25,8 @@
 #define PNX8550_DMA_INT_ENABLE   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd4)
 #define PNX8550_DMA_INT_CLEAR    *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd8)
 
+#define PNX8550_XIO_CTRL_XIO_ACK     0x00000002
+
 #define PNX8550_XIO_SEL0_EN_16BIT    0x00800000
 #define PNX8550_XIO_SEL0_USE_ACK     0x00400000
 #define PNX8550_XIO_SEL0_REN_HIGH    0x00100000

@@ -39,6 +45,9 @@
 #define PNX8550_XIO_SEL0_SIZE_64MB   0x00000006
 #define PNX8550_XIO_SEL0_ENAB        0x00000001
 
+#define PNX8550_XIO_SEL0_OFFSET_SHIFT 5
+#define PNX8550_XIO_SEL0_OFFSET_MASK  (0xf << PNX8550_XIO_SEL0_OFFSET_SHIFT)
+
 #define PNX8550_SEL0_DEFAULT ((PNX8550_XIO_SEL0_EN_16BIT)  | \
                               (PNX8550_XIO_SEL0_REN_HIGH*0)| \
 	                      (PNX8550_XIO_SEL0_REN_LOW*2) | \

@@ -59,11 +68,15 @@
 
 #define PNX8550_XIO_FLASH_64MB       0x00200000
 #define PNX8550_XIO_FLASH_INC_DATA   0x00100000
-#define PNX8550_XIO_FLASH_CMD_PH     0x000C0000
+#define PNX8550_XIO_FLASH_CMD_PH_SHIFT 18
+#define PNX8550_XIO_FLASH_CMD_PH_MASK  (3 << PNX8550_XIO_FLASH_CMD_PH_SHIFT)
+#define PNX8550_XIO_FLASH_CMD_PH(_x)   (((_x) << PNX8550_XIO_FLASH_CMD_PH_SHIFT) & PNX8550_XIO_FLASH_CMD_PH_MASK)
+#define PNX8550_XIO_FLASH_ADR_PH_SHIFT 16
+#define PNX8550_XIO_FLASH_ADR_PH_MASK  (3 << PNX8550_XIO_FLASH_ADR_PH_SHIFT)
+#define PNX8550_XIO_FLASH_ADR_PH(_x)   (((_x) << PNX8550_XIO_FLASH_ADR_PH_SHIFT) & PNX8550_XIO_FLASH_ADR_PH_MASK)
 #define PNX8550_XIO_FLASH_CMD_PH2    0x00080000
 #define PNX8550_XIO_FLASH_CMD_PH1    0x00040000
 #define PNX8550_XIO_FLASH_CMD_PH0    0x00000000
-#define PNX8550_XIO_FLASH_ADR_PH     0x00030000
 #define PNX8550_XIO_FLASH_ADR_PH3    0x00030000
 #define PNX8550_XIO_FLASH_ADR_PH2    0x00020000
 #define PNX8550_XIO_FLASH_ADR_PH1    0x00010000

@@ -118,4 +131,9 @@
 #define PNX8550_DMA_INT_CLR_M_ABORT	(1<<2)
 #define PNX8550_DMA_INT_CLR_T_ABORT	(1<<1)
 
+#define PNX8550_DMA_INT_ACK          0x00004000
+#define PNX8550_DMA_INT_COMPL        0x00001000
+#define PNX8550_DMA_INT_NONSUP       0x00000200
+#define PNX8550_DMA_INT_ABORT        0x00000004
+
 #endif