OMAP2+: clock: add clockfw autoidle for iclks, OMAP2xxx

PATCH New Paul Walmsley 3 participants 20 messages Feb 16, 2011 – Mar 8, 2011

Subsystems (5)

Arm (32-bit) Arm sub-architectures OMAP2+ support OMAP power management support +1 more subsystems

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Paul Walmsley

author maintainer

2011-02-16 06:52 UTC #0 lore raw

cover OMAP2+: clock: add clockfw autoidle for iclks, OMAP2xxx

Hello,

This patch series adds clock framework-controlled autoidle support for the OMAP2xxx DPLL, APLLs, and OMAP2/3 interface clocks. The old direct register writes in the PM code to enable clock autoidle have been removed.

This series also ensures that all clock autoidle is disabled during boot and only re-enabled if CONFIG_PM is enabled.

The series applies on the 'clk_autoidle_a_2.6.39' branch of
git://git.pwsan.com/linux-2.6.

Boot-tested on N800, and dynamic idle-tested on OMAP3430 Beagleboard. Compile-tested with omap1_defconfig, omap2plus_defconfig, a 5912 OSK-only config, an N8x0-only config, an OMAP3-only config, and an OMAP4-only config.

- Paul

---

clk_autoidle_b_2.6.39
text data bss dec hex filename
5530703 330544 5594520 11455767 aecd17 vmlinux.omap2plus_defconfig.orig
5531167 330544 5594520 11456231 aecee7 vmlinux.omap2plus_defconfig.patched

Paul Walmsley (11):
OMAP2+: clock: disable autoidle on all clocks during clock init
OMAP2: clock: add DPLL autoidle support
OMAP2xxx: clock: add clockfw autoidle support for APLLs
OMAP2+: clock: comment that osc_ck/osc_sys_ck should use clockfw autoidle control OMAP2+: clock: add interface clock type code with autoidle support
OMAP2420: clock: add sdrc_ick
OMAP2420: clock: use autoidle clkops for all autoidle-controllable interface clocks OMAP2430/3xxx: clock: add modem clock autoidle support
OMAP2430: clock: use autoidle clkops for all autoidle-controllable interface clocks
OMAP3: clock: use autoidle clkops for all autoidle-controllable interface clocks OMAP2/3: PM: remove manual CM_AUTOIDLE bit setting in mach-omap2/pm*xx.c

 arch/arm/mach-omap2/Makefile          |    7 +
 arch/arm/mach-omap2/clkt2xxx_apll.c   |   24 +++++
 arch/arm/mach-omap2/clkt2xxx_dpll.c   |   63 +++++++++++++
 arch/arm/mach-omap2/clkt2xxx_osc.c    |   14 +++
 arch/arm/mach-omap2/clkt_iclk.c       |   82 +++++++++++++++++
 arch/arm/mach-omap2/clock.h           |   11 ++
 arch/arm/mach-omap2/clock2420_data.c  |  130 +++++++++++++++++-----------
 arch/arm/mach-omap2/clock2430_data.c  |  130 ++++++++++++++++------------
 arch/arm/mach-omap2/clock34xx.c       |   29 ++++++
 arch/arm/mach-omap2/clock34xx.h       |    5 +
 arch/arm/mach-omap2/clock3517.c       |    4 +
 arch/arm/mach-omap2/clock3xxx.c       |    3 -
 arch/arm/mach-omap2/clock3xxx_data.c  |  155 +++++++++++++++++----------------
 arch/arm/mach-omap2/clock44xx_data.c  |    3 +
 arch/arm/mach-omap2/cm-regbits-24xx.h |    3 +
 arch/arm/mach-omap2/cm2xxx_3xxx.c     |   69 +++++++++++++++
 arch/arm/mach-omap2/cm2xxx_3xxx.h     |    8 ++
 arch/arm/mach-omap2/pm24xx.c          |   69 +--------------
 arch/arm/mach-omap2/pm34xx.c          |  105 ----------------------
 19 files changed, 557 insertions(+), 357 deletions(-)
 create mode 100644 arch/arm/mach-omap2/clkt2xxx_dpll.c
 create mode 100644 arch/arm/mach-omap2/clkt_iclk.c

Paul Walmsley

author maintainer

2011-02-16 06:52 UTC #1 lore raw

PATCH 1/11 OMAP2+: clock: disable autoidle on all clocks during clock init

Disable autoidle on all clocks during clock framework initialization. (If CONFIG_PM is set, autoidle is re-enabled for all clocks later in the boot process.)

The principle behind this patch, and some similar patches, is that the kernel should start with all power management features disabled. Later in the boot process, the PM code, if compiled in with CONFIG_PM, enables or re-enables power management features.

Signed-off-by Paul Walmsley <[email protected]>

---
 arch/arm/mach-omap2/clock2420_data.c |    3 +++
 arch/arm/mach-omap2/clock2430_data.c |    3 +++
 arch/arm/mach-omap2/clock3xxx.c      |    3 ---
 arch/arm/mach-omap2/clock3xxx_data.c |    6 +++++-
 arch/arm/mach-omap2/clock44xx_data.c |    3 +++
 5 files changed, 14 insertions(+), 4 deletions(-)

arch/arm/mach-omap2/clock2420_data.c +3 -0

index 0a992bc..ee73e14 100644
@@ -1913,6 +1913,9 @@ int __init omap2420_clk_init(void)
 		omap2_init_clk_clkdm(c->lk.clk);
 	}
 
+	/* Disable autoidle on all clocks; let the PM code enable it later */
+	omap_clk_disable_autoidle_all();
+
 	/* Check the MPU rate set by bootloader */
 	clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
 	for (prcm = rate_table; prcm->mpu_speed; prcm++) {

arch/arm/mach-omap2/clock2430_data.c +3 -0

index c047dcd..a1298e5 100644
@@ -2028,6 +2028,9 @@ int __init omap2430_clk_init(void)
 		omap2_init_clk_clkdm(c->lk.clk);
 	}
 
+	/* Disable autoidle on all clocks; let the PM code enable it later */
+	omap_clk_disable_autoidle_all();
+
 	/* Check the MPU rate set by bootloader */
 	clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
 	for (prcm = rate_table; prcm->mpu_speed; prcm++) {

arch/arm/mach-omap2/clock3xxx.c +0 -3

index e9f66b6..952c3e0 100644
@@ -65,9 +65,6 @@ void __init omap3_clk_lock_dpll5(void)
 	clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
 	clk_enable(dpll5_clk);
 
-	/* Enable autoidle to allow it to enter low power bypass */
-	omap3_dpll_allow_idle(dpll5_clk);
-
 	/* Program dpll5_m2_clk divider for no division */
 	dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
 	clk_enable(dpll5_m2_clk);

arch/arm/mach-omap2/clock3xxx_data.c +5 -1

index 7cf89f8..0021559 100644
@@ -3535,6 +3535,9 @@ int __init omap3xxx_clk_init(void)
 			omap2_init_clk_clkdm(c->lk.clk);
 		}
 
+	/* Disable autoidle on all clocks; let the PM code enable it later */
+	omap_clk_disable_autoidle_all();
+
 	recalculate_root_clocks();
 
 	pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",

@@ -3548,7 +3551,8 @@ int __init omap3xxx_clk_init(void)
 	clk_enable_init_clocks();
 
 	/*
-	 * Lock DPLL5 and put it in autoidle.
+	 * Lock DPLL5 -- here only until other device init code can
+	 * handle this
 	 */
 	if (omap_rev() >= OMAP3430_REV_ES2_0)
 		omap3_clk_lock_dpll5();

arch/arm/mach-omap2/clock44xx_data.c +3 -0

index dcbe105..2795342 100644
@@ -3309,6 +3309,9 @@ int __init omap4xxx_clk_init(void)
 			omap2_init_clk_clkdm(c->lk.clk);
 		}
 
+	/* Disable autoidle on all clocks; let the PM code enable it later */
+	omap_clk_disable_autoidle_all();
+
 	recalculate_root_clocks();
 
 	/*

Paul Walmsley

author maintainer

2011-02-16 06:52 UTC #2 lore raw

PATCH 2/11 OMAP2: clock: add DPLL autoidle support

In reply to Paul Walmsley

Add the necessary code and data to allow the clock framework to enable and disable the OMAP2 DPLL autoidle state. This is so the direct register access can be moved out of the mach-omap2/pm24xx.c code, and other code that needs to control this (e.g., CPUIdle) can do so via an API. As part of this patch, remove the pm24xx.c code that formerly wrote directly to the autoidle bits.

Signed-off-by Paul Walmsley <[email protected]>

Cc Kevin Hilman <[email protected]>

---
 arch/arm/mach-omap2/Makefile         |    3 +-
 arch/arm/mach-omap2/clkt2xxx_dpll.c  |   63 ++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/clock.h          |    1 +
 arch/arm/mach-omap2/clock2420_data.c |    2 +
 arch/arm/mach-omap2/clock2430_data.c |    2 +
 arch/arm/mach-omap2/cm2xxx_3xxx.c    |   27 +++++++++++++++
 arch/arm/mach-omap2/cm2xxx_3xxx.h    |    3 ++
 arch/arm/mach-omap2/pm24xx.c         |   12 ++++--
 8 files changed, 105 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/mach-omap2/clkt2xxx_dpll.c

arch/arm/mach-omap2/Makefile +2 -1

index 3a798ef..41cb404 100644
@@ -112,7 +112,8 @@ obj-$(CONFIG_ARCH_OMAP2)		+= $(clock-common) clock2xxx.o \
 					   clkt2xxx_sys.o \
 					   clkt2xxx_dpllcore.o \
 					   clkt2xxx_virt_prcm_set.o \
-					   clkt2xxx_apll.o clkt2xxx_osc.o
+					   clkt2xxx_apll.o clkt2xxx_osc.o \
+					   clkt2xxx_dpll.o
 obj-$(CONFIG_ARCH_OMAP2420)		+= clock2420_data.o
 obj-$(CONFIG_ARCH_OMAP2430)		+= clock2430.o clock2430_data.o
 obj-$(CONFIG_ARCH_OMAP3)		+= $(clock-common) clock3xxx.o \

arch/arm/mach-omap2/clkt2xxx_dpll.c new file +63 -0

63 lines not on this page · raw message

arch/arm/mach-omap2/clock.h +1 -0

index 0725a6a..9972d89 100644
@@ -148,6 +148,7 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
 #define omap2_clk_exit_cpufreq_table	0
 #endif
 
+extern const struct clkops clkops_omap2xxx_dpll_ops;
 extern const struct clkops clkops_omap3_noncore_dpll_ops;
 extern const struct clkops clkops_omap3_core_dpll_ops;
 extern const struct clkops clkops_omap4_dpllmx_ops;

arch/arm/mach-omap2/clock2420_data.c +1 -1

index ee73e14..30fbcbd 100644
@@ -125,7 +125,7 @@ static struct dpll_data dpll_dd = {
  */
 static struct clk dpll_ck = {
 	.name		= "dpll_ck",
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap2xxx_dpll_ops,
 	.parent		= &sys_ck,		/* Can be func_32k also */
 	.dpll_data	= &dpll_dd,
 	.clkdm_name	= "wkup_clkdm",

arch/arm/mach-omap2/clock2430_data.c +1 -1

index a1298e5..1ff150a 100644
@@ -125,7 +125,7 @@ static struct dpll_data dpll_dd = {
  */
 static struct clk dpll_ck = {
 	.name		= "dpll_ck",
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap2xxx_dpll_ops,
 	.parent		= &sys_ck,		/* Can be func_32k also */
 	.dpll_data	= &dpll_dd,
 	.clkdm_name	= "wkup_clkdm",

arch/arm/mach-omap2/cm2xxx_3xxx.c +27 -0

index 96954aa..6b0c7c8 100644
@@ -25,6 +25,10 @@
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
 
+/* CM_AUTOIDLE_PLL.AUTO_* bit values */
+#define DPLL_AUTOIDLE_DISABLE				0x0
+#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP		0x3
+
 static const u8 cm_idlest_offs[] = {
 	CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
 };

@@ -125,6 +129,29 @@ void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
 	_write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
 }
 
+/*
+ * DPLL autoidle control
+ */
+
+static void _omap2xxx_set_dpll_autoidle(u8 m)
+{
+	u32 v;
+
+	v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+	v &= ~OMAP24XX_AUTO_DPLL_MASK;
+	v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
+	omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
+}
+
+void omap2xxx_cm_set_dpll_disable_autoidle(void)
+{
+	_omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
+}
+
+void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
+{
+	_omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
+}
 
 /*
  *

arch/arm/mach-omap2/cm2xxx_3xxx.h +3 -0

index 5e9ea5b..5f4df1c 100644
@@ -122,6 +122,9 @@ extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
 extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
 extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
 
+extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
+extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
+
 #endif
 
 /* CM register bits shared between 24XX and 3430 */

arch/arm/mach-omap2/pm24xx.c +7 -5

index 97feb3a..23b4607 100644
@@ -378,6 +378,7 @@ static void __init prcm_setup_regs(void)
 {
 	int i, num_mem_banks;
 	struct powerdomain *pwrdm;
+	u32 v;
 
 	/* Enable autoidle */
 	omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,

@@ -468,11 +469,12 @@ static void __init prcm_setup_regs(void)
 	omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
 			       CM_AUTOIDLE);
 
-	/* Put DPLL and both APLLs into autoidle mode */
-	omap2_cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
-			       (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
-			       (0x03 << OMAP24XX_AUTO_54M_SHIFT),
-			       PLL_MOD, CM_AUTOIDLE);
+	/* Put both APLLs into autoidle mode */
+	v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+	v &= ~(OMAP24XX_AUTO_96M_MASK | OMAP24XX_AUTO_54M_SHIFT);
+	v |= (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
+		(0x03 << OMAP24XX_AUTO_54M_SHIFT);
+	omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
 
 	omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
 			       OMAP24XX_AUTO_WDT1_MASK |

Paul Walmsley

author maintainer

2011-02-16 06:52 UTC #3 lore raw

PATCH 3/11 OMAP2xxx: clock: add clockfw autoidle support for APLLs

In reply to Paul Walmsley

OMAP2xxx devices have two on-chip APLLs. These APLLs can automatically enter idle when not in use. Connect the APLL autoidle code to the clock code, so that the clock framework can handle this process. As part of this patch, remove the code in mach-omap2/pm24xx.c that previously handled APLL autoidle control.

Signed-off-by Paul Walmsley <[email protected]>

Cc Kevin Hilman <[email protected]>

---
 arch/arm/mach-omap2/clkt2xxx_apll.c |   24 +++++++++++++++++++
 arch/arm/mach-omap2/cm2xxx_3xxx.c   |   44 ++++++++++++++++++++++++++++++++++-
 arch/arm/mach-omap2/cm2xxx_3xxx.h   |    5 ++++
 arch/arm/mach-omap2/pm24xx.c        |    8 ------
 4 files changed, 72 insertions(+), 9 deletions(-)

arch/arm/mach-omap2/clkt2xxx_apll.c +24 -0

index f51cffd..b19a1f7 100644
@@ -78,6 +78,26 @@ static int omap2_clk_apll54_enable(struct clk *clk)
 	return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK);
 }
 
+static void _apll96_allow_idle(struct clk *clk)
+{
+	omap2xxx_cm_set_apll96_auto_low_power_stop();
+}
+
+static void _apll96_deny_idle(struct clk *clk)
+{
+	omap2xxx_cm_set_apll96_disable_autoidle();
+}
+
+static void _apll54_allow_idle(struct clk *clk)
+{
+	omap2xxx_cm_set_apll54_auto_low_power_stop();
+}
+
+static void _apll54_deny_idle(struct clk *clk)
+{
+	omap2xxx_cm_set_apll54_disable_autoidle();
+}
+
 /* Stop APLL */
 static void omap2_clk_apll_disable(struct clk *clk)
 {

@@ -93,11 +113,15 @@ static void omap2_clk_apll_disable(struct clk *clk)
 const struct clkops clkops_apll96 = {
 	.enable		= omap2_clk_apll96_enable,
 	.disable	= omap2_clk_apll_disable,
+	.allow_idle	= _apll96_allow_idle,
+	.deny_idle	= _apll96_deny_idle,
 };
 
 const struct clkops clkops_apll54 = {
 	.enable		= omap2_clk_apll54_enable,
 	.disable	= omap2_clk_apll_disable,
+	.allow_idle	= _apll54_allow_idle,
+	.deny_idle	= _apll54_deny_idle,
 };
 
 /* Public functions */

arch/arm/mach-omap2/cm2xxx_3xxx.c +43 -1

59 lines not on this page · raw message

arch/arm/mach-omap2/cm2xxx_3xxx.h +5 -0

index 5f4df1c..088bbad 100644
@@ -125,6 +125,11 @@ extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
 extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
 extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
 
+extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
+extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
+extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
+extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
+
 #endif
 
 /* CM register bits shared between 24XX and 3430 */

arch/arm/mach-omap2/pm24xx.c +0 -8

index 23b4607..15b0f53 100644
@@ -378,7 +378,6 @@ static void __init prcm_setup_regs(void)
 {
 	int i, num_mem_banks;
 	struct powerdomain *pwrdm;
-	u32 v;
 
 	/* Enable autoidle */
 	omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,

@@ -469,13 +468,6 @@ static void __init prcm_setup_regs(void)
 	omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
 			       CM_AUTOIDLE);
 
-	/* Put both APLLs into autoidle mode */
-	v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
-	v &= ~(OMAP24XX_AUTO_96M_MASK | OMAP24XX_AUTO_54M_SHIFT);
-	v |= (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
-		(0x03 << OMAP24XX_AUTO_54M_SHIFT);
-	omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
-
 	omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
 			       OMAP24XX_AUTO_WDT1_MASK |
 			       OMAP24XX_AUTO_MPU_WDT_MASK |

Paul Walmsley

author maintainer

2011-02-16 06:52 UTC #4 lore raw

PATCH 4/11 OMAP2+: clock: comment that osc_ck/osc_sys_ck should use clockfw autoidle control

In reply to Paul Walmsley

Place some comments in the OMAP oscillator clock control code to note that its autoidle mode should eventually be controlled via the new OMAP clockfw autoidle control interface.

Signed-off-by Paul Walmsley <[email protected]>

---
 arch/arm/mach-omap2/clkt2xxx_osc.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

arch/arm/mach-omap2/clkt2xxx_osc.c +14 -0

index df7b805..c346092 100644
@@ -30,6 +30,13 @@
 #include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
 
+/*
+ * XXX This does not actually enable the osc_ck, since the osc_ck must
+ * be running for this function to be called.  Instead, this function
+ * is used to disable an autoidle mode on the osc_ck.  The existing
+ * clk_enable/clk_disable()-based usecounting for osc_ck should be
+ * replaced with autoidle-based usecounting.
+ */
 static int omap2_enable_osc_ck(struct clk *clk)
 {
 	u32 pcc;

@@ -41,6 +48,13 @@ static int omap2_enable_osc_ck(struct clk *clk)
 	return 0;
 }
 
+/*
+ * XXX This does not actually disable the osc_ck, since doing so would
+ * immediately halt the system.  Instead, this function is used to
+ * enable an autoidle mode on the osc_ck.  The existing
+ * clk_enable/clk_disable()-based usecounting for osc_ck should be
+ * replaced with autoidle-based usecounting.
+ */
 static void omap2_disable_osc_ck(struct clk *clk)
 {
 	u32 pcc;

Paul Walmsley

author maintainer

2011-02-16 06:52 UTC #5 lore raw

PATCH 5/11 OMAP2+: clock: add interface clock type code with autoidle support

In reply to Paul Walmsley

Add interface clock type code with autoidle enable/disable support. The clkops structures created in this file will be used for all OMAP2/3 interface clocks with autoidle support. They will enable the clock framework to control interface clock autoidle directly.

Signed-off-by Paul Walmsley <[email protected]>

---
 arch/arm/mach-omap2/Makefile    |    6 ++-
 arch/arm/mach-omap2/clkt_iclk.c |   73 +++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/clock.h     |    9 ++++-
 3 files changed, 85 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/mach-omap2/clkt_iclk.c

arch/arm/mach-omap2/Makefile +4 -2

index 41cb404..a28ba5a 100644
@@ -107,19 +107,21 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clockdomain.o \
 					   clockdomains2xxx_3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)		+= clockdomain.o \
 					   clockdomains44xx_data.o
+
 # Clock framework
 obj-$(CONFIG_ARCH_OMAP2)		+= $(clock-common) clock2xxx.o \
 					   clkt2xxx_sys.o \
 					   clkt2xxx_dpllcore.o \
 					   clkt2xxx_virt_prcm_set.o \
 					   clkt2xxx_apll.o clkt2xxx_osc.o \
-					   clkt2xxx_dpll.o
+					   clkt2xxx_dpll.o clkt_iclk.o
 obj-$(CONFIG_ARCH_OMAP2420)		+= clock2420_data.o
 obj-$(CONFIG_ARCH_OMAP2430)		+= clock2430.o clock2430_data.o
 obj-$(CONFIG_ARCH_OMAP3)		+= $(clock-common) clock3xxx.o \
 					   clock34xx.o clkt34xx_dpll3m2.o \
 					   clock3517.o clock36xx.o \
-					   dpll3xxx.o clock3xxx_data.o
+					   dpll3xxx.o clock3xxx_data.o \
+					   clkt_iclk.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common) clock44xx_data.o \
 					   dpll3xxx.o dpll44xx.o

arch/arm/mach-omap2/clkt_iclk.c new file +73 -0

73 lines not on this page · raw message

arch/arm/mach-omap2/clock.h +8 -1

index 9972d89..5008f14 100644
@@ -2,7 +2,7 @@
  *  linux/arch/arm/mach-omap2/clock.h
  *
  *  Copyright (C) 2005-2009 Texas Instruments, Inc.
- *  Copyright (C) 2004-2009 Nokia Corporation
+ *  Copyright (C) 2004-2011 Nokia Corporation
  *
  *  Contacts:
  *  Richard Woodruff <[email protected]>

@@ -86,6 +86,10 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
 int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
 
+/* clkt_iclk.c public functions */
+extern void omap2_clkt_iclk_allow_idle(struct clk *clk);
+extern void omap2_clkt_iclk_deny_idle(struct clk *clk);
+
 u32 omap2_get_dpll_rate(struct clk *clk);
 void omap2_init_dpll_parent(struct clk *clk);

@@ -148,6 +152,9 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
 #define omap2_clk_exit_cpufreq_table	0
 #endif
 
+extern const struct clkops clkops_omap2_iclk_dflt_wait;
+extern const struct clkops clkops_omap2_iclk_dflt;
+extern const struct clkops clkops_omap2_iclk_idle_only;
 extern const struct clkops clkops_omap2xxx_dpll_ops;
 extern const struct clkops clkops_omap3_noncore_dpll_ops;
 extern const struct clkops clkops_omap3_core_dpll_ops;

Paul Walmsley

author maintainer

2011-02-16 06:52 UTC #6 lore raw

PATCH 6/11 OMAP2420: clock: add sdrc_ick

In reply to Paul Walmsley

Add sdrc_ick to the OMAP2420 clock data so the clock code can control the CM_AUTOIDLE bit associated with this clock.

Signed-off-by Paul Walmsley <[email protected]>

---
 arch/arm/mach-omap2/clock2420_data.c  |   16 ++++++++++++++++
 arch/arm/mach-omap2/cm-regbits-24xx.h |    1 +
 2 files changed, 17 insertions(+), 0 deletions(-)

arch/arm/mach-omap2/clock2420_data.c +16 -0

index 30fbcbd..63ed481 100644
@@ -1608,6 +1608,21 @@ static struct clk sdma_ick = {
 	.recalc		= &followparent_recalc,
 };
 
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
+static struct clk sdrc_ick = {
+	.name		= "sdrc_ick",
+	.ops		= &clkops_omap2_iclk_idle_only,
+	.parent		= &core_l3_ck,
+	.flags		= ENABLE_ON_INIT,
+	.clkdm_name	= "core_l3_clkdm",
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+	.enable_bit	= OMAP24XX_AUTO_SDRC_SHIFT,
+	.recalc		= &followparent_recalc,
+};
+
 static struct clk vlynq_ick = {
 	.name		= "vlynq_ick",
 	.ops		= &clkops_omap2_dflt_wait,

@@ -1869,6 +1884,7 @@ static struct omap_clk omap2420_clks[] = {
 	CLK(NULL,	"gpmc_fck",	&gpmc_fck,	CK_242X),
 	CLK(NULL,	"sdma_fck",	&sdma_fck,	CK_242X),
 	CLK(NULL,	"sdma_ick",	&sdma_ick,	CK_242X),
+	CLK(NULL,	"sdrc_ick",	&sdrc_ick,	CK_242X),
 	CLK(NULL,	"vlynq_ick",	&vlynq_ick,	CK_242X),
 	CLK(NULL,	"vlynq_fck",	&vlynq_fck,	CK_242X),
 	CLK(NULL,	"des_ick",	&des_ick,	CK_242X),

arch/arm/mach-omap2/cm-regbits-24xx.h +1 -0

index d70660e..409c813 100644
@@ -210,6 +210,7 @@
 #define OMAP24XX_AUTO_USB_MASK				(1 << 0)
 
 /* CM_AUTOIDLE3_CORE */
+#define OMAP24XX_AUTO_SDRC_SHIFT			2
 #define OMAP24XX_AUTO_SDRC_MASK				(1 << 2)
 #define OMAP24XX_AUTO_GPMC_MASK				(1 << 1)
 #define OMAP24XX_AUTO_SDMA_MASK				(1 << 0)

Paul Walmsley

author maintainer

2011-02-16 06:52 UTC #7 lore raw

PATCH 7/11 OMAP2420: clock: use autoidle clkops for all autoidle-controllable interface clocks

In reply to Paul Walmsley

Mark each interface clock with a corresponding CM_AUTOIDLE bit with a clkops that has the allow_idle/deny_idle function pointers populated. This allows the OMAP clock framework to enable and disable autoidle for these clocks.

Signed-off-by Paul Walmsley <[email protected]>

---
 arch/arm/mach-omap2/clock2420_data.c  |  109 ++++++++++++++++++---------------
 arch/arm/mach-omap2/cm-regbits-24xx.h |    2 +
 2 files changed, 63 insertions(+), 48 deletions(-)

arch/arm/mach-omap2/clock2420_data.c +61 ~~-48~~

index 63ed481..68c0369 100644
@@ -2,7 +2,7 @@
  *  linux/arch/arm/mach-omap2/clock2420_data.c
  *
  *  Copyright (C) 2005-2009 Texas Instruments, Inc.
- *  Copyright (C) 2004-2010 Nokia Corporation
+ *  Copyright (C) 2004-2011 Nokia Corporation
  *
  *  Contacts:
  *  Richard Woodruff <[email protected]>

@@ -481,7 +481,7 @@ static struct clk dsp_irate_ick = {
 /* 2420 only */
 static struct clk dsp_ick = {
 	.name		= "dsp_ick",	 /* apparently ipi and isp */
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &dsp_irate_ick,
 	.enable_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
 	.enable_bit	= OMAP2420_EN_DSP_IPI_SHIFT,	      /* for ipi */

@@ -579,7 +579,7 @@ static const struct clksel usb_l4_ick_clksel[] = {
 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
 static struct clk usb_l4_ick = {	/* FS-USB interface clock */
 	.name		= "usb_l4_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &core_l3_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),

@@ -661,7 +661,7 @@ static struct clk ssi_ssr_sst_fck = {
  */
 static struct clk ssi_l4_ick = {
 	.name		= "ssi_l4_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),

@@ -716,6 +716,7 @@ static struct clk gfx_2d_fck = {
 	.recalc		= &omap2_clksel_recalc,
 };
 
+/* This interface clock does not have a CM_AUTOIDLE bit */
 static struct clk gfx_ick = {
 	.name		= "gfx_ick",		/* From l3 */
 	.ops		= &clkops_omap2_dflt_wait,

@@ -763,7 +764,7 @@ static const struct clksel dss1_fck_clksel[] = {
 
 static struct clk dss_ick = {		/* Enables both L3,L4 ICLK's */
 	.name		= "dss_ick",
-	.ops		= &clkops_omap2_dflt,
+	.ops		= &clkops_omap2_iclk_dflt,
 	.parent		= &l4_ck,	/* really both l3 and l4 */
 	.clkdm_name	= "dss_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -845,7 +846,7 @@ static const struct clksel omap24xx_gpt_clksel[] = {
 
 static struct clk gpt1_ick = {
 	.name		= "gpt1_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),

@@ -871,7 +872,7 @@ static struct clk gpt1_fck = {
 
 static struct clk gpt2_ick = {
 	.name		= "gpt2_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -895,7 +896,7 @@ static struct clk gpt2_fck = {
 
 static struct clk gpt3_ick = {
 	.name		= "gpt3_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -919,7 +920,7 @@ static struct clk gpt3_fck = {
 
 static struct clk gpt4_ick = {
 	.name		= "gpt4_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -943,7 +944,7 @@ static struct clk gpt4_fck = {
 
 static struct clk gpt5_ick = {
 	.name		= "gpt5_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -967,7 +968,7 @@ static struct clk gpt5_fck = {
 
 static struct clk gpt6_ick = {
 	.name		= "gpt6_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -991,7 +992,7 @@ static struct clk gpt6_fck = {
 
 static struct clk gpt7_ick = {
 	.name		= "gpt7_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT7_SHIFT,

@@ -1014,7 +1015,7 @@ static struct clk gpt7_fck = {
 
 static struct clk gpt8_ick = {
 	.name		= "gpt8_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1038,7 +1039,7 @@ static struct clk gpt8_fck = {
 
 static struct clk gpt9_ick = {
 	.name		= "gpt9_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1062,7 +1063,7 @@ static struct clk gpt9_fck = {
 
 static struct clk gpt10_ick = {
 	.name		= "gpt10_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1086,7 +1087,7 @@ static struct clk gpt10_fck = {
 
 static struct clk gpt11_ick = {
 	.name		= "gpt11_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1110,7 +1111,7 @@ static struct clk gpt11_fck = {
 
 static struct clk gpt12_ick = {
 	.name		= "gpt12_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1134,7 +1135,7 @@ static struct clk gpt12_fck = {
 
 static struct clk mcbsp1_ick = {
 	.name		= "mcbsp1_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1174,7 +1175,7 @@ static struct clk mcbsp1_fck = {
 
 static struct clk mcbsp2_ick = {
 	.name		= "mcbsp2_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1198,7 +1199,7 @@ static struct clk mcbsp2_fck = {
 
 static struct clk mcspi1_ick = {
 	.name		= "mcspi1_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1218,7 +1219,7 @@ static struct clk mcspi1_fck = {
 
 static struct clk mcspi2_ick = {
 	.name		= "mcspi2_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1238,7 +1239,7 @@ static struct clk mcspi2_fck = {
 
 static struct clk uart1_ick = {
 	.name		= "uart1_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1258,7 +1259,7 @@ static struct clk uart1_fck = {
 
 static struct clk uart2_ick = {
 	.name		= "uart2_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1278,7 +1279,7 @@ static struct clk uart2_fck = {
 
 static struct clk uart3_ick = {
 	.name		= "uart3_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),

@@ -1298,7 +1299,7 @@ static struct clk uart3_fck = {
 
 static struct clk gpios_ick = {
 	.name		= "gpios_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),

@@ -1318,7 +1319,7 @@ static struct clk gpios_fck = {
 
 static struct clk mpu_wdt_ick = {
 	.name		= "mpu_wdt_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),

@@ -1338,7 +1339,7 @@ static struct clk mpu_wdt_fck = {
 
 static struct clk sync_32k_ick = {
 	.name		= "sync_32k_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.flags		= ENABLE_ON_INIT,
 	.clkdm_name	= "core_l4_clkdm",

@@ -1349,7 +1350,7 @@ static struct clk sync_32k_ick = {
 
 static struct clk wdt1_ick = {
 	.name		= "wdt1_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),

@@ -1359,7 +1360,7 @@ static struct clk wdt1_ick = {
 
 static struct clk omapctrl_ick = {
 	.name		= "omapctrl_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.flags		= ENABLE_ON_INIT,
 	.clkdm_name	= "core_l4_clkdm",

@@ -1370,7 +1371,7 @@ static struct clk omapctrl_ick = {
 
 static struct clk cam_ick = {
 	.name		= "cam_ick",
-	.ops		= &clkops_omap2_dflt,
+	.ops		= &clkops_omap2_iclk_dflt,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1395,7 +1396,7 @@ static struct clk cam_fck = {
 
 static struct clk mailboxes_ick = {
 	.name		= "mailboxes_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1405,7 +1406,7 @@ static struct clk mailboxes_ick = {
 
 static struct clk wdt4_ick = {
 	.name		= "wdt4_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1425,7 +1426,7 @@ static struct clk wdt4_fck = {
 
 static struct clk wdt3_ick = {
 	.name		= "wdt3_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1445,7 +1446,7 @@ static struct clk wdt3_fck = {
 
 static struct clk mspro_ick = {
 	.name		= "mspro_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1465,7 +1466,7 @@ static struct clk mspro_fck = {
 
 static struct clk mmc_ick = {
 	.name		= "mmc_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1485,7 +1486,7 @@ static struct clk mmc_fck = {
 
 static struct clk fac_ick = {
 	.name		= "fac_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1505,7 +1506,7 @@ static struct clk fac_fck = {
 
 static struct clk eac_ick = {
 	.name		= "eac_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1525,7 +1526,7 @@ static struct clk eac_fck = {
 
 static struct clk hdq_ick = {
 	.name		= "hdq_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1545,7 +1546,7 @@ static struct clk hdq_fck = {
 
 static struct clk i2c2_ick = {
 	.name		= "i2c2_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1565,7 +1566,7 @@ static struct clk i2c2_fck = {
 
 static struct clk i2c1_ick = {
 	.name		= "i2c1_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1583,12 +1584,18 @@ static struct clk i2c1_fck = {
 	.recalc		= &followparent_recalc,
 };
 
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
 static struct clk gpmc_fck = {
 	.name		= "gpmc_fck",
-	.ops		= &clkops_null, /* RMK: missing? */
+	.ops		= &clkops_omap2_iclk_idle_only,
 	.parent		= &core_l3_ck,
 	.flags		= ENABLE_ON_INIT,
 	.clkdm_name	= "core_l3_clkdm",
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+	.enable_bit	= OMAP24XX_AUTO_GPMC_SHIFT,
 	.recalc		= &followparent_recalc,
 };

@@ -1600,11 +1607,17 @@ static struct clk sdma_fck = {
 	.recalc		= &followparent_recalc,
 };
 
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
 static struct clk sdma_ick = {
 	.name		= "sdma_ick",
-	.ops		= &clkops_null, /* RMK: missing? */
+	.ops		= &clkops_omap2_iclk_idle_only,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l3_clkdm",
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+	.enable_bit	= OMAP24XX_AUTO_SDMA_SHIFT,
 	.recalc		= &followparent_recalc,
 };

@@ -1625,7 +1638,7 @@ static struct clk sdrc_ick = {
 
 static struct clk vlynq_ick = {
 	.name		= "vlynq_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &core_l3_ck,
 	.clkdm_name	= "core_l3_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1674,7 +1687,7 @@ static struct clk vlynq_fck = {
 
 static struct clk des_ick = {
 	.name		= "des_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),

@@ -1684,7 +1697,7 @@ static struct clk des_ick = {
 
 static struct clk sha_ick = {
 	.name		= "sha_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),

@@ -1694,7 +1707,7 @@ static struct clk sha_ick = {
 
 static struct clk rng_ick = {
 	.name		= "rng_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),

@@ -1704,7 +1717,7 @@ static struct clk rng_ick = {
 
 static struct clk aes_ick = {
 	.name		= "aes_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),

@@ -1714,7 +1727,7 @@ static struct clk aes_ick = {
 
 static struct clk pka_ick = {
 	.name		= "pka_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),

arch/arm/mach-omap2/cm-regbits-24xx.h +2 -0

index 409c813..6862904 100644
@@ -212,7 +212,9 @@
 /* CM_AUTOIDLE3_CORE */
 #define OMAP24XX_AUTO_SDRC_SHIFT			2
 #define OMAP24XX_AUTO_SDRC_MASK				(1 << 2)
+#define OMAP24XX_AUTO_GPMC_SHIFT			1
 #define OMAP24XX_AUTO_GPMC_MASK				(1 << 1)
+#define OMAP24XX_AUTO_SDMA_SHIFT			0
 #define OMAP24XX_AUTO_SDMA_MASK				(1 << 0)
 
 /* CM_AUTOIDLE4_CORE */

Paul Walmsley

author maintainer

2011-02-16 06:52 UTC #8 lore raw

PATCH 8/11 OMAP2430/3xxx: clock: add modem clock autoidle support

In reply to Paul Walmsley

OMAP2430 and OMAP3xxx have modem autoidle bits that are actually attached to clocks with CM_FCLKEN bits; add the code and data to handle these.

Signed-off-by Paul Walmsley <[email protected]>

---
 arch/arm/mach-omap2/clkt_iclk.c |    9 +++++++++
 arch/arm/mach-omap2/clock.h     |    1 +
 2 files changed, 10 insertions(+), 0 deletions(-)

arch/arm/mach-omap2/clkt_iclk.c +9 -0

index dd8a6d3..3d43fba 100644
@@ -71,3 +71,12 @@ const struct clkops clkops_omap2_iclk_idle_only = {
 	.deny_idle	= omap2_clkt_iclk_deny_idle,
 };
 
+const struct clkops clkops_omap2_mdmclk_dflt_wait = {
+	.enable		= omap2_dflt_clk_enable,
+	.disable	= omap2_dflt_clk_disable,
+	.find_companion	= omap2_clk_dflt_find_companion,
+	.find_idlest	= omap2_clk_dflt_find_idlest,
+	.allow_idle	= omap2_clkt_iclk_allow_idle,
+	.deny_idle	= omap2_clkt_iclk_deny_idle,
+};
+

arch/arm/mach-omap2/clock.h +1 -0

index 5008f14..70f8b07 100644
@@ -155,6 +155,7 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
 extern const struct clkops clkops_omap2_iclk_dflt_wait;
 extern const struct clkops clkops_omap2_iclk_dflt;
 extern const struct clkops clkops_omap2_iclk_idle_only;
+extern const struct clkops clkops_omap2_mdmclk_dflt_wait;
 extern const struct clkops clkops_omap2xxx_dpll_ops;
 extern const struct clkops clkops_omap3_noncore_dpll_ops;
 extern const struct clkops clkops_omap3_core_dpll_ops;

Paul Walmsley

author maintainer

2011-02-16 06:52 UTC #9 lore raw

PATCH 9/11 OMAP2430: clock: use autoidle clkops for all autoidle-controllable interface clocks

In reply to Paul Walmsley

Signed-off-by Paul Walmsley <[email protected]>

---
 arch/arm/mach-omap2/clock2430_data.c |  125 +++++++++++++++++++---------------
 1 files changed, 69 insertions(+), 56 deletions(-)

arch/arm/mach-omap2/clock2430_data.c +69 ~~-56~~

index 1ff150a..34daed9 100644
@@ -2,7 +2,7 @@
  *  linux/arch/arm/mach-omap2/clock2430_data.c
  *
  *  Copyright (C) 2005-2009 Texas Instruments, Inc.
- *  Copyright (C) 2004-2010 Nokia Corporation
+ *  Copyright (C) 2004-2011 Nokia Corporation
  *
  *  Contacts:
  *  Richard Woodruff <[email protected]>

@@ -525,7 +525,7 @@ static const struct clksel usb_l4_ick_clksel[] = {
 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
 static struct clk usb_l4_ick = {	/* FS-USB interface clock */
 	.name		= "usb_l4_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &core_l3_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),

@@ -606,7 +606,7 @@ static struct clk ssi_ssr_sst_fck = {
  */
 static struct clk ssi_l4_ick = {
 	.name		= "ssi_l4_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),

@@ -661,6 +661,7 @@ static struct clk gfx_2d_fck = {
 	.recalc		= &omap2_clksel_recalc,
 };
 
+/* This interface clock does not have a CM_AUTOIDLE bit */
 static struct clk gfx_ick = {
 	.name		= "gfx_ick",		/* From l3 */
 	.ops		= &clkops_omap2_dflt_wait,

@@ -693,7 +694,7 @@ static const struct clksel mdm_ick_clksel[] = {
 
 static struct clk mdm_ick = {		/* used both as a ick and fck */
 	.name		= "mdm_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &core_ck,
 	.clkdm_name	= "mdm_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),

@@ -706,7 +707,7 @@ static struct clk mdm_ick = {		/* used both as a ick and fck */
 
 static struct clk mdm_osc_ck = {
 	.name		= "mdm_osc_ck",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_mdmclk_dflt_wait,
 	.parent		= &osc_ck,
 	.clkdm_name	= "mdm_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),

@@ -751,7 +752,7 @@ static const struct clksel dss1_fck_clksel[] = {
 
 static struct clk dss_ick = {		/* Enables both L3,L4 ICLK's */
 	.name		= "dss_ick",
-	.ops		= &clkops_omap2_dflt,
+	.ops		= &clkops_omap2_iclk_dflt,
 	.parent		= &l4_ck,	/* really both l3 and l4 */
 	.clkdm_name	= "dss_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -833,7 +834,7 @@ static const struct clksel omap24xx_gpt_clksel[] = {
 
 static struct clk gpt1_ick = {
 	.name		= "gpt1_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),

@@ -859,7 +860,7 @@ static struct clk gpt1_fck = {
 
 static struct clk gpt2_ick = {
 	.name		= "gpt2_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -883,7 +884,7 @@ static struct clk gpt2_fck = {
 
 static struct clk gpt3_ick = {
 	.name		= "gpt3_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -907,7 +908,7 @@ static struct clk gpt3_fck = {
 
 static struct clk gpt4_ick = {
 	.name		= "gpt4_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -931,7 +932,7 @@ static struct clk gpt4_fck = {
 
 static struct clk gpt5_ick = {
 	.name		= "gpt5_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -955,7 +956,7 @@ static struct clk gpt5_fck = {
 
 static struct clk gpt6_ick = {
 	.name		= "gpt6_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -979,7 +980,7 @@ static struct clk gpt6_fck = {
 
 static struct clk gpt7_ick = {
 	.name		= "gpt7_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= OMAP24XX_EN_GPT7_SHIFT,

@@ -1002,7 +1003,7 @@ static struct clk gpt7_fck = {
 
 static struct clk gpt8_ick = {
 	.name		= "gpt8_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1026,7 +1027,7 @@ static struct clk gpt8_fck = {
 
 static struct clk gpt9_ick = {
 	.name		= "gpt9_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1050,7 +1051,7 @@ static struct clk gpt9_fck = {
 
 static struct clk gpt10_ick = {
 	.name		= "gpt10_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1074,7 +1075,7 @@ static struct clk gpt10_fck = {
 
 static struct clk gpt11_ick = {
 	.name		= "gpt11_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1098,7 +1099,7 @@ static struct clk gpt11_fck = {
 
 static struct clk gpt12_ick = {
 	.name		= "gpt12_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1122,7 +1123,7 @@ static struct clk gpt12_fck = {
 
 static struct clk mcbsp1_ick = {
 	.name		= "mcbsp1_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1162,7 +1163,7 @@ static struct clk mcbsp1_fck = {
 
 static struct clk mcbsp2_ick = {
 	.name		= "mcbsp2_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1186,7 +1187,7 @@ static struct clk mcbsp2_fck = {
 
 static struct clk mcbsp3_ick = {
 	.name		= "mcbsp3_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),

@@ -1210,7 +1211,7 @@ static struct clk mcbsp3_fck = {
 
 static struct clk mcbsp4_ick = {
 	.name		= "mcbsp4_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),

@@ -1234,7 +1235,7 @@ static struct clk mcbsp4_fck = {
 
 static struct clk mcbsp5_ick = {
 	.name		= "mcbsp5_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),

@@ -1258,7 +1259,7 @@ static struct clk mcbsp5_fck = {
 
 static struct clk mcspi1_ick = {
 	.name		= "mcspi1_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1278,7 +1279,7 @@ static struct clk mcspi1_fck = {
 
 static struct clk mcspi2_ick = {
 	.name		= "mcspi2_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1298,7 +1299,7 @@ static struct clk mcspi2_fck = {
 
 static struct clk mcspi3_ick = {
 	.name		= "mcspi3_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),

@@ -1318,7 +1319,7 @@ static struct clk mcspi3_fck = {
 
 static struct clk uart1_ick = {
 	.name		= "uart1_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1338,7 +1339,7 @@ static struct clk uart1_fck = {
 
 static struct clk uart2_ick = {
 	.name		= "uart2_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1358,7 +1359,7 @@ static struct clk uart2_fck = {
 
 static struct clk uart3_ick = {
 	.name		= "uart3_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),

@@ -1378,7 +1379,7 @@ static struct clk uart3_fck = {
 
 static struct clk gpios_ick = {
 	.name		= "gpios_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),

@@ -1398,7 +1399,7 @@ static struct clk gpios_fck = {
 
 static struct clk mpu_wdt_ick = {
 	.name		= "mpu_wdt_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),

@@ -1418,7 +1419,7 @@ static struct clk mpu_wdt_fck = {
 
 static struct clk sync_32k_ick = {
 	.name		= "sync_32k_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.flags		= ENABLE_ON_INIT,
 	.clkdm_name	= "core_l4_clkdm",

@@ -1429,7 +1430,7 @@ static struct clk sync_32k_ick = {
 
 static struct clk wdt1_ick = {
 	.name		= "wdt1_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),

@@ -1439,7 +1440,7 @@ static struct clk wdt1_ick = {
 
 static struct clk omapctrl_ick = {
 	.name		= "omapctrl_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.flags		= ENABLE_ON_INIT,
 	.clkdm_name	= "core_l4_clkdm",

@@ -1450,7 +1451,7 @@ static struct clk omapctrl_ick = {
 
 static struct clk icr_ick = {
 	.name		= "icr_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),

@@ -1460,7 +1461,7 @@ static struct clk icr_ick = {
 
 static struct clk cam_ick = {
 	.name		= "cam_ick",
-	.ops		= &clkops_omap2_dflt,
+	.ops		= &clkops_omap2_iclk_dflt,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1485,7 +1486,7 @@ static struct clk cam_fck = {
 
 static struct clk mailboxes_ick = {
 	.name		= "mailboxes_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1495,7 +1496,7 @@ static struct clk mailboxes_ick = {
 
 static struct clk wdt4_ick = {
 	.name		= "wdt4_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1515,7 +1516,7 @@ static struct clk wdt4_fck = {
 
 static struct clk mspro_ick = {
 	.name		= "mspro_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1535,7 +1536,7 @@ static struct clk mspro_fck = {
 
 static struct clk fac_ick = {
 	.name		= "fac_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1555,7 +1556,7 @@ static struct clk fac_fck = {
 
 static struct clk hdq_ick = {
 	.name		= "hdq_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1579,7 +1580,7 @@ static struct clk hdq_fck = {
  */
 static struct clk i2c2_ick = {
 	.name		= "i2c2_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1603,7 +1604,7 @@ static struct clk i2chs2_fck = {
  */
 static struct clk i2c1_ick = {
 	.name		= "i2c1_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

@@ -1621,12 +1622,18 @@ static struct clk i2chs1_fck = {
 	.recalc		= &followparent_recalc,
 };
 
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
 static struct clk gpmc_fck = {
 	.name		= "gpmc_fck",
-	.ops		= &clkops_null, /* RMK: missing? */
+	.ops		= &clkops_omap2_iclk_idle_only,
 	.parent		= &core_l3_ck,
 	.flags		= ENABLE_ON_INIT,
 	.clkdm_name	= "core_l3_clkdm",
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+	.enable_bit	= OMAP24XX_AUTO_GPMC_SHIFT,
 	.recalc		= &followparent_recalc,
 };

@@ -1638,17 +1645,23 @@ static struct clk sdma_fck = {
 	.recalc		= &followparent_recalc,
 };
 
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
 static struct clk sdma_ick = {
 	.name		= "sdma_ick",
-	.ops		= &clkops_null, /* RMK: missing? */
+	.ops		= &clkops_omap2_iclk_idle_only,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l3_clkdm",
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+	.enable_bit	= OMAP24XX_AUTO_SDMA_SHIFT,
 	.recalc		= &followparent_recalc,
 };
 
 static struct clk sdrc_ick = {
 	.name		= "sdrc_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_idle_only,
 	.parent		= &l4_ck,
 	.flags		= ENABLE_ON_INIT,
 	.clkdm_name	= "core_l4_clkdm",

@@ -1659,7 +1672,7 @@ static struct clk sdrc_ick = {
 
 static struct clk des_ick = {
 	.name		= "des_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),

@@ -1669,7 +1682,7 @@ static struct clk des_ick = {
 
 static struct clk sha_ick = {
 	.name		= "sha_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),

@@ -1679,7 +1692,7 @@ static struct clk sha_ick = {
 
 static struct clk rng_ick = {
 	.name		= "rng_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),

@@ -1689,7 +1702,7 @@ static struct clk rng_ick = {
 
 static struct clk aes_ick = {
 	.name		= "aes_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),

@@ -1699,7 +1712,7 @@ static struct clk aes_ick = {
 
 static struct clk pka_ick = {
 	.name		= "pka_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),

@@ -1719,7 +1732,7 @@ static struct clk usb_fck = {
 
 static struct clk usbhs_ick = {
 	.name		= "usbhs_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &core_l3_ck,
 	.clkdm_name	= "core_l3_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),

@@ -1729,7 +1742,7 @@ static struct clk usbhs_ick = {
 
 static struct clk mmchs1_ick = {
 	.name		= "mmchs1_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),

@@ -1749,7 +1762,7 @@ static struct clk mmchs1_fck = {
 
 static struct clk mmchs2_ick = {
 	.name		= "mmchs2_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),

@@ -1768,7 +1781,7 @@ static struct clk mmchs2_fck = {
 
 static struct clk gpio5_ick = {
 	.name		= "gpio5_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),

@@ -1788,7 +1801,7 @@ static struct clk gpio5_fck = {
 
 static struct clk mdm_intc_ick = {
 	.name		= "mdm_intc_ick",
-	.ops		= &clkops_omap2_dflt_wait,
+	.ops		= &clkops_omap2_iclk_dflt_wait,
 	.parent		= &l4_ck,
 	.clkdm_name	= "core_l4_clkdm",
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),

Paul Walmsley

author maintainer

2011-02-16 06:52 UTC #10 lore raw

PATCH 10/11 OMAP3: clock: use autoidle clkops for all autoidle-controllable interface clocks

In reply to Paul Walmsley

Signed-off-by Paul Walmsley <[email protected]>

---
 arch/arm/mach-omap2/clock34xx.c      |   29 ++++++-
 arch/arm/mach-omap2/clock34xx.h      |    5 +
 arch/arm/mach-omap2/clock3517.c      |    4 +
 arch/arm/mach-omap2/clock3xxx_data.c |  149 ++++++++++++++++++----------------
 4 files changed, 112 insertions(+), 75 deletions(-)

arch/arm/mach-omap2/clock34xx.c +28 -1

index 287abc4..1fc96b9 100644
@@ -2,7 +2,7 @@
  * OMAP3-specific clock framework functions
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
  *
  * Paul Walmsley
  * Jouni H?gander

@@ -59,6 +59,15 @@ const struct clkops clkops_omap3430es2_ssi_wait = {
 	.find_companion = omap2_clk_dflt_find_companion,
 };
 
+const struct clkops clkops_omap3430es2_iclk_ssi_wait = {
+	.enable		= omap2_dflt_clk_enable,
+	.disable	= omap2_dflt_clk_disable,
+	.find_idlest	= omap3430es2_clk_ssi_find_idlest,
+	.find_companion = omap2_clk_dflt_find_companion,
+	.allow_idle	= omap2_clkt_iclk_allow_idle,
+	.deny_idle	= omap2_clkt_iclk_deny_idle,
+};
+
 /**
  * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
  * @clk: struct clk * being enabled

@@ -94,6 +103,15 @@ const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
 	.find_companion = omap2_clk_dflt_find_companion,
 };
 
+const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait = {
+	.enable		= omap2_dflt_clk_enable,
+	.disable	= omap2_dflt_clk_disable,
+	.find_idlest	= omap3430es2_clk_dss_usbhost_find_idlest,
+	.find_companion = omap2_clk_dflt_find_companion,
+	.allow_idle	= omap2_clkt_iclk_allow_idle,
+	.deny_idle	= omap2_clkt_iclk_deny_idle,
+};
+
 /**
  * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
  * @clk: struct clk * being enabled

@@ -124,3 +142,12 @@ const struct clkops clkops_omap3430es2_hsotgusb_wait = {
 	.find_idlest	= omap3430es2_clk_hsotgusb_find_idlest,
 	.find_companion = omap2_clk_dflt_find_companion,
 };
+
+const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait = {
+	.enable		= omap2_dflt_clk_enable,
+	.disable	= omap2_dflt_clk_disable,
+	.find_idlest	= omap3430es2_clk_hsotgusb_find_idlest,
+	.find_companion = omap2_clk_dflt_find_companion,
+	.allow_idle	= omap2_clkt_iclk_allow_idle,
+	.deny_idle	= omap2_clkt_iclk_deny_idle,
+};

arch/arm/mach-omap2/clock34xx.h +4 -1

index 628e8de..084ba71 100644
@@ -2,14 +2,17 @@
  * OMAP34xx clock function prototypes and macros
  *
  * Copyright (C) 2007-2010 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
  */
 
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
 
 extern const struct clkops clkops_omap3430es2_ssi_wait;
+extern const struct clkops clkops_omap3430es2_iclk_ssi_wait;
 extern const struct clkops clkops_omap3430es2_hsotgusb_wait;
+extern const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait;
 extern const struct clkops clkops_omap3430es2_dss_usbhost_wait;
+extern const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait;
 
 #endif

arch/arm/mach-omap2/clock3517.c +3 -1

index 74116a3..2e97d08 100644
@@ -2,7 +2,7 @@
  * OMAP3517/3505-specific clock framework functions
  *
  * Copyright (C) 2010 Texas Instruments, Inc.
- * Copyright (C) 2010 Nokia Corporation
+ * Copyright (C) 2011 Nokia Corporation
  *
  * Ranjith Lohithakshan
  * Paul Walmsley

@@ -119,6 +119,8 @@ const struct clkops clkops_am35xx_ipss_wait = {
 	.disable	= omap2_dflt_clk_disable,
 	.find_idlest	= am35xx_clk_ipss_find_idlest,
 	.find_companion	= omap2_clk_dflt_find_companion,
+	.allow_idle	= omap2_clkt_iclk_allow_idle,
+	.deny_idle	= omap2_clkt_iclk_deny_idle,
 };

arch/arm/mach-omap2/clock3xxx_data.c +77 ~~-72~~

593 lines not on this page · raw message

Paul Walmsley

author maintainer

2011-02-16 06:52 UTC #11 lore raw

PATCH 11/11 OMAP2/3: PM: remove manual CM_AUTOIDLE bit setting in mach-omap2/pm*xx.c

In reply to Paul Walmsley

These CM_AUTOIDLE bits are now set by the clock code via the common PM code in mach-omap2/pm.c.

N.B.: The pm24xx.c code that this patch removes didn't ensure that the CM_AUTOIDLE bits were set for several 2430-only modules, such as GPIO5, MDM_INTC, MMCHS1/2, the modem oscillator clock, and USBHS. Similarly, the pm34xx.c code that this patch removes didn't ensure that the CM_AUTOIDLE bits were set for USIM and the AM3517 UART4. Those cases should now be handled.

Signed-off-by Paul Walmsley <[email protected]>

Cc Kevin Hilman <[email protected]>

---
 arch/arm/mach-omap2/pm24xx.c |   63 ++-----------------------
 arch/arm/mach-omap2/pm34xx.c |  105 ------------------------------------------
 2 files changed, 5 insertions(+), 163 deletions(-)

arch/arm/mach-omap2/pm24xx.c +4 ~~-59~~

index 15b0f53..a168730 100644
@@ -379,7 +379,10 @@ static void __init prcm_setup_regs(void)
 	int i, num_mem_banks;
 	struct powerdomain *pwrdm;
 
-	/* Enable autoidle */
+	/*
+	 * Enable autoidle
+	 * XXX This should be handled by hwmod code or PRCM init code
+	 */
 	omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
 			  OMAP2_PRCM_SYSCONFIG_OFFSET);

@@ -418,64 +421,6 @@ static void __init prcm_setup_regs(void)
 	clkdm_for_each(clkdms_setup, NULL);
 	clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 
-	/* Enable clock autoidle for all domains */
-	omap2_cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK |
-			       OMAP24XX_AUTO_MAILBOXES_MASK |
-			       OMAP24XX_AUTO_WDT4_MASK |
-			       OMAP2420_AUTO_WDT3_MASK |
-			       OMAP24XX_AUTO_MSPRO_MASK |
-			       OMAP2420_AUTO_MMC_MASK |
-			       OMAP24XX_AUTO_FAC_MASK |
-			       OMAP2420_AUTO_EAC_MASK |
-			       OMAP24XX_AUTO_HDQ_MASK |
-			       OMAP24XX_AUTO_UART2_MASK |
-			       OMAP24XX_AUTO_UART1_MASK |
-			       OMAP24XX_AUTO_I2C2_MASK |
-			       OMAP24XX_AUTO_I2C1_MASK |
-			       OMAP24XX_AUTO_MCSPI2_MASK |
-			       OMAP24XX_AUTO_MCSPI1_MASK |
-			       OMAP24XX_AUTO_MCBSP2_MASK |
-			       OMAP24XX_AUTO_MCBSP1_MASK |
-			       OMAP24XX_AUTO_GPT12_MASK |
-			       OMAP24XX_AUTO_GPT11_MASK |
-			       OMAP24XX_AUTO_GPT10_MASK |
-			       OMAP24XX_AUTO_GPT9_MASK |
-			       OMAP24XX_AUTO_GPT8_MASK |
-			       OMAP24XX_AUTO_GPT7_MASK |
-			       OMAP24XX_AUTO_GPT6_MASK |
-			       OMAP24XX_AUTO_GPT5_MASK |
-			       OMAP24XX_AUTO_GPT4_MASK |
-			       OMAP24XX_AUTO_GPT3_MASK |
-			       OMAP24XX_AUTO_GPT2_MASK |
-			       OMAP2420_AUTO_VLYNQ_MASK |
-			       OMAP24XX_AUTO_DSS_MASK,
-			       CORE_MOD, CM_AUTOIDLE1);
-	omap2_cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK |
-			       OMAP24XX_AUTO_SSI_MASK |
-			       OMAP24XX_AUTO_USB_MASK,
-			       CORE_MOD, CM_AUTOIDLE2);
-	omap2_cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK |
-			       OMAP24XX_AUTO_GPMC_MASK |
-			       OMAP24XX_AUTO_SDMA_MASK,
-			       CORE_MOD, CM_AUTOIDLE3);
-	omap2_cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK |
-			       OMAP24XX_AUTO_AES_MASK |
-			       OMAP24XX_AUTO_RNG_MASK |
-			       OMAP24XX_AUTO_SHA_MASK |
-			       OMAP24XX_AUTO_DES_MASK,
-			       CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
-
-	omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
-			       CM_AUTOIDLE);
-
-	omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
-			       OMAP24XX_AUTO_WDT1_MASK |
-			       OMAP24XX_AUTO_MPU_WDT_MASK |
-			       OMAP24XX_AUTO_GPIOS_MASK |
-			       OMAP24XX_AUTO_32KSYNC_MASK |
-			       OMAP24XX_AUTO_GPT1_MASK,
-			       WKUP_MOD, CM_AUTOIDLE);
-
 	/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 	 * stabilisation */
 	omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,

arch/arm/mach-omap2/pm34xx.c +1 ~~-104~~

122 lines not on this page · raw message

Rajendra Nayak

2011-02-16 09:37 UTC #12 lore raw

cover OMAP2+: clock: add clockfw autoidle for iclks, OMAP2xxx

In reply to Paul Walmsley

Hi Paul,

Quoted 2 lines

-----Original Message-----
From: linux-arm-kernel-bounces at lists.infradead.org

[mailto:linux-arm-kernel-bounces at lists.infradead.org] On Behalf

Quoted 4 lines

Of Paul Walmsley
Sent: Wednesday, February 16, 2011 12:23 PM
To: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org
Subject: [PATCH 00/11] OMAP2+: clock: add clockfw autoidle for iclks,

OMAP2xxx

Quoted 10 lines

Hello,
This patch series adds clock framework-controlled autoidle support for the OMAP2xxx DPLL, APLLs, and OMAP2/3 interface clocks. The old direct register writes in the PM code to enable clock autoidle have been removed.
This series also ensures that all clock autoidle is disabled during boot and only re-enabled if CONFIG_PM is enabled.

This does not seem to be the case. Maybe something like the below patch is what is missing..

---

Paul Walmsley

author maintainer

2011-02-16 22:14 UTC #13 lore raw

cover OMAP2+: clock: add clockfw autoidle for iclks, OMAP2xxx

Hi Rajendra

Quoted 11 lines · Rajendra Nayak

Quoted 2 lines
-----Original Message-----
From: linux-arm-kernel-bounces at lists.infradead.org
[mailto:linux-arm-kernel-bounces at lists.infradead.org] On Behalf
Quoted 5 lines
Of Paul Walmsley
Sent: Wednesday, February 16, 2011 12:23 PM
This series also ensures that all clock autoidle is disabled during boot and only re-enabled if CONFIG_PM is enabled.
This does not seem to be the case. Maybe something like the below patch is what is missing..

Thanks for the review, you are absolutely right. Rather than the patch you sent, and since mach-omap2/pm.c is compiled in even if !CONFIG_PM, I'd propose a different approach. Until we can sort out the CONFIG_PM/pm.c issue, probably it would make more sense to move the autoidle-enable as part of CONFIG_OMAP_RESET_CLOCKS. Will send a patch in reply to the original thread.

- Paul

Rajendra Nayak

2011-02-18 05:33 UTC #14 lore raw

cover OMAP2+: clock: add clockfw autoidle for iclks, OMAP2xxx

Hi Paul,

Quoted 6 lines

-----Original Message-----
From: Paul Walmsley [mailto:paul at pwsan.com]
Sent: Thursday, February 17, 2011 3:44 AM
To: Rajendra Nayak
Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org
Subject: RE: [PATCH 00/11] OMAP2+: clock: add clockfw autoidle for

iclks, OMAP2xxx

Quoted 14 lines

Hi Rajendra
Quoted 9 lines · Rajendra Nayak
Quoted 2 lines
-----Original Message-----
From: linux-arm-kernel-bounces at lists.infradead.org
[mailto:linux-arm-kernel-bounces at lists.infradead.org] On Behalf
Quoted 5 lines
Of Paul Walmsley
Sent: Wednesday, February 16, 2011 12:23 PM
This series also ensures that all clock autoidle is disabled during boot and only re-enabled if CONFIG_PM is enabled.

Quoted 8 lines

Quoted 2 lines
This does not seem to be the case. Maybe something like the below patch is what is missing..
Thanks for the review, you are absolutely right. Rather than the patch you sent, and since mach-omap2/pm.c is compiled in even if !CONFIG_PM, I'd propose a different approach. Until we can sort out the CONFIG_PM/pm.c issue, probably it would make more sense to move the autoidle-enable as part of CONFIG_OMAP_RESET_CLOCKS. Will send a patch

Quoted 1 line

reply to the original thread.

I had a look at the patch and it does look like a better way to handle it for now, till the CONFIG options are further cleaned up. Thanks,
Rajendra

Quoted 3 lines

- Paul

Rajendra Nayak

2011-02-16 11:15 UTC #15 lore raw

cover OMAP2+: clock: add clockfw autoidle for iclks, OMAP2xxx

In reply to Paul Walmsley

Quoted 2 lines

-----Original Message-----
From: linux-arm-kernel-bounces at lists.infradead.org

[mailto:linux-arm-kernel-bounces at lists.infradead.org] On Behalf

Quoted 4 lines

Of Paul Walmsley
Sent: Wednesday, February 16, 2011 12:23 PM
To: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org
Subject: [PATCH 00/11] OMAP2+: clock: add clockfw autoidle for iclks,

OMAP2xxx

Quoted 11 lines

Hello,
This patch series adds clock framework-controlled autoidle support for the OMAP2xxx DPLL, APLLs, and OMAP2/3 interface clocks. The old direct register writes in the PM code to enable clock autoidle have been removed.
This series also ensures that all clock autoidle is disabled during boot and only re-enabled if CONFIG_PM is enabled.

Quoted 6 lines

The series applies on the 'clk_autoidle_a_2.6.39' branch of
git://git.pwsan.com/linux-2.6.
Boot-tested on N800, and dynamic idle-tested on OMAP3430 Beagleboard. Compile-tested with omap1_defconfig, omap2plus_defconfig, a 5912 OSK-only config, an N8x0-only config, an OMAP3-only config, and an

OMAP4-only

Quoted 1 line

config.

Boot-tested on 3430sdp/4430sdp, with CONFIG_PM and with !CONFIG_PM. suspend-offmode tested on 3430sdp and suspend-retmode on 4430sdp (with some out-of-tree patches)
Dynamic idle testing on 3430sdp showed me some very jerky debug console the
moment a 'echo 1 > /debug/pm_debug/sleep_while_idle' is done. This however seems to be the case even on 2.6.38-rc4 and not related to the
current patch series. Will debug further, but seems to some 3430sdp specific
issue, since you did not see it on Beagleboard and seems it is not seen on OMAP3
zoom's either.
Just out of curiosity, what dynamic-idle state where you able to achieve on
Beagle? And what was the debug console timeout that you configured?

Regards,
Rajendra

Quoted 9 lines

- Paul
---
clk_autoidle_b_2.6.39
text data bss dec hex filename
5530703 330544 5594520 11455767 aecd17

vmlinux.omap2plus_defconfig.orig

Quoted 1 line

5531167 330544 5594520 11456231 aecee7

vmlinux.omap2plus_defconfig.patched

Quoted 6 lines

Paul Walmsley (11):
OMAP2+: clock: disable autoidle on all clocks during clock init
OMAP2: clock: add DPLL autoidle support
OMAP2xxx: clock: add clockfw autoidle support for APLLs OMAP2+: clock: comment that osc_ck/osc_sys_ck should use clockfw

autoidle control

Quoted 3 lines

OMAP2+: clock: add interface clock type code with autoidle support
OMAP2420: clock: add sdrc_ick
OMAP2420: clock: use autoidle clkops for all autoidle-controllable

interface clocks

Quoted 2 lines

OMAP2430/3xxx: clock: add modem clock autoidle support
OMAP2430: clock: use autoidle clkops for all autoidle-controllable

interface clocks

Quoted 1 line

OMAP3: clock: use autoidle clkops for all autoidle-controllable

interface clocks

Quoted 1 line

OMAP2/3: PM: remove manual CM_AUTOIDLE bit setting in

mach-omap2/pm*xx.c

Quoted 9 lines


 arch/arm/mach-omap2/Makefile          |    7 +
 arch/arm/mach-omap2/clkt2xxx_apll.c   |   24 +++++
 arch/arm/mach-omap2/clkt2xxx_dpll.c   |   63 +++++++++++++
 arch/arm/mach-omap2/clkt2xxx_osc.c    |   14 +++
 arch/arm/mach-omap2/clkt_iclk.c       |   82 +++++++++++++++++
 arch/arm/mach-omap2/clock.h           |   11 ++
 arch/arm/mach-omap2/clock2420_data.c  |  130

+++++++++++++++++-----------

Quoted 1 line

 arch/arm/mach-omap2/clock2430_data.c  |  130

++++++++++++++++------------

Quoted 5 lines

 arch/arm/mach-omap2/clock34xx.c       |   29 ++++++
 arch/arm/mach-omap2/clock34xx.h       |    5 +
 arch/arm/mach-omap2/clock3517.c       |    4 +
 arch/arm/mach-omap2/clock3xxx.c       |    3 -
 arch/arm/mach-omap2/clock3xxx_data.c  |  155

+++++++++++++++++----------------

Quoted 15 lines

 arch/arm/mach-omap2/clock44xx_data.c  |    3 +
 arch/arm/mach-omap2/cm-regbits-24xx.h |    3 +
 arch/arm/mach-omap2/cm2xxx_3xxx.c     |   69 +++++++++++++++
 arch/arm/mach-omap2/cm2xxx_3xxx.h     |    8 ++
 arch/arm/mach-omap2/pm24xx.c          |   69 +--------------
 arch/arm/mach-omap2/pm34xx.c          |  105 ----------------------
 19 files changed, 557 insertions(+), 357 deletions(-)
 create mode 100644 arch/arm/mach-omap2/clkt2xxx_dpll.c
 create mode 100644 arch/arm/mach-omap2/clkt_iclk.c

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linux-arm-kernel at lists.infradead.org
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Paul Walmsley

author maintainer

2011-02-16 23:05 UTC #16 lore raw

cover OMAP2+: clock: add clockfw autoidle for iclks, OMAP2xxx

Quoted 3 lines · Rajendra Nayak

Boot-tested on 3430sdp/4430sdp, with CONFIG_PM and with !CONFIG_PM. suspend-offmode tested on 3430sdp and suspend-retmode on 4430sdp (with some out-of-tree patches)

Thanks, will add Tested-by:s.

Quoted 4 lines

Dynamic idle testing on 3430sdp showed me some very jerky debug console the moment a 'echo 1 > /debug/pm_debug/sleep_while_idle' is done. This however seems to be the case even on 2.6.38-rc4 and not related to the current patch series.

Does enabling CONFIG_OMAP2_DSS resolve the problem you're seeing?

Quoted 4 lines

Will debug further, but seems to some 3430sdp specific issue, since you did not see it on Beagleboard and seems it is not seen on OMAP3 zoom's either. Just out of curiosity, what dynamic-idle state where you able to achieve on Beagle?

Full chip off. I use omap2plus_defconfig, sometimes with CONFIG_OMAP2_DSS depending on personal mood and what's being tested. I boot to a shell and run the commands at the end of this message (some of which are probably superfluous).

- Paul

echo 1 > /debug/pm_debug/sleep_while_idle
echo 1 > /debug/pm_debug/enable_off_mode
echo 5 > /sys/devices/platform/omap/omap_uart.0/sleep_timeout echo 5 > /sys/devices/platform/omap/omap_uart.1/sleep_timeout echo 5 > /sys/devices/platform/omap/omap_uart.2/sleep_timeout echo enabled > /sys/devices/platform/omap/omap_uart.0/tty/ttyO0/power/wakeup echo enabled > /sys/devices/platform/omap/omap_uart.1/tty/ttyO1/power/wakeup echo enabled > /sys/devices/platform/omap/omap_uart.2/tty/ttyO2/power/wakeup

Rajendra Nayak

2011-02-18 05:35 UTC #17 lore raw

cover OMAP2+: clock: add clockfw autoidle for iclks, OMAP2xxx

Quoted 6 lines

-----Original Message-----
From: Paul Walmsley [mailto:paul at pwsan.com]
Sent: Thursday, February 17, 2011 4:35 AM
To: Rajendra Nayak
Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org
Subject: RE: [PATCH 00/11] OMAP2+: clock: add clockfw autoidle for

iclks, OMAP2xxx

Quoted 10 lines · Rajendra Nayak

Quoted 4 lines
Boot-tested on 3430sdp/4430sdp, with CONFIG_PM and with !CONFIG_PM. suspend-offmode tested on 3430sdp and suspend-retmode on 4430sdp (with some out-of-tree patches)
Thanks, will add Tested-by:s.
Quoted 1 line
Dynamic idle testing on 3430sdp showed me some very jerky debug

console

Quoted 5 lines

Quoted 3 lines
the moment a 'echo 1 > /debug/pm_debug/sleep_while_idle' is done. This however seems to be the case even on 2.6.38-rc4 and not related to the current patch series.
Does enabling CONFIG_OMAP2_DSS resolve the problem you're seeing?

Maybe, will try it out. Thanks for the tip.

Quoted 2 lines

Quoted 2 lines
Will debug further, but seems to some 3430sdp specific issue, since

you

Quoted 2 lines

Quoted 2 lines
did not see it on Beagleboard and seems it is not seen on OMAP3 zoom's either. Just out of curiosity, what dynamic-idle state where you able

Quoted 3 lines

Quoted 1 line
achieve on Beagle?
Full chip off. I use omap2plus_defconfig, sometimes with

CONFIG_OMAP2_DSS

Quoted 1 line

depending on personal mood and what's being tested. I boot to a shell

and

Quoted 2 lines

run the commands at the end of this message (some of which are probably superfluous).

Ok, thanks.

Quoted 11 lines

- Paul
echo 1 > /debug/pm_debug/sleep_while_idle
echo 1 > /debug/pm_debug/enable_off_mode
echo 5 > /sys/devices/platform/omap/omap_uart.0/sleep_timeout echo 5 > /sys/devices/platform/omap/omap_uart.1/sleep_timeout echo 5 > /sys/devices/platform/omap/omap_uart.2/sleep_timeout echo enabled >

/sys/devices/platform/omap/omap_uart.0/tty/ttyO0/power/wakeup

Quoted 1 line

echo enabled >

/sys/devices/platform/omap/omap_uart.1/tty/ttyO1/power/wakeup

Quoted 1 line

echo enabled >

/sys/devices/platform/omap/omap_uart.2/tty/ttyO2/power/wakeup

Quoted 1 line

Kevin Hilman

2011-03-01 20:58 UTC #18 lore raw

cover OMAP2+: clock: add clockfw autoidle for iclks, OMAP2xxx

In reply to Paul Walmsley

Quoted 10 lines · Paul Walmsley

Hello,
This patch series adds clock framework-controlled autoidle support for the OMAP2xxx DPLL, APLLs, and OMAP2/3 interface clocks. The old direct register writes in the PM code to enable clock autoidle have been removed.
This series also ensures that all clock autoidle is disabled during boot and only re-enabled if CONFIG_PM is enabled.

Quoted 7 lines

The series applies on the 'clk_autoidle_a_2.6.39' branch of
git://git.pwsan.com/linux-2.6.
Boot-tested on N800, and dynamic idle-tested on OMAP3430 Beagleboard. Compile-tested with omap1_defconfig, omap2plus_defconfig, a 5912 OSK-only config, an N8x0-only config, an OMAP3-only config, and an OMAP4-only config.

Reviewed-by Kevin Hilman <[email protected]>

Feel free to merge the various pm*.c changes via your tree.

Kevin

Paul Walmsley

author maintainer

2011-03-08 03:06 UTC #19 lore raw

cover OMAP2+: clock: add clockfw autoidle for iclks, OMAP2xxx

Quoted 13 lines · Kevin Hilman

Quoted 11 lines · Paul Walmsley
This patch series adds clock framework-controlled autoidle support for the OMAP2xxx DPLL, APLLs, and OMAP2/3 interface clocks. The old direct register writes in the PM code to enable clock autoidle have been removed.
This series also ensures that all clock autoidle is disabled during boot and only re-enabled if CONFIG_PM is enabled.
The series applies on the 'clk_autoidle_a_2.6.39' branch of
git://git.pwsan.com/linux-2.6.

Quoted 6 lines

Quoted 4 lines
Boot-tested on N800, and dynamic idle-tested on OMAP3430 Beagleboard. Compile-tested with omap1_defconfig, omap2plus_defconfig, a 5912 OSK-only config, an N8x0-only config, an OMAP3-only config, and an OMAP4-only config.
Reviewed-by Kevin Hilman <[email protected]>

Thanks, added your Reviewed-by: on these.

Quoted 1 line

Feel free to merge the various pm*.c changes via your tree.

- Paul