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Longhaul - There are limits

PATCH In review Rafał Bilski 2 participants 2 messages Jul 4, 2006 – Jul 6, 2006

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PATCH 1/1 Longhaul - There are limits

Hello!

There is no need to worry about local APIC.
There is need to worry about I/O APIC, because I/O APIC is replacing good old 8259. Acording to Nehemiah datasheet VIA is using 3-wire bus to connect local APIC to I/O APIC.

"[...] When IA32_APIC_BASE[11] is set to 0, processor APICs based on the 3-wire APIC
bus cannot be generally re-enabled until a system hardware reset. The 3-wire bus looses track of arbitration that would be necessary for complete re-enabling. Certain (local) APIC functionality can be enabled. [...]"

So we must set disable bit for each interrupt in I/O APIC registers. Same situation as for PIC - we must poke registers direcly. How to do this? I don't know. So at the moment it is better to fail.

---

arch/i386/kernel/cpu/cpufreq/Kconfig +1 -1
diff -uprN -X linux-2.6.17-git20-vanilla/Documentation/dontdiff linux-2.6.17-git20-vanilla/arch/i386/kernel/cpu/cpufreq/Kconfig linux-2.6.17-git20/arch/i386/kernel/cpu/cpufreq/Kconfig
@@ -202,7 +202,7 @@ config X86_LONGRUN
 config X86_LONGHAUL
 	tristate "VIA Cyrix III Longhaul"
 	select CPU_FREQ_TABLE
-	depends on BROKEN
+	depends on ACPI_PROCESSOR
 	help
 	  This adds the CPUFreq driver for VIA Samuel/CyrixIII,
 	  VIA Cyrix Samuel/C3, VIA Cyrix Ezra and VIA Cyrix Ezra-T
arch/i386/kernel/cpu/cpufreq/longhaul.c +9 -0
diff -uprN -X linux-2.6.17-git20-vanilla/Documentation/dontdiff linux-2.6.17-git20-vanilla/arch/i386/kernel/cpu/cpufreq/longhaul.c linux-2.6.17-git20/arch/i386/kernel/cpu/cpufreq/longhaul.c
@@ -534,6 +534,15 @@ static int __init longhaul_cpu_init(stru
 	char *cpuname=NULL;
 	int ret;
 
+#ifdef CONFIG_SMP
+	if (num_online_cpus() > 1)
+		return -ENODEV;
+#endif
+#ifdef CONFIG_X86_IO_APIC
+	if (cpu_has_apic)
+		return -ENODEV;
+#endif
+
 	switch (c->x86_model) {
 	case 6:
 		cpu_model = CPU_SAMUEL;

------------------------------------------------------------------------
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#1 lore raw
Quoted 12 lines · RafaÅ‚ Bilski

Hello!

There is no need to worry about local APIC.
There is need to worry about I/O APIC, because I/O APIC is replacing good old 8259. Acording to Nehemiah datasheet VIA is using 3-wire bus to connect local APIC to I/O APIC.

"[...] When IA32_APIC_BASE[11] is set to 0, processor APICs based on the 3-wire APIC
bus cannot be generally re-enabled until a system hardware reset. The 3-wire bus looses track of arbitration that would be necessary for complete re-enabling. Certain (local) APIC functionality can be enabled. [...]"

Quoted 4 lines

So we must set disable bit for each interrupt in I/O APIC registers. Same situation as for PIC - we must poke registers direcly. How to do this? I don't know. So at the moment it is better to fail.

Ok, I'll merge this up. We can revisit the APIC stuff later.

Thanks,

Dave

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