Add special MIPS multiply instructions
PATCH 1/1 Add special MIPS multiply instructions
This is an update of MIPS NEC VR5400 special instruction patch [1]. It is necessary because of MIPS instruction set configuration patch. Therefore this patch has to be applied on top of
http://lists.gnu.org/archive/html/qemu-devel/2006-07/msg00158.html
Best regards
Dirk
[1]
http://lists.gnu.org/archive/html/qemu-devel/2006-04/msg00375.html
target-mips/op_helper.c renamed from target-mips/op_helper.c_orig +271 -0
@@ -128,6 +128,134 @@ void do_msubu (void) tmp = ((uint64_t )T0 * (uint64_t )T1 );set_HILO (get_HILO () - tmp); } + +#ifdef MIPS_USES_NEC_VR5400 +void do_muls (void ) +{ +int64_t tmp; + + tmp =0 - ((int64_t )(int32_t )T0 * (int64_t )(int32_t )T1 ); +set_HILO (tmp); +T0 = tmp &0xFFFFFFFF ; +} + +void do_mulsu (void ) +{ +uint64_t tmp; + + tmp =0 - ((uint64_t )(uint32_t )T0 * (uint64_t )(uint32_t )T1 ); +set_HILO (tmp); +T0 = tmp &0xFFFFFFFF ; +} + +void do_macc (void ) +{ +int64_t tmp; + + tmp = ((int64_t )get_HILO ()) + ((int64_t )(int32_t )T0 * (int64_t )(int32_t )T1 ); +set_HILO (tmp); +T0 = tmp &0xFFFFFFFF ; +} + +void do_macchi (void ) +{ +int64_t tmp; + + tmp = ((int64_t )get_HILO ()) + ((int64_t )(int32_t )T0 * (int64_t )(int32_t )T1 ); +set_HILO (tmp); +T0 = tmp >>32 ; +} + +void do_maccu (void ) +{ +uint64_t tmp; + + tmp = ((uint64_t )get_HILO ()) + ((uint64_t )(uint32_t )T0 * (uint64_t )(uint32_t )T1 ); +set_HILO (tmp); +T0 = tmp &0xFFFFFFFF ; +} + +void do_macchiu (void ) +{ +uint64_t tmp; + + tmp = ((uint64_t )get_HILO ()) + ((uint64_t )(uint32_t )T0 * (uint64_t )(uint32_t )T1 ); +set_HILO (tmp); +T0 = tmp >>32 ; +} + +void do_msac (void ) +{ +int64_t tmp; + + tmp = ((int64_t )get_HILO ()) - ((int64_t )(int32_t )T0 * (int64_t )(int32_t )T1 ); +set_HILO (tmp); +T0 = tmp &0xFFFFFFFF ; +} + +void do_msachi (void ) +{ +int64_t tmp; + + tmp = ((int64_t )get_HILO ()) - ((int64_t )(int32_t )T0 * (int64_t )(int32_t )T1 ); +set_HILO (tmp); +T0 = tmp >>32 ; +} + +void do_msacu (void ) +{ +uint64_t tmp; + + tmp = ((uint64_t )get_HILO ()) - ((uint64_t )(uint32_t )T0 * (uint64_t )(uint32_t )T1 ); +set_HILO (tmp); +T0 = tmp &0xFFFFFFFF ; +} + +void do_msachiu (void ) +{ +uint64_t tmp; + + tmp = ((uint64_t )get_HILO ()) - ((uint64_t )(uint32_t )T0 * (uint64_t )(uint32_t )T1 ); +set_HILO (tmp); +T0 = tmp >>32 ; +} + +void do_mulhi (void ) +{ +int64_t tmp; + + tmp = ((int64_t )(int32_t )T0 * (int64_t )(int32_t )T1 ); +set_HILO (tmp); +T0 = tmp >>32 ; +} + +void do_mulhiu (void ) +{ +uint64_t tmp; + + tmp = ((uint64_t )(uint32_t )T0 * (uint64_t )(uint32_t )T1 ); +set_HILO (tmp); +T0 = tmp >>32 ; +} + +void do_mulshi (void ) +{ +int64_t tmp; + + tmp =0 - ((int64_t )(int32_t )T0 * (int64_t )(int32_t )T1 ); +set_HILO (tmp); +T0 = tmp >>32 ; +} + +void do_mulshiu (void ) +{ +uint64_t tmp; + + tmp =0 - ((uint64_t )(uint32_t )T0 * (uint64_t )(uint32_t )T1 ); +set_HILO (tmp); +T0 = tmp >>32 ; +} +#endif /* MIPS_USES_NEC_VR5400 */ #endif #if defined(CONFIG_USER_ONLY )
@@ -159,6 +287,149 @@ void do_tlbr (void) {cpu_abort (env,"tlbr\n" ); } + +#ifdef MIPS_USES_NEC_VR5400 +void op_muls (void ) +{ +int64_t tmp; + + tmp =0 - ((int64_t )(int32_t )T0 * (int64_t )(int32_t )T1 ); +set_HILO (tmp); +T0 = tmp &0xFFFFFFFF ; +RETURN (); +} + +void op_mulsu (void ) +{ +uint64_t tmp; + + tmp =0 - ((uint64_t )(uint32_t )T0 * (uint64_t )(uint32_t )T1 ); +set_HILO (tmp); +T0 = tmp &0xFFFFFFFF ; +RETURN (); +} + +void op_macc (void ) +{ +int64_t tmp; + + tmp = ((int64_t )get_HILO ()) + ((int64_t )(int32_t )T0 * (int64_t )(int32_t )T1 ); +set_HILO (tmp); +T0 = tmp &0xFFFFFFFF ; +RETURN (); +} + +void op_macchi (void ) +{ +int64_t tmp; + + tmp = ((int64_t )get_HILO ()) + ((int64_t )(int32_t )T0 * (int64_t )(int32_t )T1 ); +set_HILO (tmp); +T0 = tmp >>32 ; +RETURN (); +} + +void op_maccu (void ) +{ +uint64_t tmp; + + tmp = ((uint64_t )get_HILO ()) + ((uint64_t )(uint32_t )T0 * (uint64_t )(uint32_t )T1 ); +set_HILO (tmp); +T0 = tmp &0xFFFFFFFF ; +RETURN (); +} + +void op_macchiu (void ) +{ +uint64_t tmp; + + tmp = ((uint64_t )get_HILO ()) + ((uint64_t )(uint32_t )T0 * (uint64_t )(uint32_t )T1 ); +set_HILO (tmp); +T0 = tmp >>32 ; +RETURN (); +} + +void op_msac (void ) +{ +int64_t tmp; + + tmp = ((int64_t )get_HILO ()) - ((int64_t )(int32_t )T0 * (int64_t )(int32_t )T1 ); +set_HILO (tmp); +T0 = tmp &0xFFFFFFFF ; +RETURN (); +} + +void op_msachi (void ) +{ +int64_t tmp; + + tmp = ((int64_t )get_HILO ()) - ((int64_t )(int32_t )T0 * (int64_t )(int32_t )T1 ); +set_HILO (tmp); +T0 = tmp >>32 ; +RETURN (); +} + +void op_msacu (void ) +{ +uint64_t tmp; + + tmp = ((uint64_t )get_HILO ()) - ((uint64_t )(uint32_t )T0 * (uint64_t )(uint32_t )T1 ); +set_HILO (tmp); +T0 = tmp &0xFFFFFFFF ; +RETURN (); +} + +void op_msachiu (void ) +{ +uint64_t tmp; + + tmp = ((uint64_t )get_HILO ()) - ((uint64_t )(uint32_t )T0 * (uint64_t )(uint32_t )T1 ); +set_HILO (tmp); +T0 = tmp >>32 ; +RETURN (); +} + +void op_mulhi (void ) +{ +int64_t tmp; + + tmp = ((int64_t )(int32_t )T0 * (int64_t )(int32_t )T1 ); +set_HILO (tmp); +T0 = tmp >>32 ; +RETURN (); +} + +void op_mulhiu (void ) +{ +uint64_t tmp; + + tmp = ((uint64_t )(uint32_t )T0 * (uint64_t )(uint32_t )T1 ); +set_HILO (tmp); +T0 = tmp >>32 ; +RETURN (); +} + +void op_mulshi (void ) +{ +int64_t tmp; + + tmp =0 - ((int64_t )(int32_t )T0 * (int64_t )(int32_t )T1 ); +set_HILO (tmp); +T0 = tmp >>32 ; +RETURN (); +} + +void op_mulshiu (void ) +{ +uint64_t tmp; + + tmp =0 - ((uint64_t )(uint32_t )T0 * (uint64_t )(uint32_t )T1 ); +set_HILO (tmp); +T0 = tmp >>32 ; +RETURN (); +} +#endif /* MIPS_USES_NEC_VR5400 */ +#else /* CP0 helpers */
target-mips/op.c renamed from target-mips/op.c_orig +227 -0
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target-mips/translate.c renamed from target-mips/translate.c_orig +76 -1
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