PIO port width on various archs?
I'm changing the kvm userspace interface to be more friendly to other archs. One issue is the PIO port size. x86 uses 16 bits to hold the port size (64K ports). Is that an issue for other archs?
I guess I could change it to __u32, but it's better to know what various architectures actually require.
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Quoted 6 lines · Avi Kivity
I'm changing the kvm userspace interface to be more friendly to other archs. One issue is the PIO port size. x86 uses 16 bits to hold the port size (64K ports). Is that an issue for other archs?
I guess I could change it to
__u32, but it's better to know what various architectures actually require.
PowerPC doesn't have any such concept; access to ISA PIO is done by having the bridge translate a particular range of MMIO accesses as PIO. I'm no expert, but I don't know of any mainstream processor other than x86 that supports PIO.
-Hollis
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Quoted 6 lines · Hollis Blanchard
Quoted 4 lines · Avi Kivity
I'm changing the kvm userspace interface to be more friendly to other archs. One issue is the PIO port size. x86 uses 16 bits to hold the port size (64K ports). Is that an issue for other archs?
Quoted 10 lines
Quoted 3 lines
I guess I could change it to
__u32, but it's better to know what various architectures actually require.PowerPC doesn't have any such concept; access to ISA PIO is done by having the bridge translate a particular range of MMIO accesses as PIO. I'm no expert, but I don't know of any mainstream processor other than x86 that supports PIO.
I think ia64 does, but it's probably exactly the same as x86.
Signature · 8 lines
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Quoted 10 lines · Avi Kivity
Quoted 9 lines · Hollis Blanchard
Quoted 7 lines · Avi Kivity
I'm changing the kvm userspace interface to be more friendly to other archs. One issue is the PIO port size. x86 uses 16 bits to hold the port size (64K ports). Is that an issue for other archs?
I guess I could change it to
__u32, but it's better to know what various architectures actually require.
Quoted 7 lines
Quoted 5 lines
PowerPC doesn't have any such concept; access to ISA PIO is done by having the bridge translate a particular range of MMIO accesses as PIO. I'm no expert, but I don't know of any mainstream processor other than x86 that supports PIO.
I think ia64 does, but it's probably exactly the same as x86.
IA64 uses a special memory range which is translated into I/O port accesses by the CPU hardware (as opposed to the I/O bridge.) Section 10.7 of volume 2 of the Itanium SDM has the details. Only 64k of I/O ports is supported.
Brian J. Johnson
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