PPC440EPx/440GRx Sequoia/Rainier board support.
PATCH 1/1 PPC440EPx/440GRx Sequoia/Rainier board support.
Add AMCC PPC440EPx/440GRx Sequoia/Rainier board support.
arch/powerpc/kernel/cputable.c +40 -0
@@ -1179,6 +1179,46 @@ .dcache_bsize = 32, .platform = "ppc440", }, + {/* 440EPx - with Security/Kasumi */ + .pvr_mask = 0xf0000fff, + .pvr_value = 0x200008D0, + .cpu_name = "440EPx - with Security/Kasumi", + .cpu_features = CPU_FTRS_44X, + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, + .icache_bsize = 32, + .dcache_bsize = 32, + .platform = "ppc440", + }, + { /* 440EPx - without Security/Kasumi */ + .pvr_mask = 0xf0000fff, + .pvr_value = 0x200008D4, + .cpu_name = "440EPx - no Security/Kasumi", + .cpu_features = CPU_FTRS_44X, + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, + .icache_bsize = 32, + .dcache_bsize = 32, + .platform = "ppc440", + }, + { /* 440GRx - with Security/Kasumi */ + .pvr_mask = 0xf0000fff, + .pvr_value = 0x200008D8, + .cpu_name = "440GRx - with Security/Kasumi", + .cpu_features = CPU_FTRS_44X, + .cpu_user_features = COMMON_USER_BOOKE, + .icache_bsize = 32, + .dcache_bsize = 32, + .platform = "ppc440", + }, + { /* 440GRx - without Security/Kasumi */ + .pvr_mask = 0xf0000fff, + .pvr_value = 0x200008DC, + .cpu_name = "440GRx - no Security/Kasumi", + .cpu_features = CPU_FTRS_44X, + .cpu_user_features = COMMON_USER_BOOKE, + .icache_bsize = 32, + .dcache_bsize = 32, + .platform ="ppc440" , + }, #endif /* CONFIG_44x */ #ifdef CONFIG_FSL_BOOKE { /* e200z5 */
arch/ppc/kernel/head_44x.S +1 -1
@@ -227,7 +227,7 @@ lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ mtspr SPRN_IVPR,r4 -#ifdef CONFIG_440EP +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) /* Clear DAPUIB flag in CCR0 (enable APU between CPU and FPU) */ mfspr r2,SPRN_CCR0 lis r3,0xffef
arch/ppc/platforms/4xx/Kconfig +31 -3
@@ -104,6 +104,18 @@ help This option enables support for the AMCC PPC440GX evaluation board. +config SEQUOIA + bool "Sequoia" + select WANT_EARLY_SERIAL + help + This option enables support for the AMCC PPC440EPx evaluation board. + +config RAINIER + bool "Rainier" + select WANT_EARLY_SERIAL + help + This option enables support for the AMCC PPC440GRx evaluation board. + endchoice config EP405PC
@@ -125,6 +137,17 @@ select PPC_FPU default y +config 440EPX + bool + depends on SEQUOIA + select PPC_FPU + default y + +config 440GRX + bool + depends on RAINIER + default y + config 440GP bool depends on EBONY
@@ -152,7 +175,7 @@ config 440A bool - depends on 440GX + depends on 440GX || 440EPX || 440GRX default y config IBM440EP_ERR42
@@ -179,12 +202,17 @@ config IBM_OCP bool - depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || TAISHAN || WALNUT + depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SEQUOIA || RAINIER || SYCAMORE || TAISHAN || WALNUT default y config IBM_EMAC4 bool - depends on 440GX || 440SP || 440SPE + depends on 440GX || 440SP || 440SPE || 440EPX || 440GRX + default y + +config IBM_EMAC4V4 + bool + depends on 440EPX || 440GRX default y config BIOS_FIXUP
arch/ppc/platforms/4xx/Makefile +4 -0
@@ -9,8 +9,10 @@ obj-$(CONFIG_LUAN) += luan.o obj-$(CONFIG_YUCCA) += yucca.o obj-$(CONFIG_OCOTEA) += ocotea.o +obj-$(CONFIG_RAINIER) += sequoia.o obj-$(CONFIG_REDWOOD_5) += redwood5.o obj-$(CONFIG_REDWOOD_6) += redwood6.o +obj-$(CONFIG_SEQUOIA) += sequoia.o obj-$(CONFIG_SYCAMORE) += sycamore.o obj-$(CONFIG_TAISHAN) += taishan.o obj-$(CONFIG_WALNUT) += walnut.o
@@ -22,7 +24,9 @@ obj-$(CONFIG_NP405H) += ibmnp405h.o obj-$(CONFIG_REDWOOD_6) += ibmstbx25.o obj-$(CONFIG_440EP) += ibm440ep.o +obj-$(CONFIG_440EPX) += ppc440epx.o obj-$(CONFIG_440GP) += ibm440gp.o +obj-$(CONFIG_440GRX) += ppc440epx.o obj-$(CONFIG_440GX) += ibm440gx.o obj-$(CONFIG_440SP) += ibm440sp.o obj-$(CONFIG_440SPE) += ppc440spe.o
arch/ppc/platforms/4xx/ppc440epx.c +284 -0
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arch/ppc/platforms/4xx/ppc440epx.h +85 -0
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arch/ppc/platforms/4xx/sequoia.c +557 -0
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arch/ppc/platforms/4xx/sequoia.h +117 -0
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arch/ppc/syslib/ibm440gx_common.c +4 -2
@@ -31,7 +31,8 @@u32 plld =CPR_READ (DCRN_CPR_PLLD );u32 uart0 =SDR_READ (DCRN_SDR_UART0 );u32 uart1 =SDR_READ (DCRN_SDR_UART1 ); -#ifdef CONFIG_440EP +#if defined(CONFIG_440EP ) || \ + defined(CONFIG_440EPX ) || defined(CONFIG_440GRX )u32 uart2 =SDR_READ (DCRN_SDR_UART2 );u32 uart3 =SDR_READ (DCRN_SDR_UART3 );#endif
@@ -97,7 +98,8 @@ p->uart1 = ser_clk; else p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256); -#ifdef CONFIG_440EP +#if defined(CONFIG_440EP ) || \ + defined(CONFIG_440EPX ) || defined(CONFIG_440GRX )if (uart2 &0x00800000 ) p->uart2 = ser_clk;else
arch/ppc/syslib/ibm44x_common.c +24 -0
@@ -221,6 +221,30 @@mfdcr (DCRN_PLB1_BEARH ),mfdcr (DCRN_PLB1_BEARL ),mfdcr (DCRN_PLB1_ACR ),mfdcr (DCRN_PLB1_BESRH ), mfdcr(DCRN_PLB1_BESRL)); +#elif defined(CONFIG_440EPX )|| defined(CONFIG_440GRX ) +printk ("OPB to PLB3: BSTAT= 0x%08x\n" , +mfdcr (DCRN_OPB2PLB30_BSTAT )); +printk ("PLB3 to PLB4: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n" , +mfdcr (DCRN_P3P4BI0_BEARH ),mfdcr (DCRN_P3P4BI0_BEARL ), +mfdcr (DCRN_P3P4BI0_BESR0 ),mfdcr (DCRN_P3P4BI0_BESR1 )); +printk ("PLB4 to PLB3: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n" , +mfdcr (DCRN_P4P3BO0_BEARH ),mfdcr (DCRN_P4P3BO0_BEARL ), +mfdcr (DCRN_P4P3BO0_BESR0 ),mfdcr (DCRN_P4P3BO0_BESR1 )); +printk ("PLB3 to OPB: BEAR=0x%08x BESR0=0x%08x BESR1=0x%08x\n" , +mfdcr (DCRN_PLB32OPB0_BEAR ), +mfdcr (DCRN_PLB32OPB0_BESR0 ),mfdcr (DCRN_PLB32OPB0_BESR1 )); +printk ("PLB3 arbiter: BEAR=0x%08x ACR=0x%08x BESR=0x%08x\n" , +mfdcr (DCRN_PLB3A0_BEAR ), +mfdcr (DCRN_PLB3A0_ACR ),mfdcr (DCRN_PLB3A0_BESR )); +printk ("PLB4 to OPB1: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n" , +mfdcr (DCRN_PLB42OPB1_BEARH ),mfdcr (DCRN_PLB42OPB1_BEARL ), +mfdcr (DCRN_PLB42OPB1_BESR0 ),mfdcr (DCRN_PLB42OPB1_BESR1 )); +printk ("PLB40 Arbiter: BEAR=0x%08x%08x ACR=0x%08x BESR0=0x%08x\n" , +mfdcr (DCRN_PLB4A0_BEARH ),mfdcr (DCRN_PLB4A0_BEARL ), +mfdcr (DCRN_PLB4A0_ACR ),mfdcr (DCRN_PLB4A0_BESR )); +printk ("PLB41 Arbiter: BEAR=0x%08x%08x ACR=0x%08x BESR0=0x%08x\n" , +mfdcr (DCRN_PLB4A1_BEARH ),mfdcr (DCRN_PLB4A1_BEARL ), +mfdcr (DCRN_PLB4A1_ACR ),mfdcr (DCRN_PLB4A1_BESR ));#else printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x\n", mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
arch/ppc/syslib/ibm44x_common.h +2 -1
@@ -27,7 +27,8 @@unsigned int ebc;/* PerClk */ unsigned int uart0;unsigned int uart1; -#ifdef CONFIG_440EP +#if defined(CONFIG_440EP ) || \ + defined(CONFIG_440EPX ) || defined(CONFIG_440GRX )unsigned int uart2;unsigned int uart3;#endif
arch/ppc/syslib/Makefile +4 -0
@@ -12,7 +12,9 @@ obj-$(CONFIG_IBM_OCP) += ibm_ocp.o obj-$(CONFIG_44x) += ibm44x_common.o obj-$(CONFIG_440EP) += ibm440gx_common.o +obj-$(CONFIG_440EPX) += ibm440gx_common.o obj-$(CONFIG_440GP) += ibm440gp_common.o +obj-$(CONFIG_440GRX) += ibm440gx_common.o obj-$(CONFIG_440GX) += ibm440gx_common.o obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o obj-$(CONFIG_440SPE) += ibm440gx_common.o ibm440sp_common.o ppc440spe_pcie.o
@@ -70,6 +72,8 @@ obj-$(CONFIG_SPRUCE) += cpc700_pic.o pci_auto.o \ todc_time.o obj-$(CONFIG_TAISHAN) += pci_auto.o +obj-$(CONFIG_SEQUOIA) += pci_auto.o +obj-$(CONFIG_RAINIER) += pci_auto.o obj-$(CONFIG_8260) += m8260_setup.o pq2_devices.o pq2_sys.o \ ppc_sys.o obj-$(CONFIG_PCI_8260) += m82xx_pci.o pci_auto.o
arch/ppc/syslib/ppc4xx_pic.c +29 -0
@@ -118,6 +118,34 @@ }#elif NR_UICS ==3 +#if defined(CONFIG_440EPX ) || defined(CONFIG_440GRX ) +#define ACK_UIC0_PARENT +#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC); +#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC2NC); +UIC_HANDLERS (0 ); +UIC_HANDLERS (1 ); +UIC_HANDLERS (2 ); + +static int ppc4xx_pic_get_irq (void ) +{ +u32 uic0 =mfdcr (DCRN_UIC_MSR (UIC0 )); +if (uic0 &UIC0_UIC1NC ) +return 64 -ffs (mfdcr (DCRN_UIC_MSR (UIC1 ))); +else if (uic0 &UIC0_UIC2NC ) +return 96 -ffs (mfdcr (DCRN_UIC_MSR (UIC2 ))); +else +return uic0 ?32 -ffs (uic0) :-1 ; +} + +static void __init ppc4xx_pic_impl_init (void ) +{ +/* Enable cascade interrupts in UIC0 */ + ppc_cached_irq_mask[0 ] |=UIC0_UIC1NC |UIC0_UIC2NC ; +mtdcr (DCRN_UIC_SR (UIC0 ),UIC0_UIC1NC |UIC0_UIC2NC ); +mtdcr (DCRN_UIC_ER (UIC0 ), ppc_cached_irq_mask[0 ]); +} + +#else /* #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ #define ACK_UIC0_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC);#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC);
@@ -151,6 +179,7 @@mtdcr (DCRN_UIC_SR (UICB ),0xffffffff ); mtdcr(DCRN_UIC_ER(UICB), UICB_UIC0NC | UICB_UIC1NC | UICB_UIC2NC); } +#endif /* #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ #elif NR_UICS == 2#define ACK_UIC0_PARENT
include/asm-ppc/ibm44x.h +85 -10
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include/asm-ppc/ibm4xx.h +4 -0
@@ -113,6 +113,10 @@#include <platforms/4xx/taishan.h> #endif +#if defined(CONFIG_SEQUOIA ) || defined(CONFIG_RAINIER ) +#include <platforms/4xx/sequoia.h> +#endif +#ifndef __ASSEMBLY__#ifdef CONFIG_40x/*
Quoted 3 lines · Valentine Barshak
Add AMCC PPC440EPx/440GRx Sequoia/Rainier board support.
Signed-off-by Valentine Barshak <[email protected]>
Might I kindly ask you to include at least my Signed-off-by line before yours, since this code seems to be nearly a 1:1 copy from our implementation. Thanks.
And yes (before someone asks), I wanted to commit this Sequoia/Rainer support, but didn't find the time till now to do the last clean-up's and submit upstream.
Best regards,
Stefan
Quoted 8 lines · Stefan Roese
Quoted 3 lines · Valentine Barshak
Add AMCC PPC440EPx/440GRx Sequoia/Rainier board support.
Signed-off-by Valentine Barshak <[email protected]>Might I kindly ask you to include at least my Signed-off-by line before yours, since this code seems to be nearly a 1:1 copy from our implementation. Thanks.
I was going to ask about that. This seems identical to what's been in the denx tree for a while. If it came from there, it needs Stefan's sign off.
josh
Add AMCC PPC440EPx/440GRx Sequoia/Rainier board support.
arch/powerpc/kernel/cputable.c +40 -0
@@ -1179,6 +1179,46 @@ .dcache_bsize = 32, .platform = "ppc440", }, + {/* 440EPx - with Security/Kasumi */ + .pvr_mask = 0xf0000fff, + .pvr_value = 0x200008D0, + .cpu_name = "440EPx - with Security/Kasumi", + .cpu_features = CPU_FTRS_44X, + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, + .icache_bsize = 32, + .dcache_bsize = 32, + .platform = "ppc440", + }, + { /* 440EPx - without Security/Kasumi */ + .pvr_mask = 0xf0000fff, + .pvr_value = 0x200008D4, + .cpu_name = "440EPx - no Security/Kasumi", + .cpu_features = CPU_FTRS_44X, + .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, + .icache_bsize = 32, + .dcache_bsize = 32, + .platform = "ppc440", + }, + { /* 440GRx - with Security/Kasumi */ + .pvr_mask = 0xf0000fff, + .pvr_value = 0x200008D8, + .cpu_name = "440GRx - with Security/Kasumi", + .cpu_features = CPU_FTRS_44X, + .cpu_user_features = COMMON_USER_BOOKE, + .icache_bsize = 32, + .dcache_bsize = 32, + .platform = "ppc440", + }, + { /* 440GRx - without Security/Kasumi */ + .pvr_mask = 0xf0000fff, + .pvr_value = 0x200008DC, + .cpu_name = "440GRx - no Security/Kasumi", + .cpu_features = CPU_FTRS_44X, + .cpu_user_features = COMMON_USER_BOOKE, + .icache_bsize = 32, + .dcache_bsize = 32, + .platform ="ppc440" , + }, #endif /* CONFIG_44x */ #ifdef CONFIG_FSL_BOOKE { /* e200z5 */
arch/ppc/kernel/head_44x.S +1 -1
@@ -227,7 +227,7 @@ lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ mtspr SPRN_IVPR,r4 -#ifdef CONFIG_440EP +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) /* Clear DAPUIB flag in CCR0 (enable APU between CPU and FPU) */ mfspr r2,SPRN_CCR0 lis r3,0xffef
arch/ppc/platforms/4xx/Kconfig +31 -3
@@ -104,6 +104,18 @@ help This option enables support for the AMCC PPC440GX evaluation board. +config SEQUOIA + bool "Sequoia" + select WANT_EARLY_SERIAL + help + This option enables support for the AMCC PPC440EPx evaluation board. + +config RAINIER + bool "Rainier" + select WANT_EARLY_SERIAL + help + This option enables support for the AMCC PPC440GRx evaluation board. + endchoice config EP405PC
@@ -125,6 +137,17 @@ select PPC_FPU default y +config 440EPX + bool + depends on SEQUOIA + select PPC_FPU + default y + +config 440GRX + bool + depends on RAINIER + default y + config 440GP bool depends on EBONY
@@ -152,7 +175,7 @@ config 440A bool - depends on 440GX + depends on 440GX || 440EPX || 440GRX default y config IBM440EP_ERR42
@@ -179,12 +202,17 @@ config IBM_OCP bool - depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || TAISHAN || WALNUT + depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SEQUOIA || RAINIER || SYCAMORE || TAISHAN || WALNUT default y config IBM_EMAC4 bool - depends on 440GX || 440SP || 440SPE + depends on 440GX || 440SP || 440SPE || 440EPX || 440GRX + default y + +config IBM_EMAC4V4 + bool + depends on 440EPX || 440GRX default y config BIOS_FIXUP
arch/ppc/platforms/4xx/Makefile +4 -0
@@ -9,8 +9,10 @@ obj-$(CONFIG_LUAN) += luan.o obj-$(CONFIG_YUCCA) += yucca.o obj-$(CONFIG_OCOTEA) += ocotea.o +obj-$(CONFIG_RAINIER) += sequoia.o obj-$(CONFIG_REDWOOD_5) += redwood5.o obj-$(CONFIG_REDWOOD_6) += redwood6.o +obj-$(CONFIG_SEQUOIA) += sequoia.o obj-$(CONFIG_SYCAMORE) += sycamore.o obj-$(CONFIG_TAISHAN) += taishan.o obj-$(CONFIG_WALNUT) += walnut.o
@@ -22,7 +24,9 @@ obj-$(CONFIG_NP405H) += ibmnp405h.o obj-$(CONFIG_REDWOOD_6) += ibmstbx25.o obj-$(CONFIG_440EP) += ibm440ep.o +obj-$(CONFIG_440EPX) += ppc440epx.o obj-$(CONFIG_440GP) += ibm440gp.o +obj-$(CONFIG_440GRX) += ppc440epx.o obj-$(CONFIG_440GX) += ibm440gx.o obj-$(CONFIG_440SP) += ibm440sp.o obj-$(CONFIG_440SPE) += ppc440spe.o
arch/ppc/platforms/4xx/ppc440epx.c +284 -0
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arch/ppc/platforms/4xx/ppc440epx.h +85 -0
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arch/ppc/platforms/4xx/sequoia.c +557 -0
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arch/ppc/platforms/4xx/sequoia.h +117 -0
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arch/ppc/syslib/ibm440gx_common.c +4 -2
@@ -31,7 +31,8 @@u32 plld =CPR_READ (DCRN_CPR_PLLD );u32 uart0 =SDR_READ (DCRN_SDR_UART0 );u32 uart1 =SDR_READ (DCRN_SDR_UART1 ); -#ifdef CONFIG_440EP +#if defined(CONFIG_440EP ) || \ + defined(CONFIG_440EPX ) || defined(CONFIG_440GRX )u32 uart2 =SDR_READ (DCRN_SDR_UART2 );u32 uart3 =SDR_READ (DCRN_SDR_UART3 );#endif
@@ -97,7 +98,8 @@ p->uart1 = ser_clk; else p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256); -#ifdef CONFIG_440EP +#if defined(CONFIG_440EP ) || \ + defined(CONFIG_440EPX ) || defined(CONFIG_440GRX )if (uart2 &0x00800000 ) p->uart2 = ser_clk;else
arch/ppc/syslib/ibm44x_common.c +24 -0
@@ -221,6 +221,30 @@mfdcr (DCRN_PLB1_BEARH ),mfdcr (DCRN_PLB1_BEARL ),mfdcr (DCRN_PLB1_ACR ),mfdcr (DCRN_PLB1_BESRH ), mfdcr(DCRN_PLB1_BESRL)); +#elif defined(CONFIG_440EPX )|| defined(CONFIG_440GRX ) +printk ("OPB to PLB3: BSTAT= 0x%08x\n" , +mfdcr (DCRN_OPB2PLB30_BSTAT )); +printk ("PLB3 to PLB4: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n" , +mfdcr (DCRN_P3P4BI0_BEARH ),mfdcr (DCRN_P3P4BI0_BEARL ), +mfdcr (DCRN_P3P4BI0_BESR0 ),mfdcr (DCRN_P3P4BI0_BESR1 )); +printk ("PLB4 to PLB3: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n" , +mfdcr (DCRN_P4P3BO0_BEARH ),mfdcr (DCRN_P4P3BO0_BEARL ), +mfdcr (DCRN_P4P3BO0_BESR0 ),mfdcr (DCRN_P4P3BO0_BESR1 )); +printk ("PLB3 to OPB: BEAR=0x%08x BESR0=0x%08x BESR1=0x%08x\n" , +mfdcr (DCRN_PLB32OPB0_BEAR ), +mfdcr (DCRN_PLB32OPB0_BESR0 ),mfdcr (DCRN_PLB32OPB0_BESR1 )); +printk ("PLB3 arbiter: BEAR=0x%08x ACR=0x%08x BESR=0x%08x\n" , +mfdcr (DCRN_PLB3A0_BEAR ), +mfdcr (DCRN_PLB3A0_ACR ),mfdcr (DCRN_PLB3A0_BESR )); +printk ("PLB4 to OPB1: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n" , +mfdcr (DCRN_PLB42OPB1_BEARH ),mfdcr (DCRN_PLB42OPB1_BEARL ), +mfdcr (DCRN_PLB42OPB1_BESR0 ),mfdcr (DCRN_PLB42OPB1_BESR1 )); +printk ("PLB40 Arbiter: BEAR=0x%08x%08x ACR=0x%08x BESR0=0x%08x\n" , +mfdcr (DCRN_PLB4A0_BEARH ),mfdcr (DCRN_PLB4A0_BEARL ), +mfdcr (DCRN_PLB4A0_ACR ),mfdcr (DCRN_PLB4A0_BESR )); +printk ("PLB41 Arbiter: BEAR=0x%08x%08x ACR=0x%08x BESR0=0x%08x\n" , +mfdcr (DCRN_PLB4A1_BEARH ),mfdcr (DCRN_PLB4A1_BEARL ), +mfdcr (DCRN_PLB4A1_ACR ),mfdcr (DCRN_PLB4A1_BESR ));#else printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x\n", mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
arch/ppc/syslib/ibm44x_common.h +2 -1
@@ -27,7 +27,8 @@unsigned int ebc;/* PerClk */ unsigned int uart0;unsigned int uart1; -#ifdef CONFIG_440EP +#if defined(CONFIG_440EP ) || \ + defined(CONFIG_440EPX ) || defined(CONFIG_440GRX )unsigned int uart2;unsigned int uart3;#endif
arch/ppc/syslib/Makefile +4 -0
@@ -12,7 +12,9 @@ obj-$(CONFIG_IBM_OCP) += ibm_ocp.o obj-$(CONFIG_44x) += ibm44x_common.o obj-$(CONFIG_440EP) += ibm440gx_common.o +obj-$(CONFIG_440EPX) += ibm440gx_common.o obj-$(CONFIG_440GP) += ibm440gp_common.o +obj-$(CONFIG_440GRX) += ibm440gx_common.o obj-$(CONFIG_440GX) += ibm440gx_common.o obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o obj-$(CONFIG_440SPE) += ibm440gx_common.o ibm440sp_common.o ppc440spe_pcie.o
@@ -70,6 +72,8 @@ obj-$(CONFIG_SPRUCE) += cpc700_pic.o pci_auto.o \ todc_time.o obj-$(CONFIG_TAISHAN) += pci_auto.o +obj-$(CONFIG_SEQUOIA) += pci_auto.o +obj-$(CONFIG_RAINIER) += pci_auto.o obj-$(CONFIG_8260) += m8260_setup.o pq2_devices.o pq2_sys.o \ ppc_sys.o obj-$(CONFIG_PCI_8260) += m82xx_pci.o pci_auto.o
arch/ppc/syslib/ppc4xx_pic.c +29 -0
@@ -118,6 +118,34 @@ }#elif NR_UICS ==3 +#if defined(CONFIG_440EPX ) || defined(CONFIG_440GRX ) +#define ACK_UIC0_PARENT +#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC); +#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC2NC); +UIC_HANDLERS (0 ); +UIC_HANDLERS (1 ); +UIC_HANDLERS (2 ); + +static int ppc4xx_pic_get_irq (void ) +{ +u32 uic0 =mfdcr (DCRN_UIC_MSR (UIC0 )); +if (uic0 &UIC0_UIC1NC ) +return 64 -ffs (mfdcr (DCRN_UIC_MSR (UIC1 ))); +else if (uic0 &UIC0_UIC2NC ) +return 96 -ffs (mfdcr (DCRN_UIC_MSR (UIC2 ))); +else +return uic0 ?32 -ffs (uic0) :-1 ; +} + +static void __init ppc4xx_pic_impl_init (void ) +{ +/* Enable cascade interrupts in UIC0 */ + ppc_cached_irq_mask[0 ] |=UIC0_UIC1NC |UIC0_UIC2NC ; +mtdcr (DCRN_UIC_SR (UIC0 ),UIC0_UIC1NC |UIC0_UIC2NC ); +mtdcr (DCRN_UIC_ER (UIC0 ), ppc_cached_irq_mask[0 ]); +} + +#else /* #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ #define ACK_UIC0_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC);#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC);
@@ -151,6 +179,7 @@mtdcr (DCRN_UIC_SR (UICB ),0xffffffff ); mtdcr(DCRN_UIC_ER(UICB), UICB_UIC0NC | UICB_UIC1NC | UICB_UIC2NC); } +#endif /* #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ #elif NR_UICS == 2#define ACK_UIC0_PARENT
include/asm-ppc/ibm44x.h +85 -10
162 lines not on this page · raw message
include/asm-ppc/ibm4xx.h +4 -0
@@ -113,6 +113,10 @@#include <platforms/4xx/taishan.h> #endif +#if defined(CONFIG_SEQUOIA ) || defined(CONFIG_RAINIER ) +#include <platforms/4xx/sequoia.h> +#endif +#ifndef __ASSEMBLY__#ifdef CONFIG_40x/*
Valentine,
Quoted 5 lines · in message <[email protected]> you wrote:
Add AMCC PPC440EPx/440GRx Sequoia/Rainier board support.
Signed-off-by Stefan Roese <[email protected]>Signed-off-by Valentine Barshak <[email protected]>
Umm...
arch/ppc/platforms/4xx/ppc440epx.c line 8
Quoted 11 lines
arch/ppc/platforms/4xx/ppc440epx.c +8
-0@@ -0,0 +1,284 @@ +/* +* arch/ppc/platforms/4xx/ppc440epx.c +* +* PPC440EPx I/O descriptions +* +* Wade Farnsworth <[email protected]> +* Copyright 2004-2007 MontaVista Software Inc. +* Copyright 2006 AMCC
The same file in our repository looks like this:
/*
* arch/ppc/platforms/4xx/ppc440epx.c
*
* PPC440EPx I/O descriptions
*
* Copyright 2007 DENX Software Engineering, Stefan Roese <[email protected]> *
* Wade Farnsworth <[email protected]>
* Copyright 2004 MontaVista Software Inc.
* Copyright 2006 AMCC
In other words: You *removed* Stefan Roese's (resp. DENX) Copyright entry, and replaced it by one for MV?
I think this was not done by accident.
I don't know what to say.
I think your patches should be rejected.
Wolfgang Denk
Signature · 5 lines
DENX Software Engineering GmbH, HRB 165235 Munich, CEO: Wolfgang Denk Office: Kirchenstr. 5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [email protected] "If you own a machine, you are in turn owned by it, and spend your time serving it..." - Marion Zimmer Bradley, _The Forbidden Tower_
Quoted 27 lines · Wolfgang Denk
Quoted 4 lines
---
linux.orig/arch/ppc/platforms/4xx/ppc440epx.c1970-01-01
03:00:00.000000000 +0300 +++linux/arch/ppc/platforms/4xx/ppc440epx.c2007-03-20 14:43:37.000000000
+0300 @@ -0,0 +1,284 @@Quoted 8 lines
+/*
+ *arch/ppc/platforms/4xx/ppc440epx.c
+ *
+ * PPC440EPx I/O descriptions
+ *
+ * Wade Farnsworth <[email protected]>
+ * Copyright 2004-2007 MontaVista Software Inc.
+ * Copyright 2006 AMCCThe same file in our repository looks like this:
/*
*arch/ppc/platforms/4xx/ppc440epx.c
*
* PPC440EPx I/O descriptions
*
* Copyright 2007 DENX Software Engineering, Stefan Roese <[email protected]> *
* Wade Farnsworth <[email protected]>
* Copyright 2004 MontaVista Software Inc.
* Copyright 2006 AMCC
Quoted 2 lines
In other words: You *removed* Stefan Roese's (resp. DENX) Copyright entry, and replaced it by one for MV?
Just to make things clear:
The copyright in our version was added just a few days ago. So I think the Mvista code is based on an older version without the copyright.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, HRB 165235 Munich, CEO: Wolfgang Denk
Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
=====================================================================
Quoted 46 lines · Wolfgang Denk
Valentine,
Quoted 5 lines · in message <[email protected]> you wrote:
Add AMCC PPC440EPx/440GRx Sequoia/Rainier board support.
Signed-off-by Stefan Roese <[email protected]>Signed-off-by Valentine Barshak <[email protected]>Umm...
arch/ppc/platforms/4xx/ppc440epx.c line 8
Quoted 12 lines
arch/ppc/platforms/4xx/ppc440epx.c +8
-0@@ -0,0 +1,284 @@ +/* +* arch/ppc/platforms/4xx/ppc440epx.c +* +* PPC440EPx I/O descriptions +* +* Wade Farnsworth <[email protected]> +* Copyright 2004-2007 MontaVista Software Inc. +* Copyright 2006 AMCC The same file in our repository looks like this:
/*
*arch/ppc/platforms/4xx/ppc440epx.c
*
* PPC440EPx I/O descriptions
*
* Copyright 2007 DENX Software Engineering, Stefan Roese <[email protected]> *
* Wade Farnsworth <[email protected]>
* Copyright 2004 MontaVista Software Inc.
* Copyright 2006 AMCCIn other words: You *removed* Stefan Roese's (resp. DENX) Copyright entry, and replaced it by one for MV?
I think this was not done by accident.
Quoted 9 lines
I don't know what to say.
I think your patches should be rejected.
Wolfgang Denk
I'm sorry, but I did *not* remove any copyrights. I've got this file from AMCC with *no* DENX Software copyright. Please take a look at this link: http://www.amcc.com/Embedded/Downloads/download.html?item=365
You might have a later version in your repository.
Thanks.