reduce config complexity of intr.c
PATCH 1/1 reduce config complexity of intr.c
Here comes an attempt to clean up some of the mess that piled up in nucleus/intr.c over the time and specifically after our last hot-fixes.
First of all, I think we don't loose much when merging the two separate switches for level- and edge-triggered shared IRQs into a single one. That already beatifies some lines, kills conditional code, and removes one configuration decision the user has to make.
Then I reordered some code to avoid warnings for the non-shared non-SMP case AND to fix a probable compilation issue of the simulator (due to unknown ____cacheline_aligned_in_smp).
At this chance, a few redundant conditional lines in rtcan_*_pci.c drivers were removed as well.
Jan
--- include/nucleus/intr.h | 4 ksrc/drivers/can/sja1000/rtcan_ixxat_pci.c | 4 ksrc/drivers/can/sja1000/rtcan_peak_pci.c | 4 ksrc/nucleus/Config.in | 8 - ksrc/nucleus/Kconfig | 32 +--- ksrc/nucleus/intr.c | 213 ++++++++++++++--------------- 6 files changed, 116 insertions(+), 149 deletions(-)
include/nucleus/intr.h +2 -2
@@ -45,9 +45,9 @@ typedef struct xnintr { -#if defined(CONFIG_XENO_OPT_SHIRQ_LEVEL) || defined(CONFIG_XENO_OPT_SHIRQ_EDGE) +#ifdef CONFIG_XENO_OPT_SHIRQ struct xnintr *next; /* !< Next object in the IRQ-sharing chain. */ -#endif /* CONFIG_XENO_OPT_SHIRQ_LEVEL || CONFIG_XENO_OPT_SHIRQ_EDGE */ +#endif /* CONFIG_XENO_OPT_SHIRQ */ unsigned unhandled; /* !< Number of consequent unhandled interrupts */
ksrc/drivers/can/sja1000/rtcan_ixxat_pci.c +0 -4
@@ -176,11 +176,7 @@ static int rtcan_ixxat_pci_add_chan(struoutb (intcsr, board->conf_addr +IXXAT_INTCSR_OFFSET );/* Register and setup interrupt handling */ -#ifdef CONFIG_XENO_OPT_SHIRQ_LEVEL chip->irq_flags =RTDM_IRQTYPE_SHARED ; -#else - chip->irq_flags =0 ; -#endif chip->irq_num = pdev->irq; RTCAN_DBG("%s: base_addr=0x%p conf_addr=%#x irq=%d ocr=%#x cdr=%#x\n",
ksrc/drivers/can/sja1000/rtcan_peak_pci.c +0 -4
@@ -230,11 +230,7 @@ static int rtcan_peak_pci_add_chan(strucstrncpy (dev->name,RTCAN_DEV_NAME ,IFNAMSIZ );/* Register and setup interrupt handling */ -#ifdef CONFIG_XENO_OPT_SHIRQ_LEVEL chip->irq_flags =RTDM_IRQTYPE_SHARED ; -#else - chip->irq_flags =0 ; -#endif chip->irq_num = pdev->irq; pita_icr_high =readw (board->conf_addr +PITA_ICR +2 );if (channel ==CHANNEL_SLAVE ) {
ksrc/nucleus/Config.in +2 -6
@@ -36,6 +36,8 @@ if [ "$CONFIG_XENO_OPT_NUCLEUS" != "n" ] bool 'Watchdog support' CONFIG_XENO_OPT_WATCHDOG fi + bool 'Shared interrupts' CONFIG_XENO_OPT_SHIRQ + bool 'Enable periodic timing' CONFIG_XENO_OPT_TIMING_PERIODIC int 'Timer tuning latency (ns)' CONFIG_XENO_OPT_TIMING_TIMERLAT 0 int 'Scheduling latency (ns)' CONFIG_XENO_OPT_TIMING_SCHEDLAT 0
@@ -55,12 +57,6 @@ if [ "$CONFIG_XENO_OPT_NUCLEUS" != "n" ] fi endmenu - mainmenu_option next_comment - comment 'Shared interrupts' - bool 'Level-triggered interrupts' CONFIG_XENO_OPT_SHIRQ_LEVEL - bool 'Edge-triggered interrupts' CONFIG_XENO_OPT_SHIRQ_EDGE - endmenu - if [ "$CONFIG_LTT" != "n" ]; then mainmenu_option next_comment comment 'LTT tracepoints filtering'
ksrc/nucleus/Kconfig +9 -23
@@ -208,6 +208,15 @@ config XENO_OPT_WATCHDOG behalf of the timer tick handler, thus is only active after the timer has been started. +config XENO_OPT_SHIRQ + bool "Shared interrupts" + help + + Enables support for both level- and edge-triggered shared + interrupts, so that multiple real-time interrupt handlers + are allowed to control dedicated hardware devices which are + configured to share the same interrupt line. + menu "Timing" config XENO_OPT_TIMING_PERIODIC
@@ -319,29 +328,6 @@ config XENO_OPT_TIMER_WHEEL_STEP endmenu - -menu "Shared interrupts" - -config XENO_OPT_SHIRQ_LEVEL - bool "Level-triggered interrupts" - help - - Enables support for shared level-triggered interrupts, so that - multiple real-time interrupt handlers are allowed to control - dedicated hardware devices which are configured to share - the same interrupt channel. - -config XENO_OPT_SHIRQ_EDGE - bool "Edge-triggered interrupts" - help - - Enables support for shared edge-triggered interrupts, so that - multiple real-time interrupt handlers are allowed to control - dedicated hardware devices which are configured to share - the same interrupt channel. - -endmenu - menu "LTT tracepoints filtering" depends on LTT
ksrc/nucleus/intr.c +103 -110
315 lines not on this page · raw message
Quoted 4 lines · Jan Kiszka
...
Then I reordered some code to avoid warnings for the non-shared non-SMP case AND to fix a probable compilation issue of the simulator (due to unknown____cacheline_aligned_in_smp).
And this add-on patch is needed to make the simulator really build again.
Jan
--- include/asm-generic/system.h | 1 + include/asm-sim/system.h | 2 ++ ksrc/nucleus/intr.c | 10 +++++----- ksrc/nucleus/module.c | 4 ++-- 4 files changed, 10 insertions(+), 7 deletions(-)
include/asm-generic/system.h +1 -0
@@ -123,6 +123,7 @@ typedef struct { atomic_t owner; } xnloc#define XNARCH_NR_CPUS RTHAL_NR_CPUS +#define XNARCH_NR_IRQS RTHAL_NR_IRQS#define XNARCH_TIMER_IRQ RTHAL_TIMER_IRQ#define XNARCH_ROOT_STACKSZ 0/* Only a placeholder -- no stack */
include/asm-sim/system.h +2 -0
@@ -85,6 +85,8 @@ typedef unsigned long xnlock_t;#define XNARCH_NR_CPUS 1 +#define XNARCH_NR_IRQS 256 +/* Should be equal to the value used for creating the mvmtimer object (mvm_start_timer). */ #define XNARCH_TIMER_IRQ 1
ksrc/nucleus/intr.c +5 -5
@@ -141,7 +141,7 @@ typedef struct xnintr_irq { }____cacheline_aligned_in_smp xnintr_irq_t; -static xnintr_irq_t xnirqs[RTHAL_NR_IRQS ]; +static xnintr_irq_t xnirqs[XNARCH_NR_IRQS ];/* * Low-level interrupt handler dispatching the user-defined ISRs for
@@ -292,7 +292,7 @@ static inline int xnintr_irq_attach(xninxnintr_t *prev, **p = &shirq->handlers;int err; -if (intr->irq >=RTHAL_NR_IRQS ) +if (intr->irq >=XNARCH_NR_IRQS )return -EINVAL ;if (__testbits (intr->flags,XN_ISR_ATTACHED ))
@@ -346,7 +346,7 @@ static inline int xnintr_irq_detach(xninxnintr_t *e, **p = &shirq->handlers;int err =0 ; -if (intr->irq >=RTHAL_NR_IRQS ) +if (intr->irq >=XNARCH_NR_IRQS )return -EINVAL ;if (!__testbits (intr->flags,XN_ISR_ATTACHED ))
@@ -386,7 +386,7 @@ typedef struct xnintr_irq { } ____cacheline_aligned_in_smp xnintr_irq_t; -static xnintr_irq_t xnirqs[RTHAL_NR_IRQS ]; +static xnintr_irq_t xnirqs[XARCH_NR_IRQS ];#endif /* CONFIG_SMP */ static inline int xnintr_irq_attach (xnintr_t *intr)
@@ -477,7 +477,7 @@ static void xnintr_irq_handler(unsignedint xnintr_mount (void ) {int i; -for (i =0 ; i <RTHAL_NR_IRQS ; ++i) +for (i =0 ; i <XNARCH_NR_IRQS ; ++i)xnlock_init (&xnirqs[i].lock);return 0 ; }
ksrc/nucleus/module.c +2 -2
@@ -438,7 +438,7 @@ static int stat_seq_open(struct inode *i }/* Iterate over all IRQ numbers, ... */ -for (irq =0 ; irq <RTHAL_NR_IRQS ; irq++) { +for (irq =0 ; irq <XNARCH_NR_IRQS ; irq++) {xnintr_t *prev =NULL ;int cpu =0 ;int err;
@@ -865,7 +865,7 @@ static int irq_read_proc(char *page, p +=sprintf (p," CPU%d" , cpu); } -for (irq =0 ; irq <RTHAL_NR_IRQS ; irq++) { +for (irq =0 ; irq <XNARCH_NR_IRQS ; irq++) {if (rthal_irq_handler (&rthal_domain, irq) ==NULL )continue ;
Quoted 2 lines · Jan Kiszka
Here comes an attempt to clean up some of the mess that piled up in
nucleus/intr.cover the time and specifically after our last hot-fixes.
The first version contained a regression that oops'ed when dumping /proc/xenomai/stat. Here is -v2 without that bug + a few more micro-refactorings to kill #ifdefs:
http://www.rts.uni-hannover.de/rtaddon/patches/xenomai/xnintr-cleanups-v2.patch
Jan