S3C24XX large page NAND support
PATCH 1/1 S3C24XX large page NAND support
This adds support for using large page NAND devices with the S3C24XX NAND controllers. This also adds the file Documentation/arm/Samsung-S3C24XX/NAND.txt to describe the differences.
The basic stratergy is to maintain 3 bytes of ECC for each 256 byte block read from the NAND which is similar to the default kernel layout (altough we are using the hardware ECC generator to make our ECC calculations).
drivers/mtd/nand/s3c2410.c +33 -5
@@ -473,7 +473,7 @@ static int s3c2440_nand_calculate_ecc(st ecc_code[1 ] = ecc >>8 ; ecc_code[2 ] = ecc >>16 ; -pr_debug ("%s: returning ecc %06lx\n" , __func__, ecc); +pr_debug ("%s: returning ecc %06lx\n" , __func__, ecc &0xffffff );return 0 ; }
@@ -630,9 +630,6 @@ static void s3c2410_nand_init_chip(struc chip->ecc.calculate = s3c2410_nand_calculate_ecc; chip->ecc.correct = s3c2410_nand_correct_data; chip->ecc.mode =NAND_ECC_HW ; - chip->ecc.size =512 ; - chip->ecc.bytes =3 ; - chip->ecc.layout = &nand_hw_eccoob;switch (info->cpu_type) {case TYPE_S3C2410 :
@@ -656,6 +653,34 @@ static void s3c2410_nand_init_chip(struc } } +/* s3c2410_nand_update_chip +* +* post-probe chip update, to change any items, such as the +* layout for large page nand +*/ + +static void s3c2410_nand_update_chip (struct s3c2410_nand_info *info, +struct s3c2410_nand_mtd *nmtd) +{ +struct nand_chip *chip = &nmtd->chip; + +printk ("%s: chip %p: %d\n" , __func__, chip, chip->page_shift); + +if (hardware_ecc) { +/* change the behaviour depending on wether we are using +* the large or small page nand device */ + +if (chip->page_shift >10 ) { + chip->ecc.size =256 ; + chip->ecc.bytes =3 ; + }else { + chip->ecc.size =512 ; + chip->ecc.bytes =3 ; + chip->ecc.layout = &nand_hw_eccoob; + } + } +} +/* s3c2410_nand_probe * * called by device layer when it finds a device matching
@@ -762,9 +787,12 @@ static int s3c24xx_nand_probe(struct plas3c2410_nand_init_chip (info, nmtd, sets); - nmtd->scan_res =nand_scan (&nmtd->mtd, (sets) ? sets->nr_chips :1 ); + nmtd->scan_res =nand_scan_ident (&nmtd->mtd, + (sets) ? sets->nr_chips :1 );if (nmtd->scan_res ==0 ) { +s3c2410_nand_update_chip (info, nmtd); +nand_scan_tail (&nmtd->mtd);s3c2410_nand_add_partition (info, nmtd, sets); }
Documentation/arm/Samsung-S3C24XX/NAND.txt new file +30 -0
@@ -0,0 +1,30 @@ + S3C24XX NAND Support + ==================== + +Introduction +------------ + +Small Page NAND +--------------- + +The driver uses a 512 byte (1 page) ECC code for this setup. The +ECC code is not directly compatible with the default kernel ECC +code, so the driver enforces its own OOB layout and ECC parameters + +Large Page NAND +--------------- + +The driver is capable of handling NAND flash with a 2KiB page +size, with support for hardware ECC generation and correction. + +Unlike the 512byte page mode, the driver generates ECC data for +each 256 byte block in an 2KiB page. This means that more than +one error in a page can be rectified. It also means that the +OOB layout remains the default kernel layout for these flashes. + + +Document Author +--------------- + +Ben Dooks, Copyright 2007 Simtec Electronics +
Documentation/arm/Samsung-S3C24XX/Overview.txt +2 -0
@@ -156,6 +156,8 @@ NAND controller. If there are any problems the latest linux-mtd code can be found from http://www.linux-mtd.infradead.org/ + For more information see Documentation/arm/Samsung-S3C24XX/NAND.txt + Serial ------
Quoted 72 lines · Ben Dooks
This adds support for using large page NAND devices
with the S3C24XX NAND controllers. This also adds the fileDocumentation/arm/Samsung-S3C24XX/NAND.txtto describe the differences.The basic stratergy is to maintain 3 bytes of ECC for each 256 byte block read from the NAND which is similar to the default kernel layout (altough we are using the hardware ECC generator to make our ECC calculations).
Signed-off-by Ben Dooks <[email protected]>Index:
linux-2.6.21-tmp/drivers/mtd/nand/s3c2410.c
===================================================================drivers/mtd/nand/s3c2410.c +29
-4@@ -473,7 +473,7 @@ static int s3c2440_nand_calculate_ecc(st ecc_code[1 ] = ecc >>8 ; ecc_code[2 ] = ecc >>16 ; -pr_debug ("%s: returning ecc %06lx\n" , __func__, ecc); +pr_debug ("%s: returning ecc %06lx\n" , __func__, ecc &0xffffff );return 0 ; }@@ -630,9 +630,6 @@ static void s3c2410_nand_init_chip(struc chip->ecc.calculate = s3c2410_nand_calculate_ecc; chip->ecc.correct = s3c2410_nand_correct_data; chip->ecc.mode =NAND_ECC_HW ; - chip->ecc.size =512 ; - chip->ecc.bytes =3 ; - chip->ecc.layout = &nand_hw_eccoob;switch (info->cpu_type) {case TYPE_S3C2410 :@@ -656,6 +653,34 @@ static void s3c2410_nand_init_chip(struc } } +/* s3c2410_nand_update_chip +* +* post-probe chip update, to change any items, such as the +* layout for large page nand +*/ + +static void s3c2410_nand_update_chip (struct s3c2410_nand_info *info, +struct s3c2410_nand_mtd *nmtd) +{ +struct nand_chip *chip = &nmtd->chip; + +printk ("%s: chip %p: %d\n" , __func__, chip, chip->page_shift); + +if (hardware_ecc) { +/* change the behaviour depending on wether we are using +* the large or small page nand device */ + +if (chip->page_shift >10 ) { + chip->ecc.size =256 ; + chip->ecc.bytes =3 ; + }else { + chip->ecc.size =512 ; + chip->ecc.bytes =3 ; + chip->ecc.layout = &nand_hw_eccoob; + } + } +} +/* s3c2410_nand_probe * * called by device layer when it finds a device matching @@ -762,9 +787,12 @@ static int s3c24xx_nand_probe(struct plas3c2410_nand_init_chip (info, nmtd, sets);
drivers/mtd/nand/s3c2410.c static int s3c24xx_nand_probe(struct pla · line 797
Quoted 10 lines
drivers/mtd/nand/s3c2410.c +4
-1- nmtd->scan_res =nand_scan (&nmtd->mtd, (sets) ? sets->nr_chips :1 ); + nmtd->scan_res =nand_scan_ident (&nmtd->mtd, + (sets) ? sets->nr_chips :1 );if (nmtd->scan_res ==0 ) { +s3c2410_nand_update_chip (info, nmtd); +nand_scan_tail (&nmtd->mtd);s3c2410_nand_add_partition (info, nmtd, sets); }
Shouldn't nand_scan_ident and nand_scan_tail be used here ?
Matthieu
Quoted 13 lines · Matthieu CASTET
Quoted 12 lines · Ben Dooks
This adds support for using large page NAND devices with the S3C24XX NAND controllers. This also adds the file
Documentation/arm/Samsung-S3C24XX/NAND.txtto describe the differences.The basic stratergy is to maintain 3 bytes of ECC for each 256 byte block read from the NAND which is similar to the default kernel layout (altough we are using the hardware ECC generator to make our ECC calculations).
Signed-off-by Ben Dooks <[email protected]>
[snip]
Quoted 11 lines
drivers/mtd/nand/s3c2410.c static int s3c24xx_nand_probe(struct pla · line 797
Quoted 10 lines
drivers/mtd/nand/s3c2410.c +4
-1- nmtd->scan_res =nand_scan (&nmtd->mtd, (sets) ? sets->nr_chips :1 ); + nmtd->scan_res =nand_scan_ident (&nmtd->mtd, + (sets) ? sets->nr_chips :1 );if (nmtd->scan_res ==0 ) { +s3c2410_nand_update_chip (info, nmtd); +nand_scan_tail (&nmtd->mtd);s3c2410_nand_add_partition (info, nmtd, sets); }Shouldn't
nand_scan_identandnand_scan_tailbe used here ?
Sorry, do you mean that they should be used here (and they are being used in this code) or do you mean that you do not think that these two are to be used here?
Signature · 3 lines
Ben ([email protected], http://www.fluff.org/) 'a smiley only costs 4 bytes'
Hi Ben,
Quoted 14 lines · Ben Dooks
On Thu, Jul 12, 2007 at 12:04:03PM +0200, Matthieu CASTET wrote:
[snip]Quoted 11 lines
drivers/mtd/nand/s3c2410.c static int s3c24xx_nand_probe(struct pla · line 797
Quoted 10 lines
drivers/mtd/nand/s3c2410.c +4
-1- nmtd->scan_res =nand_scan (&nmtd->mtd, (sets) ? sets->nr_chips :1 ); + nmtd->scan_res =nand_scan_ident (&nmtd->mtd, + (sets) ? sets->nr_chips :1 );if (nmtd->scan_res ==0 ) { +s3c2410_nand_update_chip (info, nmtd); +nand_scan_tail (&nmtd->mtd);s3c2410_nand_add_partition (info, nmtd, sets); }Shouldn't
nand_scan_identandnand_scan_tailbe used here ?
Quoted 4 lines
Sorry, do you mean that they should be used here (and they are being used in this code) or do you mean that you do not think that these two are to be used here?
Sorry for the noise, I misread the patch and was thinking nand_scan was still used.
Again sorry.
Matthieu