s3c2410fb: remove lcdcon3 register from s3c2410fb_display

PATCH New Antonino A. Daplas 1 participant 1 message Aug 13, 2007

Subsystems (4)

Arm (32-bit) Arm sub-architectures Framebuffer layer Arm Samsung Exynos

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Antonino A. Daplas

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2007-08-13 12:47 UTC #0 lore raw

PATCH 10/22 s3c2410fb: remove lcdcon3 register from s3c2410fb_display

From: Krzysztof Helt <[email protected]>

This patch removes unused lcdcon3 register from the s3c2410fb_display structure.

Signed-off-by Krzysztof Helt <[email protected]>

Signed-off-by Antonino Daplas <[email protected]>

---

 arch/arm/mach-s3c2410/mach-amlm5900.c |   11 +--
 arch/arm/mach-s3c2410/mach-bast.c     |   99 +++++++++++------------------
 arch/arm/mach-s3c2410/mach-h1940.c    |   36 ++++-------
 arch/arm/mach-s3c2410/mach-qt2410.c   |  111 +++++++++++++--------------------
 arch/arm/mach-s3c2440/mach-rx3715.c   |   36 ++++-------
 arch/arm/mach-s3c2440/mach-smdk2440.c |   34 ++++------
 drivers/video/s3c2410fb.c             |   17 +++--
 include/asm-arm/arch-s3c2410/fb.h     |    5 +
 8 files changed, 142 insertions(+), 207 deletions(-)

arch/arm/mach-s3c2410/mach-amlm5900.c +4 -7

index e96b413..74801ce 100644
@@ -180,13 +180,10 @@ static struct s3c2410fb_display __initda
 	.left_margin	= 1 << (4 + 3),
 	.right_margin	= 8 << 3,
 
-	.regs		= {
-		.lcdcon1	= 0x00008225,
-		.lcdcon2	= 0x0027c000,
-		.lcdcon3	= 0x00182708,
-		.lcdcon4	= 0x00000002,
-		.lcdcon5	= 0x00000001,
-	}
+	.lcdcon1	= 0x00008225,
+	.lcdcon2	= 0x0027c000,
+	.lcdcon4	= 0x00000002,
+	.lcdcon5	= 0x00000001,
 };
 
 static struct s3c2410fb_mach_info __initdata amlm5900_fb_info = {

arch/arm/mach-s3c2410/mach-bast.c +36 ~~-63~~

153 lines not on this page · raw message

arch/arm/mach-s3c2410/mach-h1940.c +15 ~~-21~~

index 372caa2..52d7685 100644
@@ -134,27 +134,21 @@ static struct s3c2410_udc_mach_info h194
  * Set lcd on or off
  **/
 static struct s3c2410fb_display h1940_lcd __initdata = {
-	.regs={
-		.lcdcon1=	S3C2410_LCDCON1_TFT16BPP | \
-				S3C2410_LCDCON1_TFT | \
-				S3C2410_LCDCON1_CLKVAL(0x0C),
-
-		.lcdcon2=	S3C2410_LCDCON2_VBPD(7) | \
-				S3C2410_LCDCON2_LINEVAL(319) | \
-				S3C2410_LCDCON2_VFPD(6) | \
-				S3C2410_LCDCON2_VSPW(0),
-
-		.lcdcon3=	S3C2410_LCDCON3_HBPD(19) | \
-				S3C2410_LCDCON3_HOZVAL(239) | \
-				S3C2410_LCDCON3_HFPD(7),
-
-		.lcdcon4=	S3C2410_LCDCON4_MVAL(0) | \
-				S3C2410_LCDCON4_HSPW(3),
-
-		.lcdcon5=	S3C2410_LCDCON5_FRM565 | \
-				S3C2410_LCDCON5_INVVLINE | \
-				S3C2410_LCDCON5_HWSWP,
-	},
+	.lcdcon1=	S3C2410_LCDCON1_TFT16BPP | \
+			S3C2410_LCDCON1_TFT | \
+			S3C2410_LCDCON1_CLKVAL(0x0C),
+
+	.lcdcon2=	S3C2410_LCDCON2_VBPD(7) | \
+			S3C2410_LCDCON2_LINEVAL(319) | \
+			S3C2410_LCDCON2_VFPD(6) | \
+			S3C2410_LCDCON2_VSPW(0),
+
+	.lcdcon4=	S3C2410_LCDCON4_MVAL(0) | \
+			S3C2410_LCDCON4_HSPW(3),
+
+	.lcdcon5=	S3C2410_LCDCON5_FRM565 | \
+			S3C2410_LCDCON5_INVVLINE | \
+			S3C2410_LCDCON5_HWSWP,
 
 	.type =		S3C2410_LCDCON1_TFT,
 	.width =	240,

arch/arm/mach-s3c2410/mach-qt2410.c +45 ~~-66~~

135 lines not on this page · raw message

arch/arm/mach-s3c2440/mach-rx3715.c +15 ~~-21~~

index dab8e7b..3058272 100644
@@ -111,27 +111,21 @@ static struct s3c2410_uartcfg rx3715_uar
 /* framebuffer lcd controller information */
 
 static struct s3c2410fb_display rx3715_lcdcfg __initdata = {
-	.regs	= {
-		.lcdcon1 =	S3C2410_LCDCON1_TFT16BPP | \
-				S3C2410_LCDCON1_TFT | \
-				S3C2410_LCDCON1_CLKVAL(0x0C),
-
-		.lcdcon2 =	S3C2410_LCDCON2_VBPD(5) | \
-				S3C2410_LCDCON2_LINEVAL(319) | \
-				S3C2410_LCDCON2_VFPD(6) | \
-				S3C2410_LCDCON2_VSPW(2),
-
-		.lcdcon3 =	S3C2410_LCDCON3_HBPD(35) | \
-				S3C2410_LCDCON3_HOZVAL(239) | \
-				S3C2410_LCDCON3_HFPD(35),
-
-		.lcdcon4 =	S3C2410_LCDCON4_MVAL(0) | \
-				S3C2410_LCDCON4_HSPW(7),
-
-		.lcdcon5 =	S3C2410_LCDCON5_INVVLINE |
-				S3C2410_LCDCON5_FRM565 |
-				S3C2410_LCDCON5_HWSWP,
-	},
+	.lcdcon1 =	S3C2410_LCDCON1_TFT16BPP | \
+			S3C2410_LCDCON1_TFT | \
+			S3C2410_LCDCON1_CLKVAL(0x0C),
+
+	.lcdcon2 =	S3C2410_LCDCON2_VBPD(5) | \
+			S3C2410_LCDCON2_LINEVAL(319) | \
+			S3C2410_LCDCON2_VFPD(6) | \
+			S3C2410_LCDCON2_VSPW(2),
+
+	.lcdcon4 =	S3C2410_LCDCON4_MVAL(0) | \
+			S3C2410_LCDCON4_HSPW(7),
+
+	.lcdcon5 =	S3C2410_LCDCON5_INVVLINE |
+			S3C2410_LCDCON5_FRM565 |
+			S3C2410_LCDCON5_HWSWP,
 
 	.type		= S3C2410_LCDCON1_TFT,
 	.width		= 240,

arch/arm/mach-s3c2440/mach-smdk2440.c +14 ~~-20~~

index 5930f17..33b3644 100644
@@ -104,30 +104,24 @@ static struct s3c2410_uartcfg smdk2440_u
 /* LCD driver info */
 
 static struct s3c2410fb_display smdk2440_lcd_cfg __initdata = {
-	.regs	= {
 
-		.lcdcon1	= S3C2410_LCDCON1_TFT16BPP |
-				  S3C2410_LCDCON1_TFT |
-				  S3C2410_LCDCON1_CLKVAL(0x04),
+	.lcdcon1	= S3C2410_LCDCON1_TFT16BPP |
+			  S3C2410_LCDCON1_TFT |
+			  S3C2410_LCDCON1_CLKVAL(0x04),
 
-		.lcdcon2	= S3C2410_LCDCON2_VBPD(7) |
-				  S3C2410_LCDCON2_LINEVAL(319) |
-				  S3C2410_LCDCON2_VFPD(6) |
-				  S3C2410_LCDCON2_VSPW(3),
+	.lcdcon2	= S3C2410_LCDCON2_VBPD(7) |
+			  S3C2410_LCDCON2_LINEVAL(319) |
+			  S3C2410_LCDCON2_VFPD(6) |
+			  S3C2410_LCDCON2_VSPW(3),
 
-		.lcdcon3	= S3C2410_LCDCON3_HBPD(19) |
-				  S3C2410_LCDCON3_HOZVAL(239) |
-				  S3C2410_LCDCON3_HFPD(7),
+	.lcdcon4	= S3C2410_LCDCON4_MVAL(0) |
+			  S3C2410_LCDCON4_HSPW(3),
 
-		.lcdcon4	= S3C2410_LCDCON4_MVAL(0) |
-				  S3C2410_LCDCON4_HSPW(3),
-
-		.lcdcon5	= S3C2410_LCDCON5_FRM565 |
-				  S3C2410_LCDCON5_INVVLINE |
-				  S3C2410_LCDCON5_INVVFRAME |
-				  S3C2410_LCDCON5_PWREN |
-				  S3C2410_LCDCON5_HWSWP,
-	},
+	.lcdcon5	= S3C2410_LCDCON5_FRM565 |
+			  S3C2410_LCDCON5_INVVLINE |
+			  S3C2410_LCDCON5_INVVFRAME |
+			  S3C2410_LCDCON5_PWREN |
+			  S3C2410_LCDCON5_HWSWP,
 
 	.type		= S3C2410_LCDCON1_TFT16BPP,

drivers/video/s3c2410fb.c +9 -8

index 04e9d7a..27528ca 100644
@@ -245,7 +245,7 @@ static int s3c2410fb_check_var(struct fb
 
 	default:
 	case 16:
-		if (display->regs.lcdcon5 & S3C2410_LCDCON5_FRM565) {
+		if (display->lcdcon5 & S3C2410_LCDCON5_FRM565) {
 			/* 16 bpp, 565 format */
 			var->red.offset		= 11;
 			var->green.offset	= 5;

@@ -796,7 +796,6 @@ static int __init s3c2410fb_probe(struct
 	struct s3c2410fb_info *info;
 	struct s3c2410fb_display *display;
 	struct fb_info *fbinfo;
-	struct s3c2410fb_hw *mregs;
 	struct resource *res;
 	int ret;
 	int irq;

@@ -812,7 +811,6 @@ static int __init s3c2410fb_probe(struct
 	}
 
 	display = mach_info->displays + mach_info->default_display;
-	mregs = &display->regs;
 
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0) {

@@ -855,7 +853,10 @@ static int __init s3c2410fb_probe(struct
 
 	strcpy(fbinfo->fix.id, driver_name);
 
-	memcpy(&info->regs, &display->regs, sizeof(info->regs));
+	info->regs.lcdcon1 = display->lcdcon1;
+	info->regs.lcdcon2 = display->lcdcon2;
+	info->regs.lcdcon4 = display->lcdcon4;
+	info->regs.lcdcon5 = display->lcdcon5;
 
 	/* Stop the video and unset ENVID if set */
 	info->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;

@@ -892,14 +893,14 @@ static int __init s3c2410fb_probe(struct
 	fbinfo->var.right_margin    = display->right_margin;
 
 	fbinfo->var.upper_margin    =
-				S3C2410_LCDCON2_GET_VBPD(mregs->lcdcon2) + 1;
+				S3C2410_LCDCON2_GET_VBPD(display->lcdcon2) + 1;
 	fbinfo->var.lower_margin    =
-				S3C2410_LCDCON2_GET_VFPD(mregs->lcdcon2) + 1;
+				S3C2410_LCDCON2_GET_VFPD(display->lcdcon2) + 1;
 	fbinfo->var.vsync_len	    =
-				S3C2410_LCDCON2_GET_VSPW(mregs->lcdcon2) + 1;
+				S3C2410_LCDCON2_GET_VSPW(display->lcdcon2) + 1;
 
 	fbinfo->var.hsync_len	    =
-				S3C2410_LCDCON4_GET_HSPW(mregs->lcdcon4) + 1;
+				S3C2410_LCDCON4_GET_HSPW(display->lcdcon4) + 1;
 
 	fbinfo->var.red.offset      = 11;
 	fbinfo->var.green.offset    = 5;

include/asm-arm/arch-s3c2410/fb.h +4 -1

index a76585a..8a7fa1b 100644
@@ -44,7 +44,10 @@ struct s3c2410fb_display {
 	unsigned short vsync_len;	/* value in lines (TFT) or 0 (STN) */
 
 	/* lcd configuration registers */
-	struct s3c2410fb_hw  regs;
+	unsigned long	lcdcon1;
+	unsigned long	lcdcon2;
+	unsigned long	lcdcon4;
+	unsigned long	lcdcon5;
 };
 
 struct s3c2410fb_mach_info {

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