ppc32/8xx: Fix r3 trashing due to 8MB TLB page instantiation
PATCH 1/1 ppc32/8xx: Fix r3 trashing due to 8MB TLB page instantiation
Instantiation of 8MB pages on the TLB cache for the kernel static mapping trashes r3 register on !CONFIG_8xx_CPU6 configurations. This ensures r3 gets saved and restored.
This has been posted to linuxppc-embedded by Marcelo Tosatti <[email protected]>, but only an incomplete version of the patch has been applied in c51e078f82096a7d35ac8ec2416272e843a0e1c4. This patch adds the rest of the fix.
--- arch/ppc/kernel/head_8xx.S | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-)
This can be pulled from git://git.bocc.de/dbox2.git ppc-fixes
arch/ppc/kernel/head_8xx.S +0 -2
@@ -495,9 +495,7 @@ LoadLargeDTLB: lwz r11, 4(r0) lwz r12, 16(r0) -#ifdef CONFIG_8xx_CPU6 lwz r3, 8(r0) -#endif rfi /* This is the data TLB error on the MPC8xx. This could be due to
Please apply.
Quoted 15 lines · Jochen Friedrich
Instantiation of 8MB pages on the TLB cache for the kernel static mapping trashes r3 register on !CONFIG_8xx_CPU6 configurations. This ensures r3 gets saved and restored.
This has been posted to linuxppc-embedded by Marcelo Tosatti <[email protected]>, but only an incomplete version of the patch has been applied in
c51e078f82096a7d35ac8ec2416272e843a0e1c4. This patch adds the rest of the fix.Signed-off-by Jochen Friedrich <[email protected]>--- arch/ppc/kernel/head_8xx.S | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-)This can be pulled from
git://git.bocc.de/dbox2.gitppc-fixes
Quoted 20 lines · Jochen Friedrich
Instantiation of 8MB pages on the TLB cache for the kernel static mapping trashes r3 register on !CONFIG_8xx_CPU6 configurations. This ensures r3 gets saved and restored.
This has been posted to linuxppc-embedded by Marcelo Tosatti <[email protected]>, but only an incomplete version of the patch has been applied in
c51e078f82096a7d35ac8ec2416272e843a0e1c4. This patch adds the rest of the fix.Signed-off-by Jochen Friedrich <[email protected]>--- arch/ppc/kernel/head_8xx.S | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-)This can be pulled from
git://git.bocc.de/dbox2.gitppc-fixesarch/ppc/kernel/head_8xx.S +0
-0
arch/ppc/kernel/head_8xx.S LoadLargeDTLB: · line 501
Quoted 9 lines
arch/ppc/kernel/head_8xx.S +0
-2@@ -495,9 +495,7 @@ LoadLargeDTLB: lwz r11, 4(r0) lwz r12, 16(r0) -#ifdef CONFIG_8xx_CPU6 lwz r3, 8(r0) -#endif rfi /* This is the data TLB error on the MPC8xx. This could be due to
do we need this in arch/powerpc as well?
- k
Hi Kumar,
Quoted 1 line
do we need this in
arch/powerpcas well?
No. At least not until these patches are applied to powerpc, as well:
8f069b1a90bd97bf6d59a02ecabf0173d9175609 [PATCH] powerpc/8xx: Use 8MB D-TLB's for kernel static mapping faults 3ea4807de7b2c5c903380ba2c2e7150bee942f42 [PATCH] powerpc/8xx: last two 8MB D-TLB entries are incorrectly set c51e078f82096a7d35ac8ec2416272e843a0e1c4 [PATCH] ppc32/8xx: Fix r3 trashing due to 8MB TLB page instantiation
Thanks,
Jochen