bnx2x_hsi.h
Subsystems (2)
PATCH 4/8 bnx2x_hsi.h
bnx2x_hsi.h - machine generated hardware and microcode definitions
Signed-off-by Eliezer Tamir <[email protected]>
---drivers/net/bnx2x_hsi.h | 6991 +++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 6991 insertions(+), 0 deletions(-)
drivers/net/bnx2x_hsi.h new file +6991 -0
@@ -0,0 +1,6991 @@ +/* bnx2x_hsi.h: Broadcom Everest network driver. +* +* Copyright (c) 2007 Broadcom Corporation +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation. +* +*/ + +/* Machine generated - do not edit */ + +#define BRB1_REGISTERS_BRB1_INT_STS 0x11cUL +#define BRB1_REGISTERS_BRB1_INT_STS_CLR 0x120UL +#define BRB1_REGISTERS_BRB1_INT_STS_WR 0x124UL +#define BRB1_REGISTERS_FREE_LIST_PRS_CRDT 0x200UL +#define BRB1_REGISTERS_FREE_LIST_PRS_CRDT_SIZE 3 +#define BRB1_REGISTERS_LL_RAM 0x1000UL +#define BRB1_REGISTERS_LL_RAM_SIZE 512 +#define BRB1_REGISTERS_NUM_OF_FULL_BLOCKS 0x90UL +#define BRB1_REGISTERS_NUM_OF_FULL_CYCLES_0 0xc8UL +#define BRB1_REGISTERS_NUM_OF_FULL_CYCLES_1 0xccUL +#define BRB1_REGISTERS_NUM_OF_FULL_CYCLES_2 0xd0UL +#define BRB1_REGISTERS_NUM_OF_FULL_CYCLES_3 0xd4UL +#define BRB1_REGISTERS_NUM_OF_FULL_CYCLES_4 0xd8UL +#define BRB1_REGISTERS_NUM_OF_PAUSE_CYCLES_0 0xb8UL +#define BRB1_REGISTERS_NUM_OF_PAUSE_CYCLES_1 0xbcUL +#define BRB1_REGISTERS_NUM_OF_PAUSE_CYCLES_2 0xc0UL +#define BRB1_REGISTERS_NUM_OF_PAUSE_CYCLES_3 0xc4UL +#define BRB1_REGISTERS_PAUSE_HIGH_THRESHOLD_0 0x78UL +#define BRB1_REGISTERS_PAUSE_HIGH_THRESHOLD_1 0x7cUL +#define BRB1_REGISTERS_PAUSE_LOW_THRESHOLD_0 0x68UL +#define BRB1_REGISTERS_PAUSE_LOW_THRESHOLD_1 0x6cUL +#define BRB1_REGISTERS_SOFT_RESET 0xdcUL +#define CCM_REGISTERS_CAM_OCCUP 0x188UL +#define CCM_REGISTERS_CAM_OCCUP_ST 0x200UL +#define CCM_REGISTERS_CAM_OCCUP_ST_SIZE 1 +#define CCM_REGISTERS_CCM_CFC_IFEN 0x3cUL +#define CCM_REGISTERS_CCM_CQM_IFEN 0xcUL +#define CCM_REGISTERS_CCM_CQM_USE_Q 0xc0UL +#define CCM_REGISTERS_CCM_INT_STS 0x1d8UL +#define CCM_REGISTERS_CCM_INT_STS_CLR 0x1dcUL +#define CCM_REGISTERS_CCM_INT_STS_WR 0x1e0UL +#define CCM_REGISTERS_CCM_REG0_SZ 0xc4UL +#define CCM_REGISTERS_CCM_STORM0_IFEN 0x4UL +#define CCM_REGISTERS_CCM_STORM1_IFEN 0x8UL +#define CCM_REGISTERS_CDU_AG_RD_IFEN 0x30UL +#define CCM_REGISTERS_CDU_AG_WR_IFEN 0x2cUL +#define CCM_REGISTERS_CDU_SM_RD_IFEN 0x38UL +#define CCM_REGISTERS_CDU_SM_WR_IFEN 0x34UL +#define CCM_REGISTERS_CFC_INIT_CRD 0x204UL +#define CCM_REGISTERS_CFC_INIT_CRD_SIZE 1 +#define CCM_REGISTERS_CNT_AUX1_Q 0xc8UL +#define CCM_REGISTERS_CNT_AUX2_Q 0xccUL +#define CCM_REGISTERS_CP_WEIGHT 0xb0UL +#define CCM_REGISTERS_CQM_CCM_HDR_P 0x8cUL +#define CCM_REGISTERS_CQM_CCM_HDR_S 0x90UL +#define CCM_REGISTERS_CQM_CCM_IFEN 0x14UL +#define CCM_REGISTERS_CQM_INIT_CRD 0x20cUL +#define CCM_REGISTERS_CQM_INIT_CRD_SIZE 1 +#define CCM_REGISTERS_CQM_P_WEIGHT 0xb8UL +#define CCM_REGISTERS_CSDM_IFEN 0x18UL +#define CCM_REGISTERS_CSDM_LENGTH_MIS 0x170UL +#define CCM_REGISTERS_ERR_CCM_HDR 0x94UL +#define CCM_REGISTERS_ERR_EVNT_ID 0x98UL +#define CCM_REGISTERS_FIC0_INIT_CRD 0x210UL +#define CCM_REGISTERS_FIC0_INIT_CRD_SIZE 1 +#define CCM_REGISTERS_FIC1_INIT_CRD 0x214UL +#define CCM_REGISTERS_FIC1_INIT_CRD_SIZE 1 +#define CCM_REGISTERS_GR_ARB_TYPE 0x15cUL +#define CCM_REGISTERS_GR_LD0_PR 0x164UL +#define CCM_REGISTERS_GR_LD1_PR 0x168UL +#define CCM_REGISTERS_INV_DONE_Q 0x108UL +#define CCM_REGISTERS_N_SM_CTX_LD_0 0x4cUL +#define CCM_REGISTERS_N_SM_CTX_LD_1 0x50UL +#define CCM_REGISTERS_N_SM_CTX_LD_10 0x74UL +#define CCM_REGISTERS_N_SM_CTX_LD_11 0x78UL +#define CCM_REGISTERS_N_SM_CTX_LD_12 0x7cUL +#define CCM_REGISTERS_N_SM_CTX_LD_13 0x80UL +#define CCM_REGISTERS_N_SM_CTX_LD_14 0x84UL +#define CCM_REGISTERS_N_SM_CTX_LD_15 0x88UL +#define CCM_REGISTERS_N_SM_CTX_LD_2 0x54UL +#define CCM_REGISTERS_N_SM_CTX_LD_3 0x58UL +#define CCM_REGISTERS_N_SM_CTX_LD_4 0x5cUL +#define CCM_REGISTERS_N_SM_CTX_LD_5 0x60UL +#define CCM_REGISTERS_N_SM_CTX_LD_6 0x64UL +#define CCM_REGISTERS_N_SM_CTX_LD_7 0x68UL +#define CCM_REGISTERS_PBF_IFEN 0x28UL +#define CCM_REGISTERS_PBF_LENGTH_MIS 0x180UL +#define CCM_REGISTERS_PBF_WEIGHT 0xacUL +#define CCM_REGISTERS_PHYS_QNUM1_0 0x134UL +#define CCM_REGISTERS_PHYS_QNUM1_1 0x138UL +#define CCM_REGISTERS_PHYS_QNUM2_0 0x13cUL +#define CCM_REGISTERS_PHYS_QNUM2_1 0x140UL +#define CCM_REGISTERS_PHYS_QNUM3_0 0x144UL +#define CCM_REGISTERS_PHYS_QNUM3_1 0x148UL +#define CCM_REGISTERS_QOS_PHYS_QNUM0_0 0x114UL +#define CCM_REGISTERS_QOS_PHYS_QNUM0_1 0x118UL +#define CCM_REGISTERS_QOS_PHYS_QNUM1_0 0x11cUL +#define CCM_REGISTERS_QOS_PHYS_QNUM1_1 0x120UL +#define CCM_REGISTERS_QOS_PHYS_QNUM2_0 0x124UL +#define CCM_REGISTERS_QOS_PHYS_QNUM2_1 0x128UL +#define CCM_REGISTERS_QOS_PHYS_QNUM3_0 0x12cUL +#define CCM_REGISTERS_QOS_PHYS_QNUM3_1 0x130UL +#define CCM_REGISTERS_STORM_CCM_IFEN 0x10UL +#define CCM_REGISTERS_STORM_LENGTH_MIS 0x16cUL +#define CCM_REGISTERS_TSEM_IFEN 0x1cUL +#define CCM_REGISTERS_TSEM_LENGTH_MIS 0x174UL +#define CCM_REGISTERS_TSEM_WEIGHT 0xa0UL +#define CCM_REGISTERS_USEM_IFEN 0x24UL +#define CCM_REGISTERS_USEM_LENGTH_MIS 0x17cUL +#define CCM_REGISTERS_USEM_WEIGHT 0xa8UL +#define CCM_REGISTERS_XSEM_IFEN 0x20UL +#define CCM_REGISTERS_XSEM_LENGTH_MIS 0x178UL +#define CCM_REGISTERS_XSEM_WEIGHT 0xa4UL +#define CCM_REGISTERS_XX_DESCR_TABLE 0x300UL +#define CCM_REGISTERS_XX_DESCR_TABLE_SIZE 36 +#define CCM_REGISTERS_XX_INIT_CRD 0x220UL +#define CCM_REGISTERS_XX_INIT_CRD_SIZE 1 +#define CCM_REGISTERS_XX_MSG_NUM 0x224UL +#define CCM_REGISTERS_XX_MSG_NUM_SIZE 1 +#define CCM_REGISTERS_XX_OVFL_EVNT_ID 0x44UL +#define CCM_REGISTERS_XX_TABLE 0x280UL +#define CCM_REGISTERS_XX_TABLE_SIZE 18 +#define CDU_REGISTERS_CDU_CHK_MASK0 0x0UL +#define CDU_REGISTERS_CDU_CHK_MASK1 0x4UL +#define CDU_REGISTERS_CDU_CONTROL0 0x8UL +#define CDU_REGISTERS_CDU_GLOBAL_PARAMS 0x20UL +#define CDU_REGISTERS_CDU_INT_STS 0x30UL +#define CDU_REGISTERS_CDU_INT_STS_CLR 0x34UL +#define CDU_REGISTERS_CDU_INT_STS_WR 0x38UL +#define CDU_REGISTERS_ERROR_DATA 0x14UL +#define CDU_REGISTERS_L1TT 0x800UL +#define CDU_REGISTERS_L1TT_SIZE 512 +#define CDU_REGISTERS_MATT 0x100UL +#define CDU_REGISTERS_MATT_SIZE 64 +#define CFC_REGISTERS_AC_INIT_DONE 0x78UL +#define CFC_REGISTERS_ACTIVITY_COUNTER 0x400UL +#define CFC_REGISTERS_ACTIVITY_COUNTER_SIZE 256 +#define CFC_REGISTERS_ACTIVITY_COUNTER_SIZE 256 +#define CFC_REGISTERS_CAM_INIT_DONE 0x7cUL +#define CFC_REGISTERS_CFC_INT_STS 0xfcUL +#define CFC_REGISTERS_CFC_INT_STS_CLR 0x100UL +#define CFC_REGISTERS_CFC_INT_STS_WR 0x104UL +#define CFC_REGISTERS_CONTROL0 0x28UL +#define CFC_REGISTERS_DEBUG0 0x50UL +#define CFC_REGISTERS_DISABLE_ON_ERROR 0x44UL +#define CFC_REGISTERS_ERROR_VECTOR 0x3cUL +#define CFC_REGISTERS_INIT_REG 0x4cUL +#define CFC_REGISTERS_LCREQ_WEIGHTS 0x84UL +#define CFC_REGISTERS_LL_INIT_DONE 0x74UL +#define CFC_REGISTERS_NUM_LCIDS_ALLOC 0x20UL +#define CFC_REGISTERS_NUM_LCIDS_ARRIVING 0x4UL +#define CFC_REGISTERS_NUM_LCIDS_INSIDE 0x8UL +#define CFC_REGISTERS_NUM_LCIDS_LEAVING 0x18UL +#define CSDM_REGISTERS_AGG_INT_EVENT_0 0x38UL +#define CSDM_REGISTERS_AGG_INT_EVENT_1 0x3cUL +#define CSDM_REGISTERS_AGG_INT_EVENT_10 0x60UL +#define CSDM_REGISTERS_AGG_INT_EVENT_11 0x64UL +#define CSDM_REGISTERS_AGG_INT_EVENT_12 0x68UL +#define CSDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL +#define CSDM_REGISTERS_AGG_INT_EVENT_14 0x70UL +#define CSDM_REGISTERS_AGG_INT_EVENT_15 0x74UL +#define CSDM_REGISTERS_AGG_INT_EVENT_16 0x78UL +#define CSDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL +#define CSDM_REGISTERS_AGG_INT_EVENT_18 0x80UL +#define CSDM_REGISTERS_AGG_INT_EVENT_19 0x84UL +#define CSDM_REGISTERS_AGG_INT_EVENT_10 0x60UL +#define CSDM_REGISTERS_AGG_INT_EVENT_11 0x64UL +#define CSDM_REGISTERS_AGG_INT_EVENT_12 0x68UL +#define CSDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL +#define CSDM_REGISTERS_AGG_INT_EVENT_14 0x70UL +#define CSDM_REGISTERS_AGG_INT_EVENT_15 0x74UL +#define CSDM_REGISTERS_AGG_INT_EVENT_16 0x78UL +#define CSDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL +#define CSDM_REGISTERS_AGG_INT_EVENT_18 0x80UL +#define CSDM_REGISTERS_AGG_INT_EVENT_19 0x84UL +#define CSDM_REGISTERS_AGG_INT_EVENT_2 0x40UL +#define CSDM_REGISTERS_AGG_INT_EVENT_20 0x88UL +#define CSDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL +#define CSDM_REGISTERS_AGG_INT_EVENT_22 0x90UL +#define CSDM_REGISTERS_AGG_INT_EVENT_23 0x94UL +#define CSDM_REGISTERS_AGG_INT_EVENT_24 0x98UL +#define CSDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL +#define CSDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL +#define CSDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL +#define CSDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL +#define CSDM_REGISTERS_AGG_INT_EVENT_29 0xacUL +#define CSDM_REGISTERS_AGG_INT_EVENT_20 0x88UL +#define CSDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL +#define CSDM_REGISTERS_AGG_INT_EVENT_22 0x90UL +#define CSDM_REGISTERS_AGG_INT_EVENT_23 0x94UL +#define CSDM_REGISTERS_AGG_INT_EVENT_24 0x98UL +#define CSDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL +#define CSDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL +#define CSDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL +#define CSDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL +#define CSDM_REGISTERS_AGG_INT_EVENT_29 0xacUL +#define CSDM_REGISTERS_AGG_INT_EVENT_3 0x44UL +#define CSDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL +#define CSDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL +#define CSDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL +#define CSDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL +#define CSDM_REGISTERS_AGG_INT_EVENT_4 0x48UL +#define CSDM_REGISTERS_AGG_INT_EVENT_5 0x4cUL +#define CSDM_REGISTERS_AGG_INT_EVENT_6 0x50UL +#define CSDM_REGISTERS_AGG_INT_EVENT_7 0x54UL +#define CSDM_REGISTERS_AGG_INT_EVENT_8 0x58UL +#define CSDM_REGISTERS_AGG_INT_EVENT_9 0x5cUL +#define CSDM_REGISTERS_AGG_INT_FIC_0 0x138UL +#define CSDM_REGISTERS_AGG_INT_FIC_1 0x13cUL +#define CSDM_REGISTERS_AGG_INT_FIC_10 0x160UL +#define CSDM_REGISTERS_AGG_INT_FIC_11 0x164UL +#define CSDM_REGISTERS_AGG_INT_FIC_12 0x168UL +#define CSDM_REGISTERS_AGG_INT_FIC_13 0x16cUL +#define CSDM_REGISTERS_AGG_INT_FIC_14 0x170UL +#define CSDM_REGISTERS_AGG_INT_FIC_15 0x174UL +#define CSDM_REGISTERS_AGG_INT_FIC_16 0x178UL +#define CSDM_REGISTERS_AGG_INT_FIC_17 0x17cUL +#define CSDM_REGISTERS_AGG_INT_FIC_18 0x180UL +#define CSDM_REGISTERS_AGG_INT_FIC_19 0x184UL +#define CSDM_REGISTERS_AGG_INT_FIC_10 0x160UL +#define CSDM_REGISTERS_AGG_INT_FIC_11 0x164UL +#define CSDM_REGISTERS_AGG_INT_FIC_12 0x168UL +#define CSDM_REGISTERS_AGG_INT_FIC_13 0x16cUL +#define CSDM_REGISTERS_AGG_INT_FIC_14 0x170UL +#define CSDM_REGISTERS_AGG_INT_FIC_15 0x174UL +#define CSDM_REGISTERS_AGG_INT_FIC_16 0x178UL +#define CSDM_REGISTERS_AGG_INT_FIC_17 0x17cUL +#define CSDM_REGISTERS_AGG_INT_FIC_18 0x180UL +#define CSDM_REGISTERS_AGG_INT_FIC_19 0x184UL +#define CSDM_REGISTERS_AGG_INT_FIC_2 0x140UL +#define CSDM_REGISTERS_AGG_INT_FIC_20 0x188UL +#define CSDM_REGISTERS_AGG_INT_FIC_21 0x18cUL +#define CSDM_REGISTERS_AGG_INT_FIC_22 0x190UL +#define CSDM_REGISTERS_AGG_INT_FIC_23 0x194UL +#define CSDM_REGISTERS_AGG_INT_FIC_24 0x198UL +#define CSDM_REGISTERS_AGG_INT_FIC_25 0x19cUL +#define CSDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL +#define CSDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL +#define CSDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL +#define CSDM_REGISTERS_AGG_INT_FIC_29 0x1acUL +#define CSDM_REGISTERS_AGG_INT_FIC_20 0x188UL +#define CSDM_REGISTERS_AGG_INT_FIC_21 0x18cUL +#define CSDM_REGISTERS_AGG_INT_FIC_22 0x190UL +#define CSDM_REGISTERS_AGG_INT_FIC_23 0x194UL +#define CSDM_REGISTERS_AGG_INT_FIC_24 0x198UL +#define CSDM_REGISTERS_AGG_INT_FIC_25 0x19cUL +#define CSDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL +#define CSDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL +#define CSDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL +#define CSDM_REGISTERS_AGG_INT_FIC_29 0x1acUL +#define CSDM_REGISTERS_AGG_INT_FIC_3 0x144UL +#define CSDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL +#define CSDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL +#define CSDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL +#define CSDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL +#define CSDM_REGISTERS_AGG_INT_FIC_4 0x148UL +#define CSDM_REGISTERS_AGG_INT_FIC_5 0x14cUL +#define CSDM_REGISTERS_AGG_INT_FIC_6 0x150UL +#define CSDM_REGISTERS_AGG_INT_FIC_7 0x154UL +#define CSDM_REGISTERS_AGG_INT_FIC_8 0x158UL +#define CSDM_REGISTERS_AGG_INT_FIC_9 0x15cUL +#define CSDM_REGISTERS_AGG_INT_MODE_0 0x1b8UL +#define CSDM_REGISTERS_AGG_INT_MODE_1 0x1bcUL +#define CSDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL +#define CSDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL +#define CSDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL +#define CSDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL +#define CSDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL +#define CSDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL +#define CSDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL +#define CSDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL +#define CSDM_REGISTERS_AGG_INT_MODE_18 0x200UL +#define CSDM_REGISTERS_AGG_INT_MODE_19 0x204UL +#define CSDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL +#define CSDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL +#define CSDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL +#define CSDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL +#define CSDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL +#define CSDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL +#define CSDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL +#define CSDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL +#define CSDM_REGISTERS_AGG_INT_MODE_18 0x200UL +#define CSDM_REGISTERS_AGG_INT_MODE_19 0x204UL +#define CSDM_REGISTERS_AGG_INT_MODE_2 0x1c0UL +#define CSDM_REGISTERS_AGG_INT_MODE_20 0x208UL +#define CSDM_REGISTERS_AGG_INT_MODE_21 0x20cUL +#define CSDM_REGISTERS_AGG_INT_MODE_22 0x210UL +#define CSDM_REGISTERS_AGG_INT_MODE_23 0x214UL +#define CSDM_REGISTERS_AGG_INT_MODE_24 0x218UL +#define CSDM_REGISTERS_AGG_INT_MODE_25 0x21cUL +#define CSDM_REGISTERS_AGG_INT_MODE_26 0x220UL +#define CSDM_REGISTERS_AGG_INT_MODE_27 0x224UL +#define CSDM_REGISTERS_AGG_INT_MODE_28 0x228UL +#define CSDM_REGISTERS_AGG_INT_MODE_29 0x22cUL +#define CSDM_REGISTERS_AGG_INT_MODE_20 0x208UL +#define CSDM_REGISTERS_AGG_INT_MODE_21 0x20cUL +#define CSDM_REGISTERS_AGG_INT_MODE_22 0x210UL +#define CSDM_REGISTERS_AGG_INT_MODE_23 0x214UL +#define CSDM_REGISTERS_AGG_INT_MODE_24 0x218UL +#define CSDM_REGISTERS_AGG_INT_MODE_25 0x21cUL +#define CSDM_REGISTERS_AGG_INT_MODE_26 0x220UL +#define CSDM_REGISTERS_AGG_INT_MODE_27 0x224UL +#define CSDM_REGISTERS_AGG_INT_MODE_28 0x228UL +#define CSDM_REGISTERS_AGG_INT_MODE_29 0x22cUL +#define CSDM_REGISTERS_AGG_INT_MODE_3 0x1c4UL +#define CSDM_REGISTERS_AGG_INT_MODE_30 0x230UL +#define CSDM_REGISTERS_AGG_INT_MODE_31 0x234UL +#define CSDM_REGISTERS_AGG_INT_MODE_30 0x230UL +#define CSDM_REGISTERS_AGG_INT_MODE_31 0x234UL +#define CSDM_REGISTERS_AGG_INT_MODE_4 0x1c8UL +#define CSDM_REGISTERS_AGG_INT_MODE_5 0x1ccUL +#define CSDM_REGISTERS_AGG_INT_MODE_6 0x1d0UL +#define CSDM_REGISTERS_AGG_INT_MODE_7 0x1d4UL +#define CSDM_REGISTERS_AGG_INT_MODE_8 0x1d8UL +#define CSDM_REGISTERS_AGG_INT_MODE_9 0x1dcUL +#define CSDM_REGISTERS_AGG_INT_T_0 0xb8UL +#define CSDM_REGISTERS_AGG_INT_T_1 0xbcUL +#define CSDM_REGISTERS_AGG_INT_T_10 0xe0UL +#define CSDM_REGISTERS_AGG_INT_T_11 0xe4UL +#define CSDM_REGISTERS_AGG_INT_T_12 0xe8UL +#define CSDM_REGISTERS_AGG_INT_T_13 0xecUL +#define CSDM_REGISTERS_AGG_INT_T_14 0xf0UL +#define CSDM_REGISTERS_AGG_INT_T_15 0xf4UL +#define CSDM_REGISTERS_AGG_INT_T_16 0xf8UL +#define CSDM_REGISTERS_AGG_INT_T_17 0xfcUL +#define CSDM_REGISTERS_AGG_INT_T_18 0x100UL +#define CSDM_REGISTERS_AGG_INT_T_19 0x104UL +#define CSDM_REGISTERS_AGG_INT_T_10 0xe0UL +#define CSDM_REGISTERS_AGG_INT_T_11 0xe4UL +#define CSDM_REGISTERS_AGG_INT_T_12 0xe8UL +#define CSDM_REGISTERS_AGG_INT_T_13 0xecUL +#define CSDM_REGISTERS_AGG_INT_T_14 0xf0UL +#define CSDM_REGISTERS_AGG_INT_T_15 0xf4UL +#define CSDM_REGISTERS_AGG_INT_T_16 0xf8UL +#define CSDM_REGISTERS_AGG_INT_T_17 0xfcUL +#define CSDM_REGISTERS_AGG_INT_T_18 0x100UL +#define CSDM_REGISTERS_AGG_INT_T_19 0x104UL +#define CSDM_REGISTERS_AGG_INT_T_2 0xc0UL +#define CSDM_REGISTERS_AGG_INT_T_20 0x108UL +#define CSDM_REGISTERS_AGG_INT_T_21 0x10cUL +#define CSDM_REGISTERS_AGG_INT_T_22 0x110UL +#define CSDM_REGISTERS_AGG_INT_T_23 0x114UL +#define CSDM_REGISTERS_AGG_INT_T_24 0x118UL +#define CSDM_REGISTERS_AGG_INT_T_25 0x11cUL +#define CSDM_REGISTERS_AGG_INT_T_26 0x120UL +#define CSDM_REGISTERS_AGG_INT_T_27 0x124UL +#define CSDM_REGISTERS_AGG_INT_T_28 0x128UL +#define CSDM_REGISTERS_AGG_INT_T_29 0x12cUL +#define CSDM_REGISTERS_AGG_INT_T_20 0x108UL +#define CSDM_REGISTERS_AGG_INT_T_21 0x10cUL +#define CSDM_REGISTERS_AGG_INT_T_22 0x110UL +#define CSDM_REGISTERS_AGG_INT_T_23 0x114UL +#define CSDM_REGISTERS_AGG_INT_T_24 0x118UL +#define CSDM_REGISTERS_AGG_INT_T_25 0x11cUL +#define CSDM_REGISTERS_AGG_INT_T_26 0x120UL +#define CSDM_REGISTERS_AGG_INT_T_27 0x124UL +#define CSDM_REGISTERS_AGG_INT_T_28 0x128UL +#define CSDM_REGISTERS_AGG_INT_T_29 0x12cUL +#define CSDM_REGISTERS_AGG_INT_T_3 0xc4UL +#define CSDM_REGISTERS_AGG_INT_T_30 0x130UL +#define CSDM_REGISTERS_AGG_INT_T_31 0x134UL +#define CSDM_REGISTERS_AGG_INT_T_30 0x130UL +#define CSDM_REGISTERS_AGG_INT_T_31 0x134UL +#define CSDM_REGISTERS_AGG_INT_T_4 0xc8UL +#define CSDM_REGISTERS_AGG_INT_T_5 0xccUL +#define CSDM_REGISTERS_AGG_INT_T_6 0xd0UL +#define CSDM_REGISTERS_AGG_INT_T_7 0xd4UL +#define CSDM_REGISTERS_AGG_INT_T_8 0xd8UL +#define CSDM_REGISTERS_AGG_INT_T_9 0xdcUL +#define CSDM_REGISTERS_CFC_RSP_START_ADDR 0x8UL +#define CSDM_REGISTERS_CMP_COUNTER_MAX0 0x1cUL +#define CSDM_REGISTERS_CMP_COUNTER_MAX1 0x20UL +#define CSDM_REGISTERS_CMP_COUNTER_MAX2 0x24UL +#define CSDM_REGISTERS_CMP_COUNTER_MAX3 0x28UL +#define CSDM_REGISTERS_CMP_COUNTER_START_ADDR 0xcUL +#define CSDM_REGISTERS_ENABLE_IN1 0x238UL +#define CSDM_REGISTERS_ENABLE_IN2 0x23cUL +#define CSDM_REGISTERS_ENABLE_OUT1 0x240UL +#define CSDM_REGISTERS_ENABLE_OUT2 0x244UL +#define CSDM_REGISTERS_NUM_OF_ACK_AFTER_PLACE 0x27cUL +#define CSDM_REGISTERS_NUM_OF_PKT_END_MSG 0x274UL +#define CSDM_REGISTERS_NUM_OF_PXP_ASYNC_REQ 0x278UL +#define CSDM_REGISTERS_NUM_OF_Q0_CMD 0x248UL +#define CSDM_REGISTERS_NUM_OF_Q10_CMD 0x26cUL +#define CSDM_REGISTERS_NUM_OF_Q11_CMD 0x270UL +#define CSDM_REGISTERS_NUM_OF_Q1_CMD 0x24cUL +#define CSDM_REGISTERS_NUM_OF_Q3_CMD 0x250UL +#define CSDM_REGISTERS_NUM_OF_Q4_CMD 0x254UL +#define CSDM_REGISTERS_NUM_OF_Q5_CMD 0x258UL +#define CSDM_REGISTERS_NUM_OF_Q6_CMD 0x25cUL +#define CSDM_REGISTERS_NUM_OF_Q7_CMD 0x260UL +#define CSDM_REGISTERS_NUM_OF_Q8_CMD 0x264UL +#define CSDM_REGISTERS_NUM_OF_Q9_CMD 0x268UL +#define CSDM_REGISTERS_Q_COUNTER_START_ADDR 0x10UL +#define CSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY 0x548UL +#define CSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY_SIZE 1 +#define CSDM_REGISTERS_SYNC_PARSER_EMPTY 0x550UL +#define CSDM_REGISTERS_SYNC_PARSER_EMPTY_SIZE 1 +#define CSDM_REGISTERS_SYNC_SYNC_EMPTY 0x558UL +#define CSDM_REGISTERS_SYNC_SYNC_EMPTY_SIZE 1 +#define CSDM_REGISTERS_TIMER_TICK 0x0UL +#define CSEM_REGISTERS_ARB_CYCLE_SIZE 0x34UL +#define CSEM_REGISTERS_ARB_ELEMENT0 0x20UL +#define CSEM_REGISTERS_ARB_ELEMENT1 0x24UL +#define CSEM_REGISTERS_ARB_ELEMENT2 0x28UL +#define CSEM_REGISTERS_ARB_ELEMENT3 0x2cUL +#define CSEM_REGISTERS_ARB_ELEMENT4 0x30UL +#define CSEM_REGISTERS_ENABLE_IN 0xa4UL +#define CSEM_REGISTERS_ENABLE_OUT 0xa8UL +#define CSEM_REGISTERS_FAST_MEMORY 0x20000UL +#define CSEM_REGISTERS_FAST_MEMORY_SIZE 32768 +#define CSEM_REGISTERS_FIC0_DISABLE 0x224UL +#define CSEM_REGISTERS_FIC0_DISABLE_SIZE 1 +#define CSEM_REGISTERS_FIC1_DISABLE 0x234UL +#define CSEM_REGISTERS_FIC1_DISABLE_SIZE 1 +#define CSEM_REGISTERS_INT_TABLE_TM 0xd4UL +#define CSEM_REGISTERS_INT_TABLE 0x400UL +#define CSEM_REGISTERS_INT_TABLE_SIZE 256 +#define CSEM_REGISTERS_MSG_NUM_FIC0 0x0UL +#define CSEM_REGISTERS_MSG_NUM_FIC1 0x4UL +#define CSEM_REGISTERS_MSG_NUM_FOC0 0x8UL +#define CSEM_REGISTERS_MSG_NUM_FOC1 0xcUL +#define CSEM_REGISTERS_MSG_NUM_FOC2 0x10UL +#define CSEM_REGISTERS_MSG_NUM_FOC3 0x14UL +#define CSEM_REGISTERS_PAS_DISABLE 0x24cUL +#define CSEM_REGISTERS_PAS_DISABLE_SIZE 1 +#define CSEM_REGISTERS_PASSIVE_BUFFER 0x2000UL +#define CSEM_REGISTERS_PASSIVE_BUFFER_SIZE 2048 +#define CSEM_REGISTERS_PRAM 0x40000UL +#define CSEM_REGISTERS_PRAM_SIZE 65536 +#define CSEM_REGISTERS_SLEEP_THREADS_VALID 0x26cUL +#define CSEM_REGISTERS_SLEEP_THREADS_VALID_SIZE 1 +#define CSEM_REGISTERS_SLOW_EXT_STORE_EMPTY 0x2a0UL +#define CSEM_REGISTERS_SLOW_EXT_STORE_EMPTY_SIZE 1 +#define CSEM_REGISTERS_THREADS_LIST 0x2e4UL +#define CSEM_REGISTERS_THREADS_LIST_SIZE 1 +#define CSEM_REGISTERS_TS_0_AS 0x38UL +#define CSEM_REGISTERS_TS_10_AS 0x60UL +#define CSEM_REGISTERS_TS_11_AS 0x64UL +#define CSEM_REGISTERS_TS_12_AS 0x68UL +#define CSEM_REGISTERS_TS_13_AS 0x6cUL +#define CSEM_REGISTERS_TS_14_AS 0x70UL +#define CSEM_REGISTERS_TS_15_AS 0x74UL +#define CSEM_REGISTERS_TS_16_AS 0x78UL +#define CSEM_REGISTERS_TS_17_AS 0x7cUL +#define CSEM_REGISTERS_TS_18_AS 0x80UL +#define CSEM_REGISTERS_TS_19_AS 0x84UL +#define CSEM_REGISTERS_TS_1_AS 0x3cUL +#define CSEM_REGISTERS_TS_2_AS 0x40UL +#define CSEM_REGISTERS_TS_3_AS 0x44UL +#define CSEM_REGISTERS_TS_4_AS 0x48UL +#define CSEM_REGISTERS_TS_5_AS 0x4cUL +#define CSEM_REGISTERS_TS_6_AS 0x50UL +#define CSEM_REGISTERS_TS_7_AS 0x54UL +#define CSEM_REGISTERS_TS_8_AS 0x58UL +#define CSEM_REGISTERS_TS_9_AS 0x5cUL +#define DMAE_REGISTERS_CMD_MEM 0x400UL +#define DMAE_REGISTERS_CMD_MEM_SIZE 224 +#define DMAE_REGISTERS_CRC16C_INIT 0x1cUL +#define DMAE_REGISTERS_CRC16T10_INIT 0x20UL +#define DMAE_REGISTERS_GO_C0 0x80UL +#define DMAE_REGISTERS_GO_C0_SIZE 1 +#define DMAE_REGISTERS_GO_C1 0x84UL +#define DMAE_REGISTERS_GO_C1_SIZE 1 +#define DMAE_REGISTERS_GO_C10 0x88UL +#define DMAE_REGISTERS_GO_C10_SIZE 1 +#define DMAE_REGISTERS_GO_C11 0x8cUL +#define DMAE_REGISTERS_GO_C11_SIZE 1 +#define DMAE_REGISTERS_GO_C12 0x90UL +#define DMAE_REGISTERS_GO_C12_SIZE 1 +#define DMAE_REGISTERS_GO_C13 0x94UL +#define DMAE_REGISTERS_GO_C13_SIZE 1 +#define DMAE_REGISTERS_GO_C14 0x98UL +#define DMAE_REGISTERS_GO_C14_SIZE 1 +#define DMAE_REGISTERS_GO_C15 0x9cUL +#define DMAE_REGISTERS_GO_C15_SIZE 1 +#define DMAE_REGISTERS_GO_C10 0x88UL +#define DMAE_REGISTERS_GO_C10_SIZE 1 +#define DMAE_REGISTERS_GO_C11 0x8cUL +#define DMAE_REGISTERS_GO_C11_SIZE 1 +#define DMAE_REGISTERS_GO_C12 0x90UL +#define DMAE_REGISTERS_GO_C12_SIZE 1 +#define DMAE_REGISTERS_GO_C13 0x94UL +#define DMAE_REGISTERS_GO_C13_SIZE 1 +#define DMAE_REGISTERS_GO_C14 0x98UL +#define DMAE_REGISTERS_GO_C14_SIZE 1 +#define DMAE_REGISTERS_GO_C15 0x9cUL +#define DMAE_REGISTERS_GO_C15_SIZE 1 +#define DMAE_REGISTERS_GO_C2 0xa0UL +#define DMAE_REGISTERS_GO_C2_SIZE 1 +#define DMAE_REGISTERS_GO_C3 0xa4UL +#define DMAE_REGISTERS_GO_C3_SIZE 1 +#define DMAE_REGISTERS_GO_C4 0xa8UL +#define DMAE_REGISTERS_GO_C4_SIZE 1 +#define DMAE_REGISTERS_GO_C5 0xacUL +#define DMAE_REGISTERS_GO_C5_SIZE 1 +#define DMAE_REGISTERS_GO_C6 0xb0UL +#define DMAE_REGISTERS_GO_C6_SIZE 1 +#define DMAE_REGISTERS_GO_C7 0xb4UL +#define DMAE_REGISTERS_GO_C7_SIZE 1 +#define DMAE_REGISTERS_GO_C8 0xb8UL +#define DMAE_REGISTERS_GO_C8_SIZE 1 +#define DMAE_REGISTERS_GO_C9 0xbcUL +#define DMAE_REGISTERS_GO_C9_SIZE 1 +#define DMAE_REGISTERS_GRC_IFEN 0x8UL +#define DMAE_REGISTERS_PCI_IFEN 0x4UL +#define DMAE_REGISTERS_PXP_REQ_INIT_CRD 0xc0UL +#define DMAE_REGISTERS_PXP_REQ_INIT_CRD_SIZE 1 +#define DORQ_REGISTERS_AGG_CMD0 0x60UL +#define DORQ_REGISTERS_AGG_CMD1 0x64UL +#define DORQ_REGISTERS_AGG_CMD2 0x68UL +#define DORQ_REGISTERS_AGG_CMD3 0x6cUL +#define DORQ_REGISTERS_CMHEAD_RX 0x50UL +#define DORQ_REGISTERS_DORQ_INT_MASK 0x180UL +#define DORQ_REGISTERS_DORQ_INT_STS 0x174UL +#define DORQ_REGISTERS_DORQ_INT_STS_CLR 0x178UL +#define DORQ_REGISTERS_DORQ_INT_STS_WR 0x17cUL +#define DORQ_REGISTERS_DORQ_INT_STS_CLR 0x178UL +#define DORQ_REGISTERS_DPM_CID_ADDR 0x44UL +#define DORQ_REGISTERS_DPM_CID_OFST 0x30UL +#define DORQ_REGISTERS_DQ_FIFO_AFULL_TH 0x7cUL +#define DORQ_REGISTERS_DQ_FIFO_FULL_TH 0x78UL +#define DORQ_REGISTERS_DQ_FILL_LVLF 0xa4UL +#define DORQ_REGISTERS_DQ_FULL_ST 0xc0UL +#define DORQ_REGISTERS_ERR_CMHEAD 0x58UL +#define DORQ_REGISTERS_IF_EN 0x4UL +#define DORQ_REGISTERS_MODE_ACT 0x8UL +#define DORQ_REGISTERS_NORM_CID_OFST 0x2cUL +#define DORQ_REGISTERS_NORM_CMHEAD_TX 0x4cUL +#define DORQ_REGISTERS_OUTST_REQ 0x3cUL +#define DORQ_REGISTERS_OUTST_REQ_CNT 0xa8UL +#define DORQ_REGISTERS_REGN 0x38UL +#define DORQ_REGISTERS_RSPA_CRD_CNT 0xacUL +#define DORQ_REGISTERS_RSP_INIT_CRD 0x48UL +#define DORQ_REGISTERS_SHRT_ACT_CNT 0x70UL +#define DORQ_REGISTERS_SHRT_CMHEAD 0x54UL +#define HC_CONFIG_0_REGISTERS_ATTN_BIT_EN_0 (0x1<<4) +#define HC_CONFIG_0_REGISTERS_ATTN_BIT_EN_0_SIZE 4 +#define HC_CONFIG_0_REGISTERS_INT_LINE_EN_0 (0x1<<3) +#define HC_CONFIG_0_REGISTERS_INT_LINE_EN_0_SIZE 3 +#define HC_CONFIG_0_REGISTERS_MSI_MSIX_INT_EN_0 (0x1<<2) +#define HC_CONFIG_0_REGISTERS_MSI_MSIX_INT_EN_0_SIZE 2 +#define HC_CONFIG_0_REGISTERS_SINGLE_ISR_EN_0 (0x1<<1) +#define HC_CONFIG_0_REGISTERS_SINGLE_ISR_EN_0_SIZE 1 +#define HC_REGISTERS_AGG_INT_0 0x50UL +#define HC_REGISTERS_AGG_INT_1 0x54UL +#define HC_REGISTERS_ATTN_BIT 0x120UL +#define HC_REGISTERS_ATTN_BIT_SIZE 4 +#define HC_REGISTERS_ATTN_IDX 0x100UL +#define HC_REGISTERS_ATTN_IDX_SIZE 2 +#define HC_REGISTERS_ATTN_MSG0_ADDR_L 0x18UL +#define HC_REGISTERS_ATTN_MSG1_ADDR_L 0x20UL +#define HC_REGISTERS_ATTN_NUM_P0 0x38UL +#define HC_REGISTERS_ATTN_NUM_P1 0x3cUL +#define HC_REGISTERS_CONFIG_0 0x0UL +#define HC_REGISTERS_CONFIG_1 0x4UL +#define HC_REGISTERS_CSTORM_ADDR_FOR_COALESCE 0x6cUL +#define HC_REGISTERS_INT_MASK 0x108UL +#define HC_REGISTERS_INT_MASK_SIZE 2 +#define HC_REGISTERS_LEADING_EDGE_0 0x40UL +#define HC_REGISTERS_LEADING_EDGE_1 0x48UL +#define HC_REGISTERS_P0_PROD_CONS 0x200UL +#define HC_REGISTERS_P0_PROD_CONS_SIZE 74 +#define HC_REGISTERS_P1_PROD_CONS 0x400UL +#define HC_REGISTERS_P1_PROD_CONS_SIZE 74 +#define HC_REGISTERS_PBA_COMMAND 0x140UL +#define HC_REGISTERS_PBA_COMMAND_SIZE 4 +#define HC_REGISTERS_PCI_CONFIG_0 0x10UL +#define HC_REGISTERS_PCI_CONFIG_1 0x14UL +#define HC_REGISTERS_STATISTIC_COUNTERS 0x1000UL +#define HC_REGISTERS_STATISTIC_COUNTERS_SIZE 516 +#define HC_REGISTERS_TRAILING_EDGE_0 0x44UL +#define HC_REGISTERS_TRAILING_EDGE_1 0x4cUL +#define HC_REGISTERS_TSTORM_ADDR_FOR_COALESCE 0x74UL +#define HC_REGISTERS_UC_RAM_ADDR_0 0x28UL +#define HC_REGISTERS_UC_RAM_ADDR_1 0x30UL +#define HC_REGISTERS_USTORM_ADDR_FOR_COALESCE 0x68UL +#define HC_REGISTERS_VQID_0 0x8UL +#define HC_REGISTERS_VQID_1 0xcUL +#define HC_REGISTERS_XSTORM_ADDR_FOR_COALESCE 0x70UL +#define HC_REGISTERS_XT_RAM_ADDR_0 0x2cUL +#define HC_REGISTERS_XT_RAM_ADDR_1 0x34UL +#define MISC_REGISTERS_AEU_AFTER_INVERT_1_FUNC_0 0x42cUL +#define MISC_REGISTERS_AEU_AFTER_INVERT_1_FUNC_0_SIZE 1 +#define MISC_REGISTERS_AEU_AFTER_INVERT_1_FUNC_1 0x430UL +#define MISC_REGISTERS_AEU_AFTER_INVERT_1_FUNC_1_SIZE 1 +#define MISC_REGISTERS_AEU_AFTER_INVERT_1_MCP 0x434UL +#define MISC_REGISTERS_AEU_AFTER_INVERT_1_MCP_SIZE 1 +#define MISC_REGISTERS_AEU_AFTER_INVERT_2_FUNC_0 0x438UL +#define MISC_REGISTERS_AEU_AFTER_INVERT_2_FUNC_0_SIZE 1 +#define MISC_REGISTERS_AEU_AFTER_INVERT_2_FUNC_1 0x43cUL +#define MISC_REGISTERS_AEU_AFTER_INVERT_2_FUNC_1_SIZE 1 +#define MISC_REGISTERS_AEU_AFTER_INVERT_2_MCP 0x440UL +#define MISC_REGISTERS_AEU_AFTER_INVERT_2_MCP_SIZE 1 +#define MISC_REGISTERS_AEU_AFTER_INVERT_3_FUNC_0 0x444UL +#define MISC_REGISTERS_AEU_AFTER_INVERT_3_FUNC_0_SIZE 1 +#define MISC_REGISTERS_AEU_AFTER_INVERT_3_FUNC_1 0x448UL +#define MISC_REGISTERS_AEU_AFTER_INVERT_3_FUNC_1_SIZE 1 +#define MISC_REGISTERS_AEU_AFTER_INVERT_3_MCP 0x44cUL +#define MISC_REGISTERS_AEU_AFTER_INVERT_3_MCP_SIZE 1 +#define MISC_REGISTERS_AEU_AFTER_INVERT_4_FUNC_0 0x450UL +#define MISC_REGISTERS_AEU_AFTER_INVERT_4_FUNC_0_SIZE 1 +#define MISC_REGISTERS_AEU_AFTER_INVERT_4_FUNC_1 0x454UL +#define MISC_REGISTERS_AEU_AFTER_INVERT_4_FUNC_1_SIZE 1 +#define MISC_REGISTERS_AEU_AFTER_INVERT_4_MCP 0x458UL +#define MISC_REGISTERS_AEU_AFTER_INVERT_4_MCP_SIZE 1 +#define MISC_REGISTERS_AEU_CLR_LATCH_SIGNAL 0x45cUL +#define MISC_REGISTERS_AEU_CLR_LATCH_SIGNAL_SIZE 1 +#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_0 0x6cUL +#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_1 0x7cUL +#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_2 0x8cUL +#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_3 0x9cUL +#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_4 0xacUL +#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_5 0xbcUL +#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_6 0xccUL +#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_7 0xdcUL +#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_0 0x10cUL +#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_1 0x11cUL +#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_2 0x12cUL +#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_3 0x13cUL +#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_4 0x14cUL +#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_5 0x15cUL +#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_6 0x16cUL +#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_7 0x17cUL +#define MISC_REGISTERS_AEU_ENABLE1_NIG_0 0xecUL +#define MISC_REGISTERS_AEU_ENABLE1_NIG_1 0x18cUL +#define MISC_REGISTERS_AEU_ENABLE1_PXP_0 0xfcUL +#define MISC_REGISTERS_AEU_ENABLE1_PXP_1 0x19cUL +#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_0 0x70UL +#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_1 0x80UL +#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_2 0x90UL +#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_3 0xa0UL +#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_4 0xb0UL +#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_5 0xc0UL +#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_6 0xd0UL +#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_7 0xe0UL +#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_0 0x110UL +#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_1 0x120UL +#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_2 0x130UL +#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_3 0x140UL +#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_4 0x150UL +#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_5 0x160UL +#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_6 0x170UL +#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_7 0x180UL +#define MISC_REGISTERS_AEU_ENABLE2_NIG_0 0xf0UL +#define MISC_REGISTERS_AEU_ENABLE2_NIG_1 0x190UL +#define MISC_REGISTERS_AEU_ENABLE2_PXP_0 0x100UL +#define MISC_REGISTERS_AEU_ENABLE2_PXP_1 0x1a0UL +#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_0 0x74UL +#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_1 0x84UL +#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_2 0x94UL +#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_3 0xa4UL +#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_4 0xb4UL +#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_5 0xc4UL +#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_6 0xd4UL +#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_7 0xe4UL +#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_0 0x114UL +#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_1 0x124UL +#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_2 0x134UL +#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_3 0x144UL +#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_4 0x154UL +#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_5 0x164UL +#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_6 0x174UL +#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_7 0x184UL +#define MISC_REGISTERS_AEU_ENABLE3_NIG_0 0xf4UL +#define MISC_REGISTERS_AEU_ENABLE3_NIG_1 0x194UL +#define MISC_REGISTERS_AEU_ENABLE3_PXP_0 0x104UL +#define MISC_REGISTERS_AEU_ENABLE3_PXP_1 0x1a4UL +#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_0 0x78UL +#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_1 0x88UL +#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_2 0x98UL +#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_3 0xa8UL +#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_4 0xb8UL +#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_5 0xc8UL +#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_6 0xd8UL +#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_7 0xe8UL +#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_0 0x118UL +#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_1 0x128UL +#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_2 0x138UL +#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_3 0x148UL +#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_4 0x158UL +#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_5 0x168UL +#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_6 0x178UL +#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_7 0x188UL +#define MISC_REGISTERS_AEU_ENABLE4_NIG_0 0xf8UL +#define MISC_REGISTERS_AEU_ENABLE4_NIG_1 0x198UL +#define MISC_REGISTERS_AEU_ENABLE4_PXP_0 0x108UL +#define MISC_REGISTERS_AEU_ENABLE4_PXP_1 0x1a8UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_0 0x0UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_1 0x4UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_10 0x28UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_11 0x2cUL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_12 0x30UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_13 0x34UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_14 0x38UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_15 0x3cUL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_16 0x40UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_17 0x44UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_18 0x48UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_19 0x4cUL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_10 0x28UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_11 0x2cUL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_12 0x30UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_13 0x34UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_14 0x38UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_15 0x3cUL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_16 0x40UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_17 0x44UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_18 0x48UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_19 0x4cUL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_2 0x8UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_20 0x50UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_21 0x54UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_20 0x50UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_21 0x54UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_3 0xcUL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_4 0x10UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_5 0x14UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_6 0x18UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_7 0x1cUL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_8 0x20UL +#define MISC_REGISTERS_AEU_GENERAL_ATTN_9 0x24UL +#define MISC_REGISTERS_AEU_INVERTER_1_FUNC_0 0x22cUL +#define MISC_REGISTERS_AEU_INVERTER_1_FUNC_1 0x23cUL +#define MISC_REGISTERS_AEU_INVERTER_2_FUNC_0 0x230UL +#define MISC_REGISTERS_AEU_INVERTER_2_FUNC_1 0x240UL +#define MISC_REGISTERS_AEU_INVERTER_3_FUNC_0 0x234UL +#define MISC_REGISTERS_AEU_INVERTER_3_FUNC_1 0x244UL +#define MISC_REGISTERS_AEU_INVERTER_4_FUNC_0 0x238UL +#define MISC_REGISTERS_AEU_INVERTER_4_FUNC_1 0x248UL +#define MISC_REGISTERS_AEU_MASK_ATTN_FUNC_0 0x60UL +#define MISC_REGISTERS_AEU_MASK_ATTN_FUNC_1 0x64UL +#define MISC_REGISTERS_BOND_ID 0x400UL +#define MISC_REGISTERS_BOND_ID_SIZE 1 +#define MISC_REGISTERS_CHIP_METAL 0x404UL +#define MISC_REGISTERS_CHIP_METAL_SIZE 1 +#define MISC_REGISTERS_CHIP_NUM 0x408UL +#define MISC_REGISTERS_CHIP_NUM_SIZE 1 +#define MISC_REGISTERS_CHIP_REV 0x40cUL +#define MISC_REGISTERS_CHIP_REV_SIZE 1 +#define MISC_REGISTERS_GRC_TIMEOUT_EN 0x280UL +#define MISC_REGISTERS_LCPLL_CTRL_1 0x2a4UL +#define MISC_REGISTERS_LCPLL_CTRL_REG_2 0x2a8UL +#define MISC_REGISTERS_PLL_STORM_CTRL_1 0x294UL +#define MISC_REGISTERS_PLL_STORM_CTRL_2 0x298UL +#define MISC_REGISTERS_PLL_STORM_CTRL_3 0x29cUL +#define MISC_REGISTERS_PLL_STORM_CTRL_4 0x2a0UL +#define MISC_REGISTERS_RESET_REG_1 0x580UL +#define MISC_REGISTERS_RESET_REG_1_SIZE 3 +#define MISC_REGISTERS_RESET_REG_2 0x590UL +#define MISC_REGISTERS_RESET_REG_2_SIZE 3 +#define MISC_REGISTERS_RESET_REG_3 0x5a0UL +#define MISC_REGISTERS_RESET_REG_3_SIZE 3 +#define MISC_REGISTERS_RESET_REG_1 0x580UL +#define MISC_REGISTERS_RESET_REG_1_SIZE 3 +#define MISC_REGISTERS_RESET_REG_2 0x590UL +#define MISC_REGISTERS_RESET_REG_2_SIZE 3 +#define MISC_REGISTERS_SHARED_MEM_ADDR 0x2b4UL +#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_EMAC0_MISC_MI_INT (0x1<<0) +#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_EMAC0_MISC_MI_INT_SIZE 0 +#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_SERDES0_LINK_STATUS (0x1<<9) +#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_SERDES0_LINK_STATUS_SIZE 9 +#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_XGXS0_LINK10G (0x1<<15) +#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_XGXS0_LINK10G_SIZE 15 +#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_XGXS0_LINK_STATUS (0xf<<18) +#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_XGXS0_LINK_STATUS_SIZE 18 +#define NIG_REGISTERS_BMAC0_IN_EN 0xacUL +#define NIG_REGISTERS_BMAC0_OUT_EN 0xe0UL +#define NIG_REGISTERS_BMAC0_PAUSE_OUT_EN 0x110UL +#define NIG_REGISTERS_BMAC0_REGS_OUT_EN 0xe8UL +#define NIG_REGISTERS_BRB0_OUT_EN 0xf8UL +#define NIG_REGISTERS_BRB0_PAUSE_IN_EN 0xc4UL +#define NIG_REGISTERS_BRB1_OUT_EN 0xfcUL +#define NIG_REGISTERS_BRB1_PAUSE_IN_EN 0xc8UL +#define NIG_REGISTERS_BRB_LB_OUT_EN 0x100UL +#define NIG_REGISTERS_DEBUG_PACKET_LB 0x800UL +#define NIG_REGISTERS_DEBUG_PACKET_LB_SIZE 3 +#define NIG_REGISTERS_EGRESS_DEBUG_IN_EN 0xdcUL +#define NIG_REGISTERS_EGRESS_DRAIN0_MODE 0x60UL +#define NIG_REGISTERS_EGRESS_EMAC0_OUT_EN 0x120UL +#define NIG_REGISTERS_EGRESS_EMAC0_PORT 0x58UL +#define NIG_REGISTERS_EGRESS_PBF0_IN_EN 0xccUL +#define NIG_REGISTERS_EGRESS_PBF1_IN_EN 0xd0UL +#define NIG_REGISTERS_EMAC0_IN_EN 0xa4UL +#define NIG_REGISTERS_EMAC0_PAUSE_OUT_EN 0x118UL +#define NIG_REGISTERS_EMAC0_STATUS_MISC_MI_INT 0x494UL +#define NIG_REGISTERS_EMAC0_STATUS_MISC_MI_INT_SIZE 1 +#define NIG_REGISTERS_INGRESS_BMAC0_MEM 0xc00UL +#define NIG_REGISTERS_INGRESS_BMAC0_MEM_SIZE 256 +#define NIG_REGISTERS_INGRESS_BMAC1_MEM 0x1000UL +#define NIG_REGISTERS_INGRESS_BMAC1_MEM_SIZE 256 +#define NIG_REGISTERS_INGRESS_EOP_LB_EMPTY 0x4e0UL +#define NIG_REGISTERS_INGRESS_EOP_LB_EMPTY_SIZE 1 +#define NIG_REGISTERS_INGRESS_EOP_LB_FIFO 0x4e4UL +#define NIG_REGISTERS_INGRESS_EOP_LB_FIFO_SIZE 1 +#define NIG_REGISTERS_LED_10G_P0 0x320UL +#define NIG_REGISTERS_LED_CONTROL_BLINK_RATE_ENA_P0 0x318UL +#define NIG_REGISTERS_LED_CONTROL_BLINK_RATE_P0 0x310UL +#define NIG_REGISTERS_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x2f8UL +#define NIG_REGISTERS_LED_MODE_P0 0x2f0UL +#define NIG_REGISTERS_LLH0_BRB1_DRV_MASK 0x244UL +#define NIG_REGISTERS_LLH0_BRB1_NOT_MCP 0x25cUL +#define NIG_REGISTERS_LLH0_CM_HEADER 0x7cUL +#define NIG_REGISTERS_LLH0_ERROR_MASK 0x8cUL +#define NIG_REGISTERS_LLH0_EVENT_ID 0x84UL +#define NIG_REGISTERS_LLH0_XCM_INIT_CREDIT 0x554UL +#define NIG_REGISTERS_LLH0_XCM_INIT_CREDIT_SIZE 1 +#define NIG_REGISTERS_LLH0_XCM_MASK 0x130UL +#define NIG_REGISTERS_LLH1_BRB1_NOT_MCP 0x2dcUL +#define NIG_REGISTERS_LLH1_CM_HEADER 0x80UL +#define NIG_REGISTERS_LLH1_ERROR_MASK 0x90UL +#define NIG_REGISTERS_LLH1_EVENT_ID 0x88UL +#define NIG_REGISTERS_LLH1_XCM_INIT_CREDIT 0x564UL +#define NIG_REGISTERS_LLH1_XCM_INIT_CREDIT_SIZE 1 +#define NIG_REGISTERS_LLH1_XCM_MASK 0x134UL +#define NIG_REGISTERS_MASK_INTERRUPT_PORT0 0x330UL +#define NIG_REGISTERS_MASK_INTERRUPT_PORT1 0x334UL +#define NIG_REGISTERS_NIG_EMAC0_EN 0x3cUL +#define NIG_REGISTERS_NIG_INGRESS_EMAC0_NO_CRC 0x44UL +#define NIG_REGISTERS_PBF_LB_IN_EN 0xb4UL +#define NIG_REGISTERS_PRS_EOP_OUT_EN 0x104UL +#define NIG_REGISTERS_PRS_REQ_IN_EN 0xb8UL +#define NIG_REGISTERS_SERDES0_CTRL_PHY_ADDR 0x374UL +#define NIG_REGISTERS_SERDES0_STATUS_LINK_STATUS 0x578UL +#define NIG_REGISTERS_SERDES0_STATUS_LINK_STATUS_SIZE 1 +#define NIG_REGISTERS_STAT0_BRB_DISCARD 0x5f0UL +#define NIG_REGISTERS_STAT0_BRB_DISCARD_SIZE 1 +#define NIG_REGISTERS_STAT1_BRB_DISCARD 0x628UL +#define NIG_REGISTERS_STAT1_BRB_DISCARD_SIZE 1 +#define NIG_REGISTERS_STAT2_BRB_OCTET 0x7e0UL +#define NIG_REGISTERS_STAT2_BRB_OCTET_SIZE 2 +#define NIG_REGISTERS_STATUS_INTERRUPT_PORT0 0x328UL +#define NIG_REGISTERS_STATUS_INTERRUPT_PORT1 0x32cUL +#define NIG_REGISTERS_XCM0_OUT_EN 0xf0UL +#define NIG_REGISTERS_XCM1_OUT_EN 0xf4UL +#define NIG_REGISTERS_XGXS0_CTRL_MD_DEVAD 0x33cUL +#define NIG_REGISTERS_XGXS0_CTRL_PHY_ADDR 0x340UL +#define NIG_REGISTERS_XGXS0_STATUS_LINK10G 0x680UL +#define NIG_REGISTERS_XGXS0_STATUS_LINK10G_SIZE 1 +#define NIG_REGISTERS_XGXS0_STATUS_LINK_STATUS 0x684UL +#define NIG_REGISTERS_XGXS0_STATUS_LINK_STATUS_SIZE 1 +#define NIG_REGISTERS_XGXS_LANE_SEL_P0 0x2e8UL +#define NIG_REGISTERS_XGXS_SERDES0_MODE_SEL 0x2e0UL +#define NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_SERDES0_LINK_STATUS (0x1<<9) +#define NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_SERDES0_LINK_STATUS_SIZE 9 +#define NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_XGXS0_LINK10G (0x1<<15) +#define NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_XGXS0_LINK10G_SIZE 15 +#define NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_XGXS0_LINK_STATUS (0xf<<18) +#define NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_XGXS0_LINK_STATUS_SIZE 18 +#define NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_XGXS0_LINK_STATUS_SIZE 18 +#define PBF_REGISTERS_DISABLE_NEW_TASK_PROC_P0 0x5cUL +#define PBF_REGISTERS_DISABLE_NEW_TASK_PROC_P1 0x60UL +#define PBF_REGISTERS_DISABLE_NEW_TASK_PROC_P4 0x6cUL +#define PBF_REGISTERS_IF_ENABLE_REG 0x44UL +#define PBF_REGISTERS_INIT 0x0UL +#define PBF_REGISTERS_INIT_P0 0x4UL +#define PBF_REGISTERS_INIT_P1 0x8UL +#define PBF_REGISTERS_INIT_P4 0xcUL +#define PBF_REGISTERS_INIT_P0 0x4UL +#define PBF_REGISTERS_INIT_P1 0x8UL +#define PBF_REGISTERS_INIT_P4 0xcUL +#define PBF_REGISTERS_MAC_IF0_ENABLE 0x30UL +#define PBF_REGISTERS_MAC_IF1_ENABLE 0x34UL +#define PBF_REGISTERS_MAC_LB_ENABLE 0x40UL +#define PBF_REGISTERS_P0_ARB_THRSH 0xe4UL +#define PBF_REGISTERS_P0_CREDIT 0x200UL +#define PBF_REGISTERS_P0_CREDIT_SIZE 1 +#define PBF_REGISTERS_P0_INIT_CRD 0xd0UL +#define PBF_REGISTERS_P0_PAUSE_ENABLE 0x14UL +#define PBF_REGISTERS_P0_TASK_CNT 0x204UL +#define PBF_REGISTERS_P0_TASK_CNT_SIZE 1 +#define PBF_REGISTERS_P1_CREDIT 0x208UL +#define PBF_REGISTERS_P1_CREDIT_SIZE 1 +#define PBF_REGISTERS_P1_INIT_CRD 0xd4UL +#define PBF_REGISTERS_P1_TASK_CNT 0x20cUL +#define PBF_REGISTERS_P1_TASK_CNT_SIZE 1 +#define PBF_REGISTERS_P4_CREDIT 0x210UL +#define PBF_REGISTERS_P4_CREDIT_SIZE 1 +#define PBF_REGISTERS_P4_INIT_CRD 0xe0UL +#define PBF_REGISTERS_P4_TASK_CNT 0x214UL +#define PBF_REGISTERS_P4_TASK_CNT_SIZE 1 +#define PBF_REGISTERS_PBF_INT_STS 0x1c8UL +#define PBF_REGISTERS_PBF_INT_STS_CLR 0x1ccUL +#define PBF_REGISTERS_PBF_INT_STS_WR 0x1d0UL +#define PB_REGISTERS_CONTROL 0x0UL +#define PB_REGISTERS_PB_INT_STS 0x1cUL +#define PB_REGISTERS_PB_INT_STS_CLR 0x20UL +#define PB_REGISTERS_PB_INT_STS_WR 0x24UL +#define PRS_REGISTERS_CFC_LD_CURRENT_CREDIT 0x164UL +#define PRS_REGISTERS_CFC_SEARCH_CURRENT_CREDIT 0x168UL +#define PRS_REGISTERS_CFC_SEARCH_INITIAL_CREDIT 0x11cUL +#define PRS_REGISTERS_CID_PORT_0 0xfcUL +#define PRS_REGISTERS_CID_PORT_1 0x100UL +#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_0 0xdcUL +#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_1 0xe0UL +#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_2 0xe4UL +#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_3 0xe8UL +#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_4 0xecUL +#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_5 0xf0UL +#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_6 0xf4UL +#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_7 0xf8UL +#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0xbcUL +#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0xc0UL +#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0xc4UL +#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0xc8UL +#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0xccUL +#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0xd0UL +#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_6 0xd4UL +#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_7 0xd8UL +#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_0 0x98UL +#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_1 0x9cUL +#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_2 0xa0UL +#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_3 0xa4UL +#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_4 0xa8UL +#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_5 0xacUL +#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_6 0xb0UL +#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_7 0xb4UL +#define PRS_REGISTERS_CM_HDR_TYPE_0 0x78UL +#define PRS_REGISTERS_CM_HDR_TYPE_1 0x7cUL +#define PRS_REGISTERS_CM_HDR_TYPE_2 0x80UL +#define PRS_REGISTERS_CM_HDR_TYPE_3 0x84UL +#define PRS_REGISTERS_CM_HDR_TYPE_4 0x88UL +#define PRS_REGISTERS_CM_HDR_TYPE_5 0x8cUL +#define PRS_REGISTERS_CM_HDR_TYPE_6 0x90UL +#define PRS_REGISTERS_CM_HDR_TYPE_7 0x94UL +#define PRS_REGISTERS_CM_NO_MATCH_HDR 0xb8UL +#define PRS_REGISTERS_EVENT_ID_1 0x54UL +#define PRS_REGISTERS_EVENT_ID_2 0x58UL +#define PRS_REGISTERS_EVENT_ID_3 0x5cUL +#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_0 0x4UL +#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_1 0x8UL +#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_2 0xcUL +#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_3 0x10UL +#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_4 0x14UL +#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_5 0x18UL +#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_6 0x1cUL +#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_7 0x20UL +#define PRS_REGISTERS_INC_VALUE 0x48UL +#define PRS_REGISTERS_NIC_MODE 0x138UL +#define PRS_REGISTERS_NO_MATCH_EVENT_ID 0x70UL +#define PRS_REGISTERS_NUM_OF_CFC_FLUSH_MESSAGES 0x128UL +#define PRS_REGISTERS_NUM_OF_DEAD_CYCLES 0x130UL +#define PRS_REGISTERS_NUM_OF_PACKETS 0x124UL +#define PRS_REGISTERS_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x12cUL +#define PRS_REGISTERS_PACKET_REGIONS_TYPE_0 0x28UL +#define PRS_REGISTERS_PACKET_REGIONS_TYPE_1 0x2cUL +#define PRS_REGISTERS_PACKET_REGIONS_TYPE_2 0x30UL +#define PRS_REGISTERS_PACKET_REGIONS_TYPE_3 0x34UL +#define PRS_REGISTERS_PACKET_REGIONS_TYPE_4 0x38UL +#define PRS_REGISTERS_PACKET_REGIONS_TYPE_5 0x3cUL +#define PRS_REGISTERS_PACKET_REGIONS_TYPE_6 0x40UL +#define PRS_REGISTERS_PACKET_REGIONS_TYPE_7 0x44UL +#define PRS_REGISTERS_PENDING_BRB_CAC0_RQ 0x174UL +#define PRS_REGISTERS_PENDING_BRB_CAC1_RQ 0x178UL +#define PRS_REGISTERS_PENDING_BRB_CAC2_RQ 0x17cUL +#define PRS_REGISTERS_PENDING_BRB_CAC3_RQ 0x180UL +#define PRS_REGISTERS_PENDING_BRB_CAC4_RQ 0x184UL +#define PRS_REGISTERS_PENDING_BRB_PRS_RQ 0x170UL +#define PRS_REGISTERS_PRS_INT_STS 0x188UL +#define PRS_REGISTERS_PRS_INT_STS_CLR 0x18cUL +#define PRS_REGISTERS_PRS_INT_STS_WR 0x190UL +#define PRS_REGISTERS_PURE_REGIONS 0x24UL +#define PRS_REGISTERS_SERIAL_NUM_STATUS_LSB 0x154UL +#define PRS_REGISTERS_SERIAL_NUM_STATUS_MSB 0x158UL +#define PRS_REGISTERS_SRC_CURRENT_CREDIT 0x16cUL +#define PRS_REGISTERS_TCM_CURRENT_CREDIT 0x160UL +#define PRS_REGISTERS_TSDM_CURRENT_CREDIT 0x15cUL +#define PXP2_REGISTERS_HST_DATA_FIFO_STATUS 0x47cUL +#define PXP2_REGISTERS_HST_HEADER_FIFO_STATUS 0x478UL +#define PXP2_REGISTERS_PGL_CONTROL0 0x490UL +#define PXP2_REGISTERS_PGL_CONTROL1 0x514UL +#define PXP2_REGISTERS_PGL_INT_CSDM_0 0x4f4UL +#define PXP2_REGISTERS_PGL_INT_CSDM_1 0x4f8UL +#define PXP2_REGISTERS_PGL_INT_CSDM_2 0x4fcUL +#define PXP2_REGISTERS_PGL_INT_CSDM_3 0x500UL +#define PXP2_REGISTERS_PGL_INT_CSDM_4 0x504UL +#define PXP2_REGISTERS_PGL_INT_CSDM_5 0x508UL +#define PXP2_REGISTERS_PGL_INT_CSDM_6 0x50cUL +#define PXP2_REGISTERS_PGL_INT_CSDM_7 0x510UL +#define PXP2_REGISTERS_PGL_INT_TSDM_0 0x494UL +#define PXP2_REGISTERS_PGL_INT_TSDM_1 0x498UL +#define PXP2_REGISTERS_PGL_INT_TSDM_2 0x49cUL +#define PXP2_REGISTERS_PGL_INT_TSDM_3 0x4a0UL +#define PXP2_REGISTERS_PGL_INT_TSDM_4 0x4a4UL +#define PXP2_REGISTERS_PGL_INT_TSDM_5 0x4a8UL +#define PXP2_REGISTERS_PGL_INT_TSDM_6 0x4acUL +#define PXP2_REGISTERS_PGL_INT_TSDM_7 0x4b0UL +#define PXP2_REGISTERS_PGL_INT_USDM_0 0x4b4UL +#define PXP2_REGISTERS_PGL_INT_USDM_1 0x4b8UL +#define PXP2_REGISTERS_PGL_INT_USDM_2 0x4bcUL +#define PXP2_REGISTERS_PGL_INT_USDM_3 0x4c0UL +#define PXP2_REGISTERS_PGL_INT_USDM_4 0x4c4UL +#define PXP2_REGISTERS_PGL_INT_USDM_5 0x4c8UL +#define PXP2_REGISTERS_PGL_INT_USDM_6 0x4ccUL +#define PXP2_REGISTERS_PGL_INT_USDM_7 0x4d0UL +#define PXP2_REGISTERS_PGL_INT_XSDM_0 0x4d4UL +#define PXP2_REGISTERS_PGL_INT_XSDM_1 0x4d8UL +#define PXP2_REGISTERS_PGL_INT_XSDM_2 0x4dcUL +#define PXP2_REGISTERS_PGL_INT_XSDM_3 0x4e0UL +#define PXP2_REGISTERS_PGL_INT_XSDM_4 0x4e4UL +#define PXP2_REGISTERS_PGL_INT_XSDM_5 0x4e8UL +#define PXP2_REGISTERS_PGL_INT_XSDM_6 0x4ecUL +#define PXP2_REGISTERS_PGL_INT_XSDM_7 0x4f0UL +#define PXP2_REGISTERS_PGL_READ_BLOCKED 0x568UL +#define PXP2_REGISTERS_PGL_TXR_CDTS 0x528UL +#define PXP2_REGISTERS_PGL_TXW_CDTS 0x52cUL +#define PXP2_REGISTERS_PGL_WRITE_BLOCKED 0x564UL +#define PXP2_REGISTERS_PSWRQ_BW_ADD1 0x1c0UL +#define PXP2_REGISTERS_PSWRQ_BW_ADD10 0x1e4UL +#define PXP2_REGISTERS_PSWRQ_BW_ADD11 0x1e8UL +#define PXP2_REGISTERS_PSWRQ_BW_ADD10 0x1e4UL +#define PXP2_REGISTERS_PSWRQ_BW_ADD11 0x1e8UL +#define PXP2_REGISTERS_PSWRQ_BW_ADD2 0x1c4UL +#define PXP2_REGISTERS_PSWRQ_BW_ADD28 0x228UL +#define PXP2_REGISTERS_PSWRQ_BW_ADD28 0x228UL +#define PXP2_REGISTERS_PSWRQ_BW_ADD3 0x1c8UL +#define PXP2_REGISTERS_PSWRQ_BW_ADD6 0x1d4UL +#define PXP2_REGISTERS_PSWRQ_BW_ADD7 0x1d8UL +#define PXP2_REGISTERS_PSWRQ_BW_ADD8 0x1dcUL +#define PXP2_REGISTERS_PSWRQ_BW_ADD9 0x1e0UL +#define PXP2_REGISTERS_PSWRQ_BW_CREDIT 0x32cUL +#define PXP2_REGISTERS_PSWRQ_BW_L1 0x2b0UL +#define PXP2_REGISTERS_PSWRQ_BW_L10 0x2d4UL +#define PXP2_REGISTERS_PSWRQ_BW_L11 0x2d8UL +#define PXP2_REGISTERS_PSWRQ_BW_L10 0x2d4UL +#define PXP2_REGISTERS_PSWRQ_BW_L11 0x2d8UL +#define PXP2_REGISTERS_PSWRQ_BW_L2 0x2b4UL +#define PXP2_REGISTERS_PSWRQ_BW_L28 0x318UL +#define PXP2_REGISTERS_PSWRQ_BW_L28 0x318UL +#define PXP2_REGISTERS_PSWRQ_BW_L3 0x2b8UL +#define PXP2_REGISTERS_PSWRQ_BW_L6 0x2c4UL +#define PXP2_REGISTERS_PSWRQ_BW_L7 0x2c8UL +#define PXP2_REGISTERS_PSWRQ_BW_L8 0x2ccUL +#define PXP2_REGISTERS_PSWRQ_BW_L9 0x2d0UL +#define PXP2_REGISTERS_PSWRQ_BW_RD 0x324UL +#define PXP2_REGISTERS_PSWRQ_BW_UB1 0x238UL +#define PXP2_REGISTERS_PSWRQ_BW_UB10 0x25cUL +#define PXP2_REGISTERS_PSWRQ_BW_UB11 0x260UL +#define PXP2_REGISTERS_PSWRQ_BW_UB10 0x25cUL +#define PXP2_REGISTERS_PSWRQ_BW_UB11 0x260UL +#define PXP2_REGISTERS_PSWRQ_BW_UB2 0x23cUL +#define PXP2_REGISTERS_PSWRQ_BW_UB28 0x2a0UL +#define PXP2_REGISTERS_PSWRQ_BW_UB28 0x2a0UL +#define PXP2_REGISTERS_PSWRQ_BW_UB3 0x240UL +#define PXP2_REGISTERS_PSWRQ_BW_UB6 0x24cUL +#define PXP2_REGISTERS_PSWRQ_BW_UB7 0x250UL +#define PXP2_REGISTERS_PSWRQ_BW_UB8 0x254UL +#define PXP2_REGISTERS_PSWRQ_BW_UB9 0x258UL +#define PXP2_REGISTERS_PSWRQ_BW_WR 0x328UL +#define PXP2_REGISTERS_PSWRQ_CDU0_L2P 0x0UL +#define PXP2_REGISTERS_PSWRQ_CDU1_L2P 0x4UL +#define PXP2_REGISTERS_PSWRQ_QM0_L2P 0x38UL +#define PXP2_REGISTERS_PSWRQ_QM1_L2P 0x3cUL +#define PXP2_REGISTERS_PSWRQ_SRC0_L2P 0x54UL +#define PXP2_REGISTERS_PSWRQ_SRC1_L2P 0x58UL +#define PXP2_REGISTERS_PSWRQ_TM0_L2P 0x1cUL +#define PXP2_REGISTERS_PSWRQ_TM1_L2P 0x20UL +#define PXP2_REGISTERS_RD_ALMOST_FULL_0 0x424UL +#define PXP2_REGISTERS_RD_ALMOST_FULL_1 0x428UL +#define PXP2_REGISTERS_RD_ALMOST_FULL_10 0x44cUL +#define PXP2_REGISTERS_RD_ALMOST_FULL_10 0x44cUL +#define PXP2_REGISTERS_RD_ALMOST_FULL_2 0x42cUL +#define PXP2_REGISTERS_RD_ALMOST_FULL_3 0x430UL +#define PXP2_REGISTERS_RD_ALMOST_FULL_4 0x434UL +#define PXP2_REGISTERS_RD_ALMOST_FULL_5 0x438UL +#define PXP2_REGISTERS_RD_ALMOST_FULL_6 0x43cUL +#define PXP2_REGISTERS_RD_ALMOST_FULL_7 0x440UL +#define PXP2_REGISTERS_RD_ALMOST_FULL_8 0x444UL +#define PXP2_REGISTERS_RD_ALMOST_FULL_9 0x448UL +#define PXP2_REGISTERS_RD_BLK_CNT 0x418UL +#define PXP2_REGISTERS_RD_BLK_NUM_CFG 0x40cUL +#define PXP2_REGISTERS_RD_CDURD_SWAP_MODE 0x404UL +#define PXP2_REGISTERS_RD_DISABLE_INPUTS 0x374UL +#define PXP2_REGISTERS_RD_INIT_DONE 0x370UL +#define PXP2_REGISTERS_RD_MAX_BLKS_VQ10 0x3a0UL +#define PXP2_REGISTERS_RD_MAX_BLKS_VQ11 0x3a4UL +#define PXP2_REGISTERS_RD_MAX_BLKS_VQ17 0x3bcUL +#define PXP2_REGISTERS_RD_MAX_BLKS_VQ18 0x3c0UL +#define PXP2_REGISTERS_RD_MAX_BLKS_VQ19 0x3c4UL +#define PXP2_REGISTERS_RD_MAX_BLKS_VQ22 0x3d0UL +#define PXP2_REGISTERS_RD_MAX_BLKS_VQ6 0x390UL +#define PXP2_REGISTERS_RD_MAX_BLKS_VQ9 0x39cUL +#define PXP2_REGISTERS_RD_PBF_SWAP_MODE 0x3f4UL +#define PXP2_REGISTERS_RD_PORT_IS_IDLE_0 0x41cUL +#define PXP2_REGISTERS_RD_PORT_IS_IDLE_1 0x420UL +#define PXP2_REGISTERS_RD_QM_SWAP_MODE 0x3f8UL +#define PXP2_REGISTERS_RD_SR_CNT 0x414UL +#define PXP2_REGISTERS_RD_SRC_SWAP_MODE 0x400UL +#define PXP2_REGISTERS_RD_SR_NUM_CFG 0x408UL +#define PXP2_REGISTERS_RD_START_INIT 0x36cUL +#define PXP2_REGISTERS_RD_TM_SWAP_MODE 0x3fcUL +#define PXP2_REGISTERS_RQ_BW_RD_ADD0 0x1bcUL +#define PXP2_REGISTERS_RQ_BW_RD_ADD12 0x1ecUL +#define PXP2_REGISTERS_RQ_BW_RD_ADD13 0x1f0UL +#define PXP2_REGISTERS_RQ_BW_RD_ADD14 0x1f4UL +#define PXP2_REGISTERS_RQ_BW_RD_ADD15 0x1f8UL +#define PXP2_REGISTERS_RQ_BW_RD_ADD16 0x1fcUL +#define PXP2_REGISTERS_RQ_BW_RD_ADD17 0x200UL +#define PXP2_REGISTERS_RQ_BW_RD_ADD18 0x204UL +#define PXP2_REGISTERS_RQ_BW_RD_ADD19 0x208UL +#define PXP2_REGISTERS_RQ_BW_RD_ADD20 0x20cUL +#define PXP2_REGISTERS_RQ_BW_RD_ADD22 0x210UL +#define PXP2_REGISTERS_RQ_BW_RD_ADD23 0x214UL +#define PXP2_REGISTERS_RQ_BW_RD_ADD24 0x218UL +#define PXP2_REGISTERS_RQ_BW_RD_ADD25 0x21cUL +#define PXP2_REGISTERS_RQ_BW_RD_ADD26 0x220UL +#define PXP2_REGISTERS_RQ_BW_RD_ADD27 0x224UL +#define PXP2_REGISTERS_RQ_BW_RD_ADD4 0x1ccUL +#define PXP2_REGISTERS_RQ_BW_RD_ADD5 0x1d0UL +#define PXP2_REGISTERS_RQ_BW_RD_L0 0x2acUL +#define PXP2_REGISTERS_RQ_BW_RD_L12 0x2dcUL +#define PXP2_REGISTERS_RQ_BW_RD_L13 0x2e0UL +#define PXP2_REGISTERS_RQ_BW_RD_L14 0x2e4UL +#define PXP2_REGISTERS_RQ_BW_RD_L15 0x2e8UL +#define PXP2_REGISTERS_RQ_BW_RD_L16 0x2ecUL +#define PXP2_REGISTERS_RQ_BW_RD_L17 0x2f0UL +#define PXP2_REGISTERS_RQ_BW_RD_L18 0x2f4UL +#define PXP2_REGISTERS_RQ_BW_RD_L19 0x2f8UL +#define PXP2_REGISTERS_RQ_BW_RD_L20 0x2fcUL +#define PXP2_REGISTERS_RQ_BW_RD_L22 0x300UL +#define PXP2_REGISTERS_RQ_BW_RD_L23 0x304UL +#define PXP2_REGISTERS_RQ_BW_RD_L24 0x308UL +#define PXP2_REGISTERS_RQ_BW_RD_L25 0x30cUL +#define PXP2_REGISTERS_RQ_BW_RD_L26 0x310UL +#define PXP2_REGISTERS_RQ_BW_RD_L27 0x314UL +#define PXP2_REGISTERS_RQ_BW_RD_L4 0x2bcUL +#define PXP2_REGISTERS_RQ_BW_RD_L5 0x2c0UL +#define PXP2_REGISTERS_RQ_BW_RD_UBOUND0 0x234UL +#define PXP2_REGISTERS_RQ_BW_RD_UBOUND12 0x264UL +#define PXP2_REGISTERS_RQ_BW_RD_UBOUND13 0x268UL +#define PXP2_REGISTERS_RQ_BW_RD_UBOUND14 0x26cUL +#define PXP2_REGISTERS_RQ_BW_RD_UBOUND15 0x270UL +#define PXP2_REGISTERS_RQ_BW_RD_UBOUND16 0x274UL +#define PXP2_REGISTERS_RQ_BW_RD_UBOUND17 0x278UL +#define PXP2_REGISTERS_RQ_BW_RD_UBOUND18 0x27cUL +#define PXP2_REGISTERS_RQ_BW_RD_UBOUND19 0x280UL +#define PXP2_REGISTERS_RQ_BW_RD_UBOUND20 0x284UL +#define PXP2_REGISTERS_RQ_BW_RD_UBOUND22 0x288UL +#define PXP2_REGISTERS_RQ_BW_RD_UBOUND23 0x28cUL +#define PXP2_REGISTERS_RQ_BW_RD_UBOUND24 0x290UL +#define PXP2_REGISTERS_RQ_BW_RD_UBOUND25 0x294UL +#define PXP2_REGISTERS_RQ_BW_RD_UBOUND26 0x298UL +#define PXP2_REGISTERS_RQ_BW_RD_UBOUND27 0x29cUL +#define PXP2_REGISTERS_RQ_BW_RD_UBOUND4 0x244UL +#define PXP2_REGISTERS_RQ_BW_RD_UBOUND5 0x248UL +#define PXP2_REGISTERS_RQ_BW_WR_ADD29 0x22cUL +#define PXP2_REGISTERS_RQ_BW_WR_ADD30 0x230UL +#define PXP2_REGISTERS_RQ_BW_WR_L29 0x31cUL +#define PXP2_REGISTERS_RQ_BW_WR_L30 0x320UL +#define PXP2_REGISTERS_RQ_BW_WR_UBOUND29 0x2a4UL +#define PXP2_REGISTERS_RQ_BW_WR_UBOUND30 0x2a8UL +#define PXP2_REGISTERS_RQ_CDU_ENDIAN_M 0x1a0UL +#define PXP2_REGISTERS_RQ_CDU_P_SIZE 0x18UL +#define PXP2_REGISTERS_RQ_CFG_DONE 0x1b4UL +#define PXP2_REGISTERS_RQ_DBG_ENDIAN_M 0x1a4UL +#define PXP2_REGISTERS_RQ_DISABLE_INPUTS 0x330UL +#define PXP2_REGISTERS_RQ_HC_ENDIAN_M 0x1a8UL +#define PXP2_REGISTERS_RQ_ONCHIP_AT 0x2000UL +#define PXP2_REGISTERS_RQ_ONCHIP_AT_SIZE 2048 +#define PXP2_REGISTERS_RQ_QM_ENDIAN_M 0x194UL +#define PXP2_REGISTERS_RQ_QM_P_SIZE 0x50UL +#define PXP2_REGISTERS_RQ_RBC_DONE 0x1b0UL +#define PXP2_REGISTERS_RQ_RD_MBS0 0x160UL +#define PXP2_REGISTERS_RQ_SRC_ENDIAN_M 0x19cUL +#define PXP2_REGISTERS_RQ_SRC_P_SIZE 0x6cUL +#define PXP2_REGISTERS_RQ_TM_ENDIAN_M 0x198UL +#define PXP2_REGISTERS_RQ_TM_P_SIZE 0x34UL +#define PXP2_REGISTERS_RQ_UFIFO_NUM_OF_ENTRY 0x80cUL +#define PXP2_REGISTERS_RQ_UFIFO_NUM_OF_ENTRY_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ0_ENTRY_CNT 0x810UL +#define PXP2_REGISTERS_RQ_VQ0_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ10_ENTRY_CNT 0x818UL +#define PXP2_REGISTERS_RQ_VQ10_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ11_ENTRY_CNT 0x820UL +#define PXP2_REGISTERS_RQ_VQ11_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ12_ENTRY_CNT 0x828UL +#define PXP2_REGISTERS_RQ_VQ12_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ13_ENTRY_CNT 0x830UL +#define PXP2_REGISTERS_RQ_VQ13_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ14_ENTRY_CNT 0x838UL +#define PXP2_REGISTERS_RQ_VQ14_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ15_ENTRY_CNT 0x840UL +#define PXP2_REGISTERS_RQ_VQ15_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ16_ENTRY_CNT 0x848UL +#define PXP2_REGISTERS_RQ_VQ16_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ17_ENTRY_CNT 0x850UL +#define PXP2_REGISTERS_RQ_VQ17_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ18_ENTRY_CNT 0x858UL +#define PXP2_REGISTERS_RQ_VQ18_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ19_ENTRY_CNT 0x860UL +#define PXP2_REGISTERS_RQ_VQ19_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ1_ENTRY_CNT 0x868UL +#define PXP2_REGISTERS_RQ_VQ1_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ20_ENTRY_CNT 0x870UL +#define PXP2_REGISTERS_RQ_VQ20_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ21_ENTRY_CNT 0x878UL +#define PXP2_REGISTERS_RQ_VQ21_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ22_ENTRY_CNT 0x880UL +#define PXP2_REGISTERS_RQ_VQ22_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ23_ENTRY_CNT 0x888UL +#define PXP2_REGISTERS_RQ_VQ23_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ24_ENTRY_CNT 0x890UL +#define PXP2_REGISTERS_RQ_VQ24_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ25_ENTRY_CNT 0x898UL +#define PXP2_REGISTERS_RQ_VQ25_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ26_ENTRY_CNT 0x8a0UL +#define PXP2_REGISTERS_RQ_VQ26_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ27_ENTRY_CNT 0x8a8UL +#define PXP2_REGISTERS_RQ_VQ27_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ28_ENTRY_CNT 0x8b0UL +#define PXP2_REGISTERS_RQ_VQ28_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ29_ENTRY_CNT 0x8b8UL +#define PXP2_REGISTERS_RQ_VQ29_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ2_ENTRY_CNT 0x8c0UL +#define PXP2_REGISTERS_RQ_VQ2_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ30_ENTRY_CNT 0x8c8UL +#define PXP2_REGISTERS_RQ_VQ30_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ31_ENTRY_CNT 0x8d0UL +#define PXP2_REGISTERS_RQ_VQ31_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ3_ENTRY_CNT 0x8d8UL +#define PXP2_REGISTERS_RQ_VQ3_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ4_ENTRY_CNT 0x8e0UL +#define PXP2_REGISTERS_RQ_VQ4_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ5_ENTRY_CNT 0x8e8UL +#define PXP2_REGISTERS_RQ_VQ5_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ6_ENTRY_CNT 0x8f0UL +#define PXP2_REGISTERS_RQ_VQ6_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ7_ENTRY_CNT 0x8f8UL +#define PXP2_REGISTERS_RQ_VQ7_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ8_ENTRY_CNT 0x900UL +#define PXP2_REGISTERS_RQ_VQ8_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_VQ9_ENTRY_CNT 0x908UL +#define PXP2_REGISTERS_RQ_VQ9_ENTRY_CNT_SIZE 1 +#define PXP2_REGISTERS_RQ_WR_MBS0 0x15cUL +#define PXP_REGISTERS_HST_ARB_IS_IDLE 0x4UL +#define PXP_REGISTERS_HST_CLIENTS_WAITING_TO_ARB 0x8UL +#define PXP_REGISTERS_HST_INBOUND_INT 0x800UL +#define PXP_REGISTERS_HST_INBOUND_INT_SIZE 512 +#define PXP_REGISTERS_PXP_INT_MASK_0 0x74UL +#define PXP_REGISTERS_PXP_INT_STS_0 0x68UL +#define PXP_REGISTERS_PXP_INT_STS_1 0x78UL +#define PXP_REGISTERS_PXP_INT_STS_CLR_0 0x6cUL +#define QM_REGISTERS_ACTCTRINITVAL_0 0x40UL +#define QM_REGISTERS_ACTCTRINITVAL_1 0x44UL +#define QM_REGISTERS_ACTCTRINITVAL_2 0x48UL +#define QM_REGISTERS_ACTCTRINITVAL_3 0x4cUL +#define QM_REGISTERS_BASEADDR 0x900UL +#define QM_REGISTERS_BASEADDR_SIZE 64 +#define QM_REGISTERS_BYTECRDCOST 0x234UL +#define QM_REGISTERS_BYTECRDINITVAL 0x238UL +#define QM_REGISTERS_BYTECRDPORT_LSB 0x228UL +#define QM_REGISTERS_BYTECRDPORT_MSB 0x224UL +#define QM_REGISTERS_BYTECREDITAFULLTHR 0x94UL +#define QM_REGISTERS_CMINITCRD_0 0xccUL +#define QM_REGISTERS_CMINITCRD_1 0xd0UL +#define QM_REGISTERS_CMINITCRD_2 0xd4UL +#define QM_REGISTERS_CMINITCRD_3 0xd8UL +#define QM_REGISTERS_CMINITCRD_4 0xdcUL +#define QM_REGISTERS_CMINITCRD_5 0xe0UL +#define QM_REGISTERS_CMINITCRD_6 0xe4UL +#define QM_REGISTERS_CMINITCRD_7 0xe8UL +#define QM_REGISTERS_CMINTEN 0xecUL +#define QM_REGISTERS_CMINTVOQMASK_0 0x1f4UL +#define QM_REGISTERS_CMINTVOQMASK_1 0x1f8UL +#define QM_REGISTERS_CMINTVOQMASK_2 0x1fcUL +#define QM_REGISTERS_CMINTVOQMASK_3 0x200UL +#define QM_REGISTERS_CMINTVOQMASK_4 0x204UL +#define QM_REGISTERS_CMINTVOQMASK_5 0x208UL +#define QM_REGISTERS_CMINTVOQMASK_6 0x20cUL +#define QM_REGISTERS_CMINTVOQMASK_7 0x210UL +#define QM_REGISTERS_CONNNUM_0 0x20UL +#define QM_REGISTERS_CONNNUM_1 0x24UL +#define QM_REGISTERS_CTXREG_0 0x30UL +#define QM_REGISTERS_CTXREG_1 0x34UL +#define QM_REGISTERS_CTXREG_2 0x38UL +#define QM_REGISTERS_CTXREG_3 0x3cUL +#define QM_REGISTERS_ENBYPVOQMASK 0x23cUL +#define QM_REGISTERS_ENBYTECRD_LSB 0x220UL +#define QM_REGISTERS_ENBYTECRD_MSB 0x21cUL +#define QM_REGISTERS_ENSEC 0xf0UL +#define QM_REGISTERS_FUNCNUMSEL_LSB 0x230UL +#define QM_REGISTERS_FUNCNUMSEL_MSB 0x22cUL +#define QM_REGISTERS_HWAEMPTYMASK_LSB 0x218UL +#define QM_REGISTERS_HWAEMPTYMASK_MSB 0x214UL +#define QM_REGISTERS_OUTLDREQ 0x804UL +#define QM_REGISTERS_OUTLDREQ_SIZE 1 +#define QM_REGISTERS_PCIREQAT 0x54UL +#define QM_REGISTERS_PORT0BYTECRD 0x300UL +#define QM_REGISTERS_PORT1BYTECRD 0x304UL +#define QM_REGISTERS_PTRTBL 0xa00UL +#define QM_REGISTERS_PTRTBL_SIZE 128 +#define QM_REGISTERS_QTASKCTR_0 0x308UL +#define QM_REGISTERS_QVOQIDX_0 0xf4UL +#define QM_REGISTERS_QVOQIDX_1 0xf8UL +#define QM_REGISTERS_QVOQIDX_10 0x11cUL +#define QM_REGISTERS_QVOQIDX_11 0x120UL +#define QM_REGISTERS_QVOQIDX_12 0x124UL +#define QM_REGISTERS_QVOQIDX_13 0x128UL +#define QM_REGISTERS_QVOQIDX_14 0x12cUL +#define QM_REGISTERS_QVOQIDX_15 0x130UL +#define QM_REGISTERS_QVOQIDX_16 0x134UL +#define QM_REGISTERS_QVOQIDX_17 0x138UL +#define QM_REGISTERS_QVOQIDX_18 0x13cUL +#define QM_REGISTERS_QVOQIDX_19 0x140UL +#define QM_REGISTERS_QVOQIDX_10 0x11cUL +#define QM_REGISTERS_QVOQIDX_11 0x120UL +#define QM_REGISTERS_QVOQIDX_12 0x124UL +#define QM_REGISTERS_QVOQIDX_13 0x128UL +#define QM_REGISTERS_QVOQIDX_14 0x12cUL +#define QM_REGISTERS_QVOQIDX_15 0x130UL +#define QM_REGISTERS_QVOQIDX_16 0x134UL +#define QM_REGISTERS_QVOQIDX_17 0x138UL +#define QM_REGISTERS_QVOQIDX_18 0x13cUL +#define QM_REGISTERS_QVOQIDX_19 0x140UL +#define QM_REGISTERS_QVOQIDX_2 0xfcUL +#define QM_REGISTERS_QVOQIDX_20 0x144UL +#define QM_REGISTERS_QVOQIDX_21 0x148UL +#define QM_REGISTERS_QVOQIDX_22 0x14cUL +#define QM_REGISTERS_QVOQIDX_23 0x150UL +#define QM_REGISTERS_QVOQIDX_24 0x154UL +#define QM_REGISTERS_QVOQIDX_25 0x158UL +#define QM_REGISTERS_QVOQIDX_26 0x15cUL +#define QM_REGISTERS_QVOQIDX_27 0x160UL +#define QM_REGISTERS_QVOQIDX_28 0x164UL +#define QM_REGISTERS_QVOQIDX_29 0x168UL +#define QM_REGISTERS_QVOQIDX_20 0x144UL +#define QM_REGISTERS_QVOQIDX_21 0x148UL +#define QM_REGISTERS_QVOQIDX_22 0x14cUL +#define QM_REGISTERS_QVOQIDX_23 0x150UL +#define QM_REGISTERS_QVOQIDX_24 0x154UL +#define QM_REGISTERS_QVOQIDX_25 0x158UL +#define QM_REGISTERS_QVOQIDX_26 0x15cUL +#define QM_REGISTERS_QVOQIDX_27 0x160UL +#define QM_REGISTERS_QVOQIDX_28 0x164UL +#define QM_REGISTERS_QVOQIDX_29 0x168UL +#define QM_REGISTERS_QVOQIDX_3 0x100UL +#define QM_REGISTERS_QVOQIDX_30 0x16cUL +#define QM_REGISTERS_QVOQIDX_31 0x170UL +#define QM_REGISTERS_QVOQIDX_32 0x174UL +#define QM_REGISTERS_QVOQIDX_33 0x178UL +#define QM_REGISTERS_QVOQIDX_34 0x17cUL +#define QM_REGISTERS_QVOQIDX_35 0x180UL +#define QM_REGISTERS_QVOQIDX_36 0x184UL +#define QM_REGISTERS_QVOQIDX_37 0x188UL +#define QM_REGISTERS_QVOQIDX_38 0x18cUL +#define QM_REGISTERS_QVOQIDX_39 0x190UL +#define QM_REGISTERS_QVOQIDX_30 0x16cUL +#define QM_REGISTERS_QVOQIDX_31 0x170UL +#define QM_REGISTERS_QVOQIDX_32 0x174UL +#define QM_REGISTERS_QVOQIDX_33 0x178UL +#define QM_REGISTERS_QVOQIDX_34 0x17cUL +#define QM_REGISTERS_QVOQIDX_35 0x180UL +#define QM_REGISTERS_QVOQIDX_36 0x184UL +#define QM_REGISTERS_QVOQIDX_37 0x188UL +#define QM_REGISTERS_QVOQIDX_38 0x18cUL +#define QM_REGISTERS_QVOQIDX_39 0x190UL +#define QM_REGISTERS_QVOQIDX_4 0x104UL +#define QM_REGISTERS_QVOQIDX_40 0x194UL +#define QM_REGISTERS_QVOQIDX_41 0x198UL +#define QM_REGISTERS_QVOQIDX_42 0x19cUL +#define QM_REGISTERS_QVOQIDX_43 0x1a0UL +#define QM_REGISTERS_QVOQIDX_44 0x1a4UL +#define QM_REGISTERS_QVOQIDX_45 0x1a8UL +#define QM_REGISTERS_QVOQIDX_46 0x1acUL +#define QM_REGISTERS_QVOQIDX_47 0x1b0UL +#define QM_REGISTERS_QVOQIDX_48 0x1b4UL +#define QM_REGISTERS_QVOQIDX_49 0x1b8UL +#define QM_REGISTERS_QVOQIDX_40 0x194UL +#define QM_REGISTERS_QVOQIDX_41 0x198UL +#define QM_REGISTERS_QVOQIDX_42 0x19cUL +#define QM_REGISTERS_QVOQIDX_43 0x1a0UL +#define QM_REGISTERS_QVOQIDX_44 0x1a4UL +#define QM_REGISTERS_QVOQIDX_45 0x1a8UL +#define QM_REGISTERS_QVOQIDX_46 0x1acUL +#define QM_REGISTERS_QVOQIDX_47 0x1b0UL +#define QM_REGISTERS_QVOQIDX_48 0x1b4UL +#define QM_REGISTERS_QVOQIDX_49 0x1b8UL +#define QM_REGISTERS_QVOQIDX_5 0x108UL +#define QM_REGISTERS_QVOQIDX_50 0x1bcUL +#define QM_REGISTERS_QVOQIDX_51 0x1c0UL +#define QM_REGISTERS_QVOQIDX_52 0x1c4UL +#define QM_REGISTERS_QVOQIDX_53 0x1c8UL +#define QM_REGISTERS_QVOQIDX_54 0x1ccUL +#define QM_REGISTERS_QVOQIDX_55 0x1d0UL +#define QM_REGISTERS_QVOQIDX_56 0x1d4UL +#define QM_REGISTERS_QVOQIDX_57 0x1d8UL +#define QM_REGISTERS_QVOQIDX_58 0x1dcUL +#define QM_REGISTERS_QVOQIDX_59 0x1e0UL +#define QM_REGISTERS_QVOQIDX_50 0x1bcUL +#define QM_REGISTERS_QVOQIDX_51 0x1c0UL +#define QM_REGISTERS_QVOQIDX_52 0x1c4UL +#define QM_REGISTERS_QVOQIDX_53 0x1c8UL +#define QM_REGISTERS_QVOQIDX_54 0x1ccUL +#define QM_REGISTERS_QVOQIDX_55 0x1d0UL +#define QM_REGISTERS_QVOQIDX_56 0x1d4UL +#define QM_REGISTERS_QVOQIDX_57 0x1d8UL +#define QM_REGISTERS_QVOQIDX_58 0x1dcUL +#define QM_REGISTERS_QVOQIDX_59 0x1e0UL +#define QM_REGISTERS_QVOQIDX_6 0x10cUL +#define QM_REGISTERS_QVOQIDX_60 0x1e4UL +#define QM_REGISTERS_QVOQIDX_61 0x1e8UL +#define QM_REGISTERS_QVOQIDX_62 0x1ecUL +#define QM_REGISTERS_QVOQIDX_63 0x1f0UL +#define QM_REGISTERS_QVOQIDX_60 0x1e4UL +#define QM_REGISTERS_QVOQIDX_61 0x1e8UL +#define QM_REGISTERS_QVOQIDX_62 0x1ecUL +#define QM_REGISTERS_QVOQIDX_63 0x1f0UL +#define QM_REGISTERS_QVOQIDX_7 0x110UL +#define QM_REGISTERS_QVOQIDX_8 0x114UL +#define QM_REGISTERS_QVOQIDX_9 0x118UL +#define QM_REGISTERS_SOFT_RESET 0x428UL +#define QM_REGISTERS_TASKCRDCOST_0 0x9cUL +#define QM_REGISTERS_TASKCRDCOST_1 0xa0UL +#define QM_REGISTERS_TASKCRDCOST_10 0xc4UL +#define QM_REGISTERS_TASKCRDCOST_11 0xc8UL +#define QM_REGISTERS_TASKCRDCOST_10 0xc4UL +#define QM_REGISTERS_TASKCRDCOST_11 0xc8UL +#define QM_REGISTERS_TASKCRDCOST_2 0xa4UL +#define QM_REGISTERS_TASKCRDCOST_3 0xa8UL +#define QM_REGISTERS_TASKCRDCOST_4 0xacUL +#define QM_REGISTERS_TASKCRDCOST_5 0xb0UL +#define QM_REGISTERS_TASKCRDCOST_6 0xb4UL +#define QM_REGISTERS_TASKCRDCOST_7 0xb8UL +#define QM_REGISTERS_TASKCRDCOST_8 0xbcUL +#define QM_REGISTERS_TASKCRDCOST_9 0xc0UL +#define QM_REGISTERS_VOQCRDERRREG 0x408UL +#define QM_REGISTERS_VOQCREDIT_0 0x2d0UL +#define QM_REGISTERS_VOQCREDIT_1 0x2d4UL +#define QM_REGISTERS_VOQCREDIT_10 0x2f8UL +#define QM_REGISTERS_VOQCREDIT_11 0x2fcUL +#define QM_REGISTERS_VOQCREDIT_4 0x2e0UL +#define QM_REGISTERS_VOQCREDITAFULLTHR 0x90UL +#define QM_REGISTERS_VOQINITCREDIT_0 0x60UL +#define QM_REGISTERS_VOQINITCREDIT_1 0x64UL +#define QM_REGISTERS_VOQINITCREDIT_10 0x88UL +#define QM_REGISTERS_VOQINITCREDIT_11 0x8cUL +#define QM_REGISTERS_VOQINITCREDIT_10 0x88UL +#define QM_REGISTERS_VOQINITCREDIT_11 0x8cUL +#define QM_REGISTERS_VOQINITCREDIT_2 0x68UL +#define QM_REGISTERS_VOQINITCREDIT_3 0x6cUL +#define QM_REGISTERS_VOQINITCREDIT_4 0x70UL +#define QM_REGISTERS_VOQINITCREDIT_5 0x74UL +#define QM_REGISTERS_VOQINITCREDIT_6 0x78UL +#define QM_REGISTERS_VOQINITCREDIT_7 0x7cUL +#define QM_REGISTERS_VOQINITCREDIT_8 0x80UL +#define QM_REGISTERS_VOQINITCREDIT_9 0x84UL +#define QM_REGISTERS_VOQPORT_0 0x2a0UL +#define QM_REGISTERS_VOQPORT_1 0x2a4UL +#define QM_REGISTERS_VOQPORT_10 0x2c8UL +#define QM_REGISTERS_VOQPORT_11 0x2ccUL +#define QM_REGISTERS_VOQPORT_10 0x2c8UL +#define QM_REGISTERS_VOQPORT_11 0x2ccUL +#define QM_REGISTERS_VOQPORT_2 0x2a8UL +#define QM_REGISTERS_VOQPORT_3 0x2acUL +#define QM_REGISTERS_VOQPORT_4 0x2b0UL +#define QM_REGISTERS_VOQPORT_5 0x2b4UL +#define QM_REGISTERS_VOQPORT_6 0x2b8UL +#define QM_REGISTERS_VOQPORT_7 0x2bcUL +#define QM_REGISTERS_VOQPORT_8 0x2c0UL +#define QM_REGISTERS_VOQPORT_9 0x2c4UL +#define QM_REGISTERS_VOQQMASK_0_LSB 0x240UL +#define QM_REGISTERS_VOQQMASK_0_MSB 0x244UL +#define QM_REGISTERS_VOQQMASK_10_LSB 0x290UL +#define QM_REGISTERS_VOQQMASK_10_MSB 0x294UL +#define QM_REGISTERS_VOQQMASK_11_LSB 0x298UL +#define QM_REGISTERS_VOQQMASK_11_MSB 0x29cUL +#define QM_REGISTERS_VOQQMASK_1_LSB 0x248UL +#define QM_REGISTERS_VOQQMASK_1_MSB 0x24cUL +#define QM_REGISTERS_VOQQMASK_2_LSB 0x250UL +#define QM_REGISTERS_VOQQMASK_2_MSB 0x254UL +#define QM_REGISTERS_VOQQMASK_3_LSB 0x258UL +#define QM_REGISTERS_VOQQMASK_3_MSB 0x25cUL +#define QM_REGISTERS_VOQQMASK_4_LSB 0x260UL +#define QM_REGISTERS_VOQQMASK_4_MSB 0x264UL +#define QM_REGISTERS_VOQQMASK_5_LSB 0x268UL +#define QM_REGISTERS_VOQQMASK_5_MSB 0x26cUL +#define QM_REGISTERS_VOQQMASK_6_LSB 0x270UL +#define QM_REGISTERS_VOQQMASK_6_MSB 0x274UL +#define QM_REGISTERS_VOQQMASK_7_LSB 0x278UL +#define QM_REGISTERS_VOQQMASK_7_MSB 0x27cUL +#define QM_REGISTERS_VOQQMASK_8_LSB 0x280UL +#define QM_REGISTERS_VOQQMASK_8_MSB 0x284UL +#define QM_REGISTERS_VOQQMASK_9_LSB 0x288UL +#define QM_REGISTERS_VOQQMASK_9_MSB 0x28cUL +#define QM_REGISTERS_WRRWEIGHTS_0 0x80cUL +#define QM_REGISTERS_WRRWEIGHTS_0_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_1 0x810UL +#define QM_REGISTERS_WRRWEIGHTS_1_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_10 0x814UL +#define QM_REGISTERS_WRRWEIGHTS_10_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_11 0x818UL +#define QM_REGISTERS_WRRWEIGHTS_11_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_12 0x81cUL +#define QM_REGISTERS_WRRWEIGHTS_12_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_13 0x820UL +#define QM_REGISTERS_WRRWEIGHTS_13_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_14 0x824UL +#define QM_REGISTERS_WRRWEIGHTS_14_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_15 0x828UL +#define QM_REGISTERS_WRRWEIGHTS_15_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_10 0x814UL +#define QM_REGISTERS_WRRWEIGHTS_10_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_11 0x818UL +#define QM_REGISTERS_WRRWEIGHTS_11_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_12 0x81cUL +#define QM_REGISTERS_WRRWEIGHTS_12_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_13 0x820UL +#define QM_REGISTERS_WRRWEIGHTS_13_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_14 0x824UL +#define QM_REGISTERS_WRRWEIGHTS_14_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_15 0x828UL +#define QM_REGISTERS_WRRWEIGHTS_15_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_2 0x82cUL +#define QM_REGISTERS_WRRWEIGHTS_2_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_3 0x830UL +#define QM_REGISTERS_WRRWEIGHTS_3_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_4 0x834UL +#define QM_REGISTERS_WRRWEIGHTS_4_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_5 0x838UL +#define QM_REGISTERS_WRRWEIGHTS_5_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_6 0x83cUL +#define QM_REGISTERS_WRRWEIGHTS_6_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_7 0x840UL +#define QM_REGISTERS_WRRWEIGHTS_7_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_8 0x844UL +#define QM_REGISTERS_WRRWEIGHTS_8_SIZE 1 +#define QM_REGISTERS_WRRWEIGHTS_9 0x848UL +#define QM_REGISTERS_WRRWEIGHTS_9_SIZE 1 +#define SRC_REGISTERS_COUNTFREE0 0x100UL +#define SRC_REGISTERS_COUNTFREE0_SIZE 1 +#define SRC_REGISTERS_FIRSTFREE0 0x110UL +#define SRC_REGISTERS_FIRSTFREE0_SIZE 2 +#define SRC_REGISTERS_KEYRSS0_0 0x8UL +#define SRC_REGISTERS_KEYRSS1_9 0x54UL +#define SRC_REGISTERS_LASTFREE0 0x130UL +#define SRC_REGISTERS_LASTFREE0_SIZE 2 +#define SRC_REGISTERS_NUMBER_HASH_BITS0 0x0UL +#define SRC_REGISTERS_SOFT_RST 0x9cUL +#define SRC_REGISTERS_SRC_INT_STS 0xacUL +#define SRC_REGISTERS_SRC_INT_STS_CLR 0xb0UL +#define SRC_REGISTERS_SRC_INT_STS_WR 0xb4UL +#define TCM_REGISTERS_CAM_OCCUP 0x17cUL +#define TCM_REGISTERS_CAM_OCCUP_ST 0x200UL +#define TCM_REGISTERS_CAM_OCCUP_ST_SIZE 1 +#define TCM_REGISTERS_CDU_AG_RD_IFEN 0x34UL +#define TCM_REGISTERS_CDU_AG_WR_IFEN 0x30UL +#define TCM_REGISTERS_CDU_SM_RD_IFEN 0x3cUL +#define TCM_REGISTERS_CDU_SM_WR_IFEN 0x38UL +#define TCM_REGISTERS_CFC_INIT_CRD 0x204UL +#define TCM_REGISTERS_CFC_INIT_CRD_SIZE 1 +#define TCM_REGISTERS_CP_WEIGHT 0xc0UL +#define TCM_REGISTERS_CSEM_IFEN 0x2cUL +#define TCM_REGISTERS_CSEM_LENGTH_MIS 0x174UL +#define TCM_REGISTERS_ERR_EVNT_ID 0xa0UL +#define TCM_REGISTERS_ERR_TCM_HDR 0x9cUL +#define TCM_REGISTERS_EXPR_EVNT_ID 0xa4UL +#define TCM_REGISTERS_FIC0_INIT_CRD 0x20cUL +#define TCM_REGISTERS_FIC0_INIT_CRD_SIZE 1 +#define TCM_REGISTERS_FIC1_INIT_CRD 0x210UL +#define TCM_REGISTERS_FIC1_INIT_CRD_SIZE 1 +#define TCM_REGISTERS_GR_ARB_TYPE 0x114UL +#define TCM_REGISTERS_GR_LD0_PR 0x11cUL +#define TCM_REGISTERS_GR_LD1_PR 0x120UL +#define TCM_REGISTERS_N_SM_CTX_LD_0 0x50UL +#define TCM_REGISTERS_N_SM_CTX_LD_1 0x54UL +#define TCM_REGISTERS_N_SM_CTX_LD_10 0x78UL +#define TCM_REGISTERS_N_SM_CTX_LD_11 0x7cUL +#define TCM_REGISTERS_N_SM_CTX_LD_12 0x80UL +#define TCM_REGISTERS_N_SM_CTX_LD_13 0x84UL +#define TCM_REGISTERS_N_SM_CTX_LD_14 0x88UL +#define TCM_REGISTERS_N_SM_CTX_LD_15 0x8cUL +#define TCM_REGISTERS_N_SM_CTX_LD_2 0x58UL +#define TCM_REGISTERS_N_SM_CTX_LD_3 0x5cUL +#define TCM_REGISTERS_N_SM_CTX_LD_4 0x60UL +#define TCM_REGISTERS_N_SM_CTX_LD_5 0x64UL +#define TCM_REGISTERS_N_SM_CTX_LD_6 0x68UL +#define TCM_REGISTERS_N_SM_CTX_LD_7 0x6cUL +#define TCM_REGISTERS_PBF_IFEN 0x24UL +#define TCM_REGISTERS_PBF_LENGTH_MIS 0x16cUL +#define TCM_REGISTERS_PBF_WEIGHT 0xb4UL +#define TCM_REGISTERS_PHYS_QNUM0_0 0xe0UL +#define TCM_REGISTERS_PHYS_QNUM0_1 0xe4UL +#define TCM_REGISTERS_PHYS_QNUM1_0 0xe8UL +#define TCM_REGISTERS_PHYS_QNUM1_1 0xecUL +#define TCM_REGISTERS_PHYS_QNUM2_0 0xf0UL +#define TCM_REGISTERS_PHYS_QNUM2_1 0xf4UL +#define TCM_REGISTERS_PHYS_QNUM3_0 0xf8UL +#define TCM_REGISTERS_PHYS_QNUM3_1 0xfcUL +#define TCM_REGISTERS_PRS_IFEN 0x20UL +#define TCM_REGISTERS_PRS_LENGTH_MIS 0x168UL +#define TCM_REGISTERS_PRS_WEIGHT 0xb0UL +#define TCM_REGISTERS_STOP_EVNT_ID 0xa8UL +#define TCM_REGISTERS_STORM_LENGTH_MIS 0x160UL +#define TCM_REGISTERS_STORM_TCM_IFEN 0x10UL +#define TCM_REGISTERS_TCM_CFC_IFEN 0x40UL +#define TCM_REGISTERS_TCM_INT_STS 0x1d0UL +#define TCM_REGISTERS_TCM_INT_STS_CLR 0x1d4UL +#define TCM_REGISTERS_TCM_INT_STS_WR 0x1d8UL +#define TCM_REGISTERS_TCM_REG0_SZ 0xd8UL +#define TCM_REGISTERS_TCM_STORM0_IFEN 0x4UL +#define TCM_REGISTERS_TCM_STORM1_IFEN 0x8UL +#define TCM_REGISTERS_TCM_TQM_IFEN 0xcUL +#define TCM_REGISTERS_TCM_TQM_USE_Q 0xd4UL +#define TCM_REGISTERS_TM_TCM_HDR 0x98UL +#define TCM_REGISTERS_TM_TCM_IFEN 0x1cUL +#define TCM_REGISTERS_TQM_INIT_CRD 0x21cUL +#define TCM_REGISTERS_TQM_INIT_CRD_SIZE 1 +#define TCM_REGISTERS_TQM_TCM_HDR_P 0x90UL +#define TCM_REGISTERS_TQM_TCM_HDR_S 0x94UL +#define TCM_REGISTERS_TQM_TCM_IFEN 0x14UL +#define TCM_REGISTERS_TSDM_IFEN 0x18UL +#define TCM_REGISTERS_TSDM_LENGTH_MIS 0x164UL +#define TCM_REGISTERS_TSDM_WEIGHT 0xc4UL +#define TCM_REGISTERS_USEM_IFEN 0x28UL +#define TCM_REGISTERS_USEM_LENGTH_MIS 0x170UL +#define TCM_REGISTERS_XX_DESCR_TABLE 0x280UL +#define TCM_REGISTERS_XX_DESCR_TABLE_SIZE 32 +#define TCM_REGISTERS_XX_INIT_CRD 0x220UL +#define TCM_REGISTERS_XX_INIT_CRD_SIZE 1 +#define TCM_REGISTERS_XX_MAX_LL_SZ 0x44UL +#define TCM_REGISTERS_XX_MSG_NUM 0x224UL +#define TCM_REGISTERS_XX_MSG_NUM_SIZE 1 +#define TCM_REGISTERS_XX_OVFL_EVNT_ID 0x48UL +#define TCM_REGISTERS_XX_TABLE 0x240UL +#define TCM_REGISTERS_XX_TABLE_SIZE 10 +#define TM_REGISTERS_CFC_AC_CRDCNT_VAL 0x208UL +#define TM_REGISTERS_CFC_AC_CRDCNT_VAL_SIZE 1 +#define TM_REGISTERS_CFC_CLD_CRDCNT_VAL 0x210UL +#define TM_REGISTERS_CFC_CLD_CRDCNT_VAL_SIZE 1 +#define TM_REGISTERS_CL0_CONT_REGION 0x30UL +#define TM_REGISTERS_CL1_CONT_REGION 0x34UL +#define TM_REGISTERS_CL2_CONT_REGION 0x38UL +#define TM_REGISTERS_CLIN_PRIOR0_CLIENT 0x24UL +#define TM_REGISTERS_CLIN_PRIOR1_CLIENT 0x28UL +#define TM_REGISTERS_CLOUT_CRDCNT0_VAL 0x220UL +#define TM_REGISTERS_CLOUT_CRDCNT0_VAL_SIZE 1 +#define TM_REGISTERS_CLOUT_CRDCNT1_VAL 0x228UL +#define TM_REGISTERS_CLOUT_CRDCNT1_VAL_SIZE 1 +#define TM_REGISTERS_CLOUT_CRDCNT2_VAL 0x230UL +#define TM_REGISTERS_CLOUT_CRDCNT2_VAL_SIZE 1 +#define TM_REGISTERS_EN_CL0_INPUT 0x8UL +#define TM_REGISTERS_EN_CL1_INPUT 0xcUL +#define TM_REGISTERS_EN_CL2_INPUT 0x10UL +#define TM_REGISTERS_EN_LINEAR0_TIMER 0x14UL +#define TM_REGISTERS_EN_LINEAR1_TIMER 0x18UL +#define TM_REGISTERS_EN_REAL_TIME_CNT 0xd8UL +#define TM_REGISTERS_EN_TIMERS 0x0UL +#define TM_REGISTERS_EXP_CRDCNT_VAL 0x238UL +#define TM_REGISTERS_EXP_CRDCNT_VAL_SIZE 1 +#define TM_REGISTERS_LIN0_MAX_ACTIVE_CID 0x48UL +#define TM_REGISTERS_LIN0_PHY_ADDR_VALID 0x248UL +#define TM_REGISTERS_LIN0_PHY_ADDR_VALID_SIZE 1 +#define TM_REGISTERS_LIN0_PHY_ADDR 0x270UL +#define TM_REGISTERS_LIN0_PHY_ADDR_SIZE 2 +#define TM_REGISTERS_LIN0_SCAN_TIME 0x3cUL +#define TM_REGISTERS_LIN1_PHY_ADDR_VALID 0x258UL +#define TM_REGISTERS_LIN1_PHY_ADDR_VALID_SIZE 1 +#define TM_REGISTERS_LIN1_PHY_ADDR 0x280UL +#define TM_REGISTERS_LIN1_PHY_ADDR_SIZE 2 +#define TM_REGISTERS_LIN_SETCLR_FIFO_ALFULL_THR 0x70UL +#define TM_REGISTERS_PCIARB_CRDCNT_VAL 0x260UL +#define TM_REGISTERS_PCIARB_CRDCNT_VAL_SIZE 1 +#define TM_REGISTERS_TIMER_SOFT_RST 0x4UL +#define TM_REGISTERS_TIMER_TICK_SIZE 0x1cUL +#define TM_REGISTERS_TM_CONTEXT_REGION 0x44UL +#define TM_REGISTERS_TM_INT_STS 0xf0UL +#define TM_REGISTERS_TM_INT_STS_CLR 0xf4UL +#define TM_REGISTERS_TM_INT_STS_WR 0xf8UL +#define TSDM_REGISTERS_AGG_INT_EVENT_0 0x38UL +#define TSDM_REGISTERS_AGG_INT_EVENT_1 0x3cUL +#define TSDM_REGISTERS_AGG_INT_EVENT_10 0x60UL +#define TSDM_REGISTERS_AGG_INT_EVENT_11 0x64UL +#define TSDM_REGISTERS_AGG_INT_EVENT_12 0x68UL +#define TSDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL +#define TSDM_REGISTERS_AGG_INT_EVENT_14 0x70UL +#define TSDM_REGISTERS_AGG_INT_EVENT_15 0x74UL +#define TSDM_REGISTERS_AGG_INT_EVENT_16 0x78UL +#define TSDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL +#define TSDM_REGISTERS_AGG_INT_EVENT_18 0x80UL +#define TSDM_REGISTERS_AGG_INT_EVENT_19 0x84UL +#define TSDM_REGISTERS_AGG_INT_EVENT_10 0x60UL +#define TSDM_REGISTERS_AGG_INT_EVENT_11 0x64UL +#define TSDM_REGISTERS_AGG_INT_EVENT_12 0x68UL +#define TSDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL +#define TSDM_REGISTERS_AGG_INT_EVENT_14 0x70UL +#define TSDM_REGISTERS_AGG_INT_EVENT_15 0x74UL +#define TSDM_REGISTERS_AGG_INT_EVENT_16 0x78UL +#define TSDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL +#define TSDM_REGISTERS_AGG_INT_EVENT_18 0x80UL +#define TSDM_REGISTERS_AGG_INT_EVENT_19 0x84UL +#define TSDM_REGISTERS_AGG_INT_EVENT_2 0x40UL +#define TSDM_REGISTERS_AGG_INT_EVENT_20 0x88UL +#define TSDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL +#define TSDM_REGISTERS_AGG_INT_EVENT_22 0x90UL +#define TSDM_REGISTERS_AGG_INT_EVENT_23 0x94UL +#define TSDM_REGISTERS_AGG_INT_EVENT_24 0x98UL +#define TSDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL +#define TSDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL +#define TSDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL +#define TSDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL +#define TSDM_REGISTERS_AGG_INT_EVENT_29 0xacUL +#define TSDM_REGISTERS_AGG_INT_EVENT_20 0x88UL +#define TSDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL +#define TSDM_REGISTERS_AGG_INT_EVENT_22 0x90UL +#define TSDM_REGISTERS_AGG_INT_EVENT_23 0x94UL +#define TSDM_REGISTERS_AGG_INT_EVENT_24 0x98UL +#define TSDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL +#define TSDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL +#define TSDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL +#define TSDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL +#define TSDM_REGISTERS_AGG_INT_EVENT_29 0xacUL +#define TSDM_REGISTERS_AGG_INT_EVENT_3 0x44UL +#define TSDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL +#define TSDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL +#define TSDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL +#define TSDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL +#define TSDM_REGISTERS_AGG_INT_EVENT_4 0x48UL +#define TSDM_REGISTERS_AGG_INT_EVENT_5 0x4cUL +#define TSDM_REGISTERS_AGG_INT_EVENT_6 0x50UL +#define TSDM_REGISTERS_AGG_INT_EVENT_7 0x54UL +#define TSDM_REGISTERS_AGG_INT_EVENT_8 0x58UL +#define TSDM_REGISTERS_AGG_INT_EVENT_9 0x5cUL +#define TSDM_REGISTERS_AGG_INT_FIC_0 0x138UL +#define TSDM_REGISTERS_AGG_INT_FIC_1 0x13cUL +#define TSDM_REGISTERS_AGG_INT_FIC_10 0x160UL +#define TSDM_REGISTERS_AGG_INT_FIC_11 0x164UL +#define TSDM_REGISTERS_AGG_INT_FIC_12 0x168UL +#define TSDM_REGISTERS_AGG_INT_FIC_13 0x16cUL +#define TSDM_REGISTERS_AGG_INT_FIC_14 0x170UL +#define TSDM_REGISTERS_AGG_INT_FIC_15 0x174UL +#define TSDM_REGISTERS_AGG_INT_FIC_16 0x178UL +#define TSDM_REGISTERS_AGG_INT_FIC_17 0x17cUL +#define TSDM_REGISTERS_AGG_INT_FIC_18 0x180UL +#define TSDM_REGISTERS_AGG_INT_FIC_19 0x184UL +#define TSDM_REGISTERS_AGG_INT_FIC_10 0x160UL +#define TSDM_REGISTERS_AGG_INT_FIC_11 0x164UL +#define TSDM_REGISTERS_AGG_INT_FIC_12 0x168UL +#define TSDM_REGISTERS_AGG_INT_FIC_13 0x16cUL +#define TSDM_REGISTERS_AGG_INT_FIC_14 0x170UL +#define TSDM_REGISTERS_AGG_INT_FIC_15 0x174UL +#define TSDM_REGISTERS_AGG_INT_FIC_16 0x178UL +#define TSDM_REGISTERS_AGG_INT_FIC_17 0x17cUL +#define TSDM_REGISTERS_AGG_INT_FIC_18 0x180UL +#define TSDM_REGISTERS_AGG_INT_FIC_19 0x184UL +#define TSDM_REGISTERS_AGG_INT_FIC_2 0x140UL +#define TSDM_REGISTERS_AGG_INT_FIC_20 0x188UL +#define TSDM_REGISTERS_AGG_INT_FIC_21 0x18cUL +#define TSDM_REGISTERS_AGG_INT_FIC_22 0x190UL +#define TSDM_REGISTERS_AGG_INT_FIC_23 0x194UL +#define TSDM_REGISTERS_AGG_INT_FIC_24 0x198UL +#define TSDM_REGISTERS_AGG_INT_FIC_25 0x19cUL +#define TSDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL +#define TSDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL +#define TSDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL +#define TSDM_REGISTERS_AGG_INT_FIC_29 0x1acUL +#define TSDM_REGISTERS_AGG_INT_FIC_20 0x188UL +#define TSDM_REGISTERS_AGG_INT_FIC_21 0x18cUL +#define TSDM_REGISTERS_AGG_INT_FIC_22 0x190UL +#define TSDM_REGISTERS_AGG_INT_FIC_23 0x194UL +#define TSDM_REGISTERS_AGG_INT_FIC_24 0x198UL +#define TSDM_REGISTERS_AGG_INT_FIC_25 0x19cUL +#define TSDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL +#define TSDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL +#define TSDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL +#define TSDM_REGISTERS_AGG_INT_FIC_29 0x1acUL +#define TSDM_REGISTERS_AGG_INT_FIC_3 0x144UL +#define TSDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL +#define TSDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL +#define TSDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL +#define TSDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL +#define TSDM_REGISTERS_AGG_INT_FIC_4 0x148UL +#define TSDM_REGISTERS_AGG_INT_FIC_5 0x14cUL +#define TSDM_REGISTERS_AGG_INT_FIC_6 0x150UL +#define TSDM_REGISTERS_AGG_INT_FIC_7 0x154UL +#define TSDM_REGISTERS_AGG_INT_FIC_8 0x158UL +#define TSDM_REGISTERS_AGG_INT_FIC_9 0x15cUL +#define TSDM_REGISTERS_AGG_INT_MODE_0 0x1b8UL +#define TSDM_REGISTERS_AGG_INT_MODE_1 0x1bcUL +#define TSDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL +#define TSDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL +#define TSDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL +#define TSDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL +#define TSDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL +#define TSDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL +#define TSDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL +#define TSDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL +#define TSDM_REGISTERS_AGG_INT_MODE_18 0x200UL +#define TSDM_REGISTERS_AGG_INT_MODE_19 0x204UL +#define TSDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL +#define TSDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL +#define TSDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL +#define TSDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL +#define TSDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL +#define TSDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL +#define TSDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL +#define TSDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL +#define TSDM_REGISTERS_AGG_INT_MODE_18 0x200UL +#define TSDM_REGISTERS_AGG_INT_MODE_19 0x204UL +#define TSDM_REGISTERS_AGG_INT_MODE_2 0x1c0UL +#define TSDM_REGISTERS_AGG_INT_MODE_20 0x208UL +#define TSDM_REGISTERS_AGG_INT_MODE_21 0x20cUL +#define TSDM_REGISTERS_AGG_INT_MODE_22 0x210UL +#define TSDM_REGISTERS_AGG_INT_MODE_23 0x214UL +#define TSDM_REGISTERS_AGG_INT_MODE_24 0x218UL +#define TSDM_REGISTERS_AGG_INT_MODE_25 0x21cUL +#define TSDM_REGISTERS_AGG_INT_MODE_26 0x220UL +#define TSDM_REGISTERS_AGG_INT_MODE_27 0x224UL +#define TSDM_REGISTERS_AGG_INT_MODE_28 0x228UL +#define TSDM_REGISTERS_AGG_INT_MODE_29 0x22cUL +#define TSDM_REGISTERS_AGG_INT_MODE_20 0x208UL +#define TSDM_REGISTERS_AGG_INT_MODE_21 0x20cUL +#define TSDM_REGISTERS_AGG_INT_MODE_22 0x210UL +#define TSDM_REGISTERS_AGG_INT_MODE_23 0x214UL +#define TSDM_REGISTERS_AGG_INT_MODE_24 0x218UL +#define TSDM_REGISTERS_AGG_INT_MODE_25 0x21cUL +#define TSDM_REGISTERS_AGG_INT_MODE_26 0x220UL +#define TSDM_REGISTERS_AGG_INT_MODE_27 0x224UL +#define TSDM_REGISTERS_AGG_INT_MODE_28 0x228UL +#define TSDM_REGISTERS_AGG_INT_MODE_29 0x22cUL +#define TSDM_REGISTERS_AGG_INT_MODE_3 0x1c4UL +#define TSDM_REGISTERS_AGG_INT_MODE_30 0x230UL +#define TSDM_REGISTERS_AGG_INT_MODE_31 0x234UL +#define TSDM_REGISTERS_AGG_INT_MODE_30 0x230UL +#define TSDM_REGISTERS_AGG_INT_MODE_31 0x234UL +#define TSDM_REGISTERS_AGG_INT_MODE_4 0x1c8UL +#define TSDM_REGISTERS_AGG_INT_MODE_5 0x1ccUL +#define TSDM_REGISTERS_AGG_INT_MODE_6 0x1d0UL +#define TSDM_REGISTERS_AGG_INT_MODE_7 0x1d4UL +#define TSDM_REGISTERS_AGG_INT_MODE_8 0x1d8UL +#define TSDM_REGISTERS_AGG_INT_MODE_9 0x1dcUL +#define TSDM_REGISTERS_AGG_INT_T_0 0xb8UL +#define TSDM_REGISTERS_AGG_INT_T_1 0xbcUL +#define TSDM_REGISTERS_AGG_INT_T_10 0xe0UL +#define TSDM_REGISTERS_AGG_INT_T_11 0xe4UL +#define TSDM_REGISTERS_AGG_INT_T_12 0xe8UL +#define TSDM_REGISTERS_AGG_INT_T_13 0xecUL +#define TSDM_REGISTERS_AGG_INT_T_14 0xf0UL +#define TSDM_REGISTERS_AGG_INT_T_15 0xf4UL +#define TSDM_REGISTERS_AGG_INT_T_16 0xf8UL +#define TSDM_REGISTERS_AGG_INT_T_17 0xfcUL +#define TSDM_REGISTERS_AGG_INT_T_18 0x100UL +#define TSDM_REGISTERS_AGG_INT_T_19 0x104UL +#define TSDM_REGISTERS_AGG_INT_T_10 0xe0UL +#define TSDM_REGISTERS_AGG_INT_T_11 0xe4UL +#define TSDM_REGISTERS_AGG_INT_T_12 0xe8UL +#define TSDM_REGISTERS_AGG_INT_T_13 0xecUL +#define TSDM_REGISTERS_AGG_INT_T_14 0xf0UL +#define TSDM_REGISTERS_AGG_INT_T_15 0xf4UL +#define TSDM_REGISTERS_AGG_INT_T_16 0xf8UL +#define TSDM_REGISTERS_AGG_INT_T_17 0xfcUL +#define TSDM_REGISTERS_AGG_INT_T_18 0x100UL +#define TSDM_REGISTERS_AGG_INT_T_19 0x104UL +#define TSDM_REGISTERS_AGG_INT_T_2 0xc0UL +#define TSDM_REGISTERS_AGG_INT_T_20 0x108UL +#define TSDM_REGISTERS_AGG_INT_T_21 0x10cUL +#define TSDM_REGISTERS_AGG_INT_T_22 0x110UL +#define TSDM_REGISTERS_AGG_INT_T_23 0x114UL +#define TSDM_REGISTERS_AGG_INT_T_24 0x118UL +#define TSDM_REGISTERS_AGG_INT_T_25 0x11cUL +#define TSDM_REGISTERS_AGG_INT_T_26 0x120UL +#define TSDM_REGISTERS_AGG_INT_T_27 0x124UL +#define TSDM_REGISTERS_AGG_INT_T_28 0x128UL +#define TSDM_REGISTERS_AGG_INT_T_29 0x12cUL +#define TSDM_REGISTERS_AGG_INT_T_20 0x108UL +#define TSDM_REGISTERS_AGG_INT_T_21 0x10cUL +#define TSDM_REGISTERS_AGG_INT_T_22 0x110UL +#define TSDM_REGISTERS_AGG_INT_T_23 0x114UL +#define TSDM_REGISTERS_AGG_INT_T_24 0x118UL +#define TSDM_REGISTERS_AGG_INT_T_25 0x11cUL +#define TSDM_REGISTERS_AGG_INT_T_26 0x120UL +#define TSDM_REGISTERS_AGG_INT_T_27 0x124UL +#define TSDM_REGISTERS_AGG_INT_T_28 0x128UL +#define TSDM_REGISTERS_AGG_INT_T_29 0x12cUL +#define TSDM_REGISTERS_AGG_INT_T_3 0xc4UL +#define TSDM_REGISTERS_AGG_INT_T_30 0x130UL +#define TSDM_REGISTERS_AGG_INT_T_31 0x134UL +#define TSDM_REGISTERS_AGG_INT_T_30 0x130UL +#define TSDM_REGISTERS_AGG_INT_T_31 0x134UL +#define TSDM_REGISTERS_AGG_INT_T_4 0xc8UL +#define TSDM_REGISTERS_AGG_INT_T_5 0xccUL +#define TSDM_REGISTERS_AGG_INT_T_6 0xd0UL +#define TSDM_REGISTERS_AGG_INT_T_7 0xd4UL +#define TSDM_REGISTERS_AGG_INT_T_8 0xd8UL +#define TSDM_REGISTERS_AGG_INT_T_9 0xdcUL +#define TSDM_REGISTERS_CFC_RSP_START_ADDR 0x8UL +#define TSDM_REGISTERS_CMP_COUNTER_MAX0 0x1cUL +#define TSDM_REGISTERS_CMP_COUNTER_MAX1 0x20UL +#define TSDM_REGISTERS_CMP_COUNTER_MAX2 0x24UL +#define TSDM_REGISTERS_CMP_COUNTER_MAX3 0x28UL +#define TSDM_REGISTERS_CMP_COUNTER_START_ADDR 0xcUL +#define TSDM_REGISTERS_ENABLE_IN1 0x238UL +#define TSDM_REGISTERS_ENABLE_IN2 0x23cUL +#define TSDM_REGISTERS_ENABLE_OUT1 0x240UL +#define TSDM_REGISTERS_ENABLE_OUT2 0x244UL +#define TSDM_REGISTERS_NUM_OF_ACK_AFTER_PLACE 0x27cUL +#define TSDM_REGISTERS_NUM_OF_PKT_END_MSG 0x274UL +#define TSDM_REGISTERS_NUM_OF_PXP_ASYNC_REQ 0x278UL +#define TSDM_REGISTERS_NUM_OF_Q0_CMD 0x248UL +#define TSDM_REGISTERS_NUM_OF_Q10_CMD 0x26cUL +#define TSDM_REGISTERS_NUM_OF_Q11_CMD 0x270UL +#define TSDM_REGISTERS_NUM_OF_Q1_CMD 0x24cUL +#define TSDM_REGISTERS_NUM_OF_Q3_CMD 0x250UL +#define TSDM_REGISTERS_NUM_OF_Q4_CMD 0x254UL +#define TSDM_REGISTERS_NUM_OF_Q5_CMD 0x258UL +#define TSDM_REGISTERS_NUM_OF_Q6_CMD 0x25cUL +#define TSDM_REGISTERS_NUM_OF_Q7_CMD 0x260UL +#define TSDM_REGISTERS_NUM_OF_Q8_CMD 0x264UL +#define TSDM_REGISTERS_NUM_OF_Q9_CMD 0x268UL +#define TSDM_REGISTERS_PCK_END_MSG_START_ADDR 0x14UL +#define TSDM_REGISTERS_Q_COUNTER_START_ADDR 0x10UL +#define TSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY 0x548UL +#define TSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY_SIZE 1 +#define TSDM_REGISTERS_SYNC_PARSER_EMPTY 0x550UL +#define TSDM_REGISTERS_SYNC_PARSER_EMPTY_SIZE 1 +#define TSDM_REGISTERS_SYNC_SYNC_EMPTY 0x558UL +#define TSDM_REGISTERS_SYNC_SYNC_EMPTY_SIZE 1 +#define TSDM_REGISTERS_TIMER_TICK 0x0UL +#define TSEM_REGISTERS_ARB_CYCLE_SIZE 0x34UL +#define TSEM_REGISTERS_ARB_ELEMENT0 0x20UL +#define TSEM_REGISTERS_ARB_ELEMENT1 0x24UL +#define TSEM_REGISTERS_ARB_ELEMENT2 0x28UL +#define TSEM_REGISTERS_ARB_ELEMENT3 0x2cUL +#define TSEM_REGISTERS_ARB_ELEMENT4 0x30UL +#define TSEM_REGISTERS_ENABLE_IN 0xa4UL +#define TSEM_REGISTERS_ENABLE_OUT 0xa8UL +#define TSEM_REGISTERS_FAST_MEMORY 0x20000UL +#define TSEM_REGISTERS_FAST_MEMORY_SIZE 32768 +#define TSEM_REGISTERS_FIC0_DISABLE 0x224UL +#define TSEM_REGISTERS_FIC0_DISABLE_SIZE 1 +#define TSEM_REGISTERS_FIC1_DISABLE 0x234UL +#define TSEM_REGISTERS_FIC1_DISABLE_SIZE 1 +#define TSEM_REGISTERS_INT_TABLE_TM 0xc4UL +#define TSEM_REGISTERS_INT_TABLE 0x400UL +#define TSEM_REGISTERS_INT_TABLE_SIZE 256 +#define TSEM_REGISTERS_MSG_NUM_FIC0 0x0UL +#define TSEM_REGISTERS_MSG_NUM_FIC1 0x4UL +#define TSEM_REGISTERS_MSG_NUM_FOC0 0x8UL +#define TSEM_REGISTERS_MSG_NUM_FOC1 0xcUL +#define TSEM_REGISTERS_MSG_NUM_FOC2 0x10UL +#define TSEM_REGISTERS_MSG_NUM_FOC3 0x14UL +#define TSEM_REGISTERS_PAS_DISABLE 0x24cUL +#define TSEM_REGISTERS_PAS_DISABLE_SIZE 1 +#define TSEM_REGISTERS_PASSIVE_BUFFER 0x1000UL +#define TSEM_REGISTERS_PASSIVE_BUFFER_SIZE 1024 +#define TSEM_REGISTERS_PRAM 0x40000UL +#define TSEM_REGISTERS_PRAM_SIZE 65536 +#define TSEM_REGISTERS_SLEEP_THREADS_VALID 0x26cUL +#define TSEM_REGISTERS_SLEEP_THREADS_VALID_SIZE 1 +#define TSEM_REGISTERS_SLOW_EXT_STORE_EMPTY 0x2a0UL +#define TSEM_REGISTERS_SLOW_EXT_STORE_EMPTY_SIZE 1 +#define TSEM_REGISTERS_THREADS_LIST 0x2e4UL +#define TSEM_REGISTERS_THREADS_LIST_SIZE 1 +#define TSEM_REGISTERS_TS_0_AS 0x38UL +#define TSEM_REGISTERS_TS_10_AS 0x60UL +#define TSEM_REGISTERS_TS_11_AS 0x64UL +#define TSEM_REGISTERS_TS_12_AS 0x68UL +#define TSEM_REGISTERS_TS_13_AS 0x6cUL +#define TSEM_REGISTERS_TS_14_AS 0x70UL +#define TSEM_REGISTERS_TS_15_AS 0x74UL +#define TSEM_REGISTERS_TS_16_AS 0x78UL +#define TSEM_REGISTERS_TS_17_AS 0x7cUL +#define TSEM_REGISTERS_TS_18_AS 0x80UL +#define TSEM_REGISTERS_TS_19_AS 0x84UL +#define TSEM_REGISTERS_TS_1_AS 0x3cUL +#define TSEM_REGISTERS_TS_2_AS 0x40UL +#define TSEM_REGISTERS_TS_3_AS 0x44UL +#define TSEM_REGISTERS_TS_4_AS 0x48UL +#define TSEM_REGISTERS_TS_5_AS 0x4cUL +#define TSEM_REGISTERS_TS_6_AS 0x50UL +#define TSEM_REGISTERS_TS_7_AS 0x54UL +#define TSEM_REGISTERS_TS_8_AS 0x58UL +#define TSEM_REGISTERS_TS_9_AS 0x5cUL +#define UCM_REGISTERS_CAM_OCCUP 0x170UL +#define UCM_REGISTERS_CAM_OCCUP_ST 0x200UL +#define UCM_REGISTERS_CAM_OCCUP_ST_SIZE 1 +#define UCM_REGISTERS_CDU_AG_RD_IFEN 0x38UL +#define UCM_REGISTERS_CDU_AG_WR_IFEN 0x34UL +#define UCM_REGISTERS_CDU_SM_RD_IFEN 0x40UL +#define UCM_REGISTERS_CDU_SM_WR_IFEN 0x3cUL +#define UCM_REGISTERS_CFC_INIT_CRD 0x204UL +#define UCM_REGISTERS_CFC_INIT_CRD_SIZE 1 +#define UCM_REGISTERS_CP_WEIGHT 0xc4UL +#define UCM_REGISTERS_CSEM_IFEN 0x28UL +#define UCM_REGISTERS_CSEM_LENGTH_MIS 0x160UL +#define UCM_REGISTERS_CSEM_WEIGHT 0xb8UL +#define UCM_REGISTERS_DORQ_IFEN 0x30UL +#define UCM_REGISTERS_DORQ_LENGTH_MIS 0x168UL +#define UCM_REGISTERS_ERR_EVNT_ID 0xa4UL +#define UCM_REGISTERS_ERR_UCM_HDR 0xa0UL +#define UCM_REGISTERS_EXPR_EVNT_ID 0xa8UL +#define UCM_REGISTERS_FIC0_INIT_CRD 0x20cUL +#define UCM_REGISTERS_FIC0_INIT_CRD_SIZE 1 +#define UCM_REGISTERS_FIC1_INIT_CRD 0x210UL +#define UCM_REGISTERS_FIC1_INIT_CRD_SIZE 1 +#define UCM_REGISTERS_GR_ARB_TYPE 0x144UL +#define UCM_REGISTERS_GR_LD0_PR 0x14cUL +#define UCM_REGISTERS_GR_LD1_PR 0x150UL +#define UCM_REGISTERS_INV_CFLG_Q 0xe4UL +#define UCM_REGISTERS_N_SM_CTX_LD_0 0x54UL +#define UCM_REGISTERS_N_SM_CTX_LD_1 0x58UL +#define UCM_REGISTERS_N_SM_CTX_LD_10 0x7cUL +#define UCM_REGISTERS_N_SM_CTX_LD_11 0x80UL +#define UCM_REGISTERS_N_SM_CTX_LD_12 0x84UL +#define UCM_REGISTERS_N_SM_CTX_LD_13 0x88UL +#define UCM_REGISTERS_N_SM_CTX_LD_14 0x8cUL +#define UCM_REGISTERS_N_SM_CTX_LD_15 0x90UL +#define UCM_REGISTERS_N_SM_CTX_LD_2 0x5cUL +#define UCM_REGISTERS_N_SM_CTX_LD_3 0x60UL +#define UCM_REGISTERS_N_SM_CTX_LD_4 0x64UL +#define UCM_REGISTERS_N_SM_CTX_LD_5 0x68UL +#define UCM_REGISTERS_N_SM_CTX_LD_6 0x6cUL +#define UCM_REGISTERS_N_SM_CTX_LD_7 0x70UL +#define UCM_REGISTERS_PHYS_QNUM0_0 0x110UL +#define UCM_REGISTERS_PHYS_QNUM0_1 0x114UL +#define UCM_REGISTERS_PHYS_QNUM1_0 0x118UL +#define UCM_REGISTERS_PHYS_QNUM1_1 0x11cUL +#define UCM_REGISTERS_STOP_EVNT_ID 0xacUL +#define UCM_REGISTERS_STORM_LENGTH_MIS 0x154UL +#define UCM_REGISTERS_STORM_UCM_IFEN 0x10UL +#define UCM_REGISTERS_TM_INIT_CRD 0x21cUL +#define UCM_REGISTERS_TM_INIT_CRD_SIZE 1 +#define UCM_REGISTERS_TM_UCM_HDR 0x9cUL +#define UCM_REGISTERS_TM_UCM_IFEN 0x1cUL +#define UCM_REGISTERS_TSEM_IFEN 0x24UL +#define UCM_REGISTERS_TSEM_LENGTH_MIS 0x15cUL +#define UCM_REGISTERS_TSEM_WEIGHT 0xb4UL +#define UCM_REGISTERS_UCM_CFC_IFEN 0x44UL +#define UCM_REGISTERS_UCM_INT_STS 0x1c8UL +#define UCM_REGISTERS_UCM_INT_STS_CLR 0x1ccUL +#define UCM_REGISTERS_UCM_INT_STS_WR 0x1d0UL +#define UCM_REGISTERS_UCM_REG0_SZ 0xdcUL +#define UCM_REGISTERS_UCM_STORM0_IFEN 0x4UL +#define UCM_REGISTERS_UCM_STORM1_IFEN 0x8UL +#define UCM_REGISTERS_UCM_TM_IFEN 0x20UL +#define UCM_REGISTERS_UCM_UQM_IFEN 0xcUL +#define UCM_REGISTERS_UCM_UQM_USE_Q 0xd8UL +#define UCM_REGISTERS_UQM_INIT_CRD 0x220UL +#define UCM_REGISTERS_UQM_INIT_CRD_SIZE 1 +#define UCM_REGISTERS_UQM_P_WEIGHT 0xccUL +#define UCM_REGISTERS_UQM_UCM_HDR_P 0x94UL +#define UCM_REGISTERS_UQM_UCM_HDR_S 0x98UL +#define UCM_REGISTERS_UQM_UCM_IFEN 0x14UL +#define UCM_REGISTERS_USDM_IFEN 0x18UL +#define UCM_REGISTERS_USDM_LENGTH_MIS 0x158UL +#define UCM_REGISTERS_XSEM_IFEN 0x2cUL +#define UCM_REGISTERS_XSEM_LENGTH_MIS 0x164UL +#define UCM_REGISTERS_XX_DESCR_TABLE 0x280UL +#define UCM_REGISTERS_XX_DESCR_TABLE_SIZE 32 +#define UCM_REGISTERS_XX_INIT_CRD 0x224UL +#define UCM_REGISTERS_XX_INIT_CRD_SIZE 1 +#define UCM_REGISTERS_XX_MSG_NUM 0x228UL +#define UCM_REGISTERS_XX_MSG_NUM_SIZE 1 +#define UCM_REGISTERS_XX_OVFL_EVNT_ID 0x4cUL +#define UCM_REGISTERS_XX_TABLE 0x300UL +#define UCM_REGISTERS_XX_TABLE_SIZE 18 +#define USDM_REGISTERS_AGG_INT_EVENT_0 0x38UL +#define USDM_REGISTERS_AGG_INT_EVENT_1 0x3cUL +#define USDM_REGISTERS_AGG_INT_EVENT_10 0x60UL +#define USDM_REGISTERS_AGG_INT_EVENT_11 0x64UL +#define USDM_REGISTERS_AGG_INT_EVENT_12 0x68UL +#define USDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL +#define USDM_REGISTERS_AGG_INT_EVENT_14 0x70UL +#define USDM_REGISTERS_AGG_INT_EVENT_15 0x74UL +#define USDM_REGISTERS_AGG_INT_EVENT_16 0x78UL +#define USDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL +#define USDM_REGISTERS_AGG_INT_EVENT_18 0x80UL +#define USDM_REGISTERS_AGG_INT_EVENT_19 0x84UL +#define USDM_REGISTERS_AGG_INT_EVENT_10 0x60UL +#define USDM_REGISTERS_AGG_INT_EVENT_11 0x64UL +#define USDM_REGISTERS_AGG_INT_EVENT_12 0x68UL +#define USDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL +#define USDM_REGISTERS_AGG_INT_EVENT_14 0x70UL +#define USDM_REGISTERS_AGG_INT_EVENT_15 0x74UL +#define USDM_REGISTERS_AGG_INT_EVENT_16 0x78UL +#define USDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL +#define USDM_REGISTERS_AGG_INT_EVENT_18 0x80UL +#define USDM_REGISTERS_AGG_INT_EVENT_19 0x84UL +#define USDM_REGISTERS_AGG_INT_EVENT_2 0x40UL +#define USDM_REGISTERS_AGG_INT_EVENT_20 0x88UL +#define USDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL +#define USDM_REGISTERS_AGG_INT_EVENT_22 0x90UL +#define USDM_REGISTERS_AGG_INT_EVENT_23 0x94UL +#define USDM_REGISTERS_AGG_INT_EVENT_24 0x98UL +#define USDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL +#define USDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL +#define USDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL +#define USDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL +#define USDM_REGISTERS_AGG_INT_EVENT_29 0xacUL +#define USDM_REGISTERS_AGG_INT_EVENT_20 0x88UL +#define USDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL +#define USDM_REGISTERS_AGG_INT_EVENT_22 0x90UL +#define USDM_REGISTERS_AGG_INT_EVENT_23 0x94UL +#define USDM_REGISTERS_AGG_INT_EVENT_24 0x98UL +#define USDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL +#define USDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL +#define USDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL +#define USDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL +#define USDM_REGISTERS_AGG_INT_EVENT_29 0xacUL +#define USDM_REGISTERS_AGG_INT_EVENT_3 0x44UL +#define USDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL +#define USDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL +#define USDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL +#define USDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL +#define USDM_REGISTERS_AGG_INT_EVENT_4 0x48UL +#define USDM_REGISTERS_AGG_INT_EVENT_5 0x4cUL +#define USDM_REGISTERS_AGG_INT_EVENT_6 0x50UL +#define USDM_REGISTERS_AGG_INT_EVENT_7 0x54UL +#define USDM_REGISTERS_AGG_INT_EVENT_8 0x58UL +#define USDM_REGISTERS_AGG_INT_EVENT_9 0x5cUL +#define USDM_REGISTERS_AGG_INT_FIC_0 0x138UL +#define USDM_REGISTERS_AGG_INT_FIC_1 0x13cUL +#define USDM_REGISTERS_AGG_INT_FIC_10 0x160UL +#define USDM_REGISTERS_AGG_INT_FIC_11 0x164UL +#define USDM_REGISTERS_AGG_INT_FIC_12 0x168UL +#define USDM_REGISTERS_AGG_INT_FIC_13 0x16cUL +#define USDM_REGISTERS_AGG_INT_FIC_14 0x170UL +#define USDM_REGISTERS_AGG_INT_FIC_15 0x174UL +#define USDM_REGISTERS_AGG_INT_FIC_16 0x178UL +#define USDM_REGISTERS_AGG_INT_FIC_17 0x17cUL +#define USDM_REGISTERS_AGG_INT_FIC_18 0x180UL +#define USDM_REGISTERS_AGG_INT_FIC_19 0x184UL +#define USDM_REGISTERS_AGG_INT_FIC_10 0x160UL +#define USDM_REGISTERS_AGG_INT_FIC_11 0x164UL +#define USDM_REGISTERS_AGG_INT_FIC_12 0x168UL +#define USDM_REGISTERS_AGG_INT_FIC_13 0x16cUL +#define USDM_REGISTERS_AGG_INT_FIC_14 0x170UL +#define USDM_REGISTERS_AGG_INT_FIC_15 0x174UL +#define USDM_REGISTERS_AGG_INT_FIC_16 0x178UL +#define USDM_REGISTERS_AGG_INT_FIC_17 0x17cUL +#define USDM_REGISTERS_AGG_INT_FIC_18 0x180UL +#define USDM_REGISTERS_AGG_INT_FIC_19 0x184UL +#define USDM_REGISTERS_AGG_INT_FIC_2 0x140UL +#define USDM_REGISTERS_AGG_INT_FIC_20 0x188UL +#define USDM_REGISTERS_AGG_INT_FIC_21 0x18cUL +#define USDM_REGISTERS_AGG_INT_FIC_22 0x190UL +#define USDM_REGISTERS_AGG_INT_FIC_23 0x194UL +#define USDM_REGISTERS_AGG_INT_FIC_24 0x198UL +#define USDM_REGISTERS_AGG_INT_FIC_25 0x19cUL +#define USDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL +#define USDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL +#define USDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL +#define USDM_REGISTERS_AGG_INT_FIC_29 0x1acUL +#define USDM_REGISTERS_AGG_INT_FIC_20 0x188UL +#define USDM_REGISTERS_AGG_INT_FIC_21 0x18cUL +#define USDM_REGISTERS_AGG_INT_FIC_22 0x190UL +#define USDM_REGISTERS_AGG_INT_FIC_23 0x194UL +#define USDM_REGISTERS_AGG_INT_FIC_24 0x198UL +#define USDM_REGISTERS_AGG_INT_FIC_25 0x19cUL +#define USDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL +#define USDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL +#define USDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL +#define USDM_REGISTERS_AGG_INT_FIC_29 0x1acUL +#define USDM_REGISTERS_AGG_INT_FIC_3 0x144UL +#define USDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL +#define USDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL +#define USDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL +#define USDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL +#define USDM_REGISTERS_AGG_INT_FIC_4 0x148UL +#define USDM_REGISTERS_AGG_INT_FIC_5 0x14cUL +#define USDM_REGISTERS_AGG_INT_FIC_6 0x150UL +#define USDM_REGISTERS_AGG_INT_FIC_7 0x154UL +#define USDM_REGISTERS_AGG_INT_FIC_8 0x158UL +#define USDM_REGISTERS_AGG_INT_FIC_9 0x15cUL +#define USDM_REGISTERS_AGG_INT_MODE_0 0x1b8UL +#define USDM_REGISTERS_AGG_INT_MODE_1 0x1bcUL +#define USDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL +#define USDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL +#define USDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL +#define USDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL +#define USDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL +#define USDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL +#define USDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL +#define USDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL +#define USDM_REGISTERS_AGG_INT_MODE_18 0x200UL +#define USDM_REGISTERS_AGG_INT_MODE_19 0x204UL +#define USDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL +#define USDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL +#define USDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL +#define USDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL +#define USDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL +#define USDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL +#define USDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL +#define USDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL +#define USDM_REGISTERS_AGG_INT_MODE_18 0x200UL +#define USDM_REGISTERS_AGG_INT_MODE_19 0x204UL +#define USDM_REGISTERS_AGG_INT_MODE_2 0x1c0UL +#define USDM_REGISTERS_AGG_INT_MODE_20 0x208UL +#define USDM_REGISTERS_AGG_INT_MODE_21 0x20cUL +#define USDM_REGISTERS_AGG_INT_MODE_22 0x210UL +#define USDM_REGISTERS_AGG_INT_MODE_23 0x214UL +#define USDM_REGISTERS_AGG_INT_MODE_24 0x218UL +#define USDM_REGISTERS_AGG_INT_MODE_25 0x21cUL +#define USDM_REGISTERS_AGG_INT_MODE_26 0x220UL +#define USDM_REGISTERS_AGG_INT_MODE_27 0x224UL +#define USDM_REGISTERS_AGG_INT_MODE_28 0x228UL +#define USDM_REGISTERS_AGG_INT_MODE_29 0x22cUL +#define USDM_REGISTERS_AGG_INT_MODE_20 0x208UL +#define USDM_REGISTERS_AGG_INT_MODE_21 0x20cUL +#define USDM_REGISTERS_AGG_INT_MODE_22 0x210UL +#define USDM_REGISTERS_AGG_INT_MODE_23 0x214UL +#define USDM_REGISTERS_AGG_INT_MODE_24 0x218UL +#define USDM_REGISTERS_AGG_INT_MODE_25 0x21cUL +#define USDM_REGISTERS_AGG_INT_MODE_26 0x220UL +#define USDM_REGISTERS_AGG_INT_MODE_27 0x224UL +#define USDM_REGISTERS_AGG_INT_MODE_28 0x228UL +#define USDM_REGISTERS_AGG_INT_MODE_29 0x22cUL +#define USDM_REGISTERS_AGG_INT_MODE_3 0x1c4UL +#define USDM_REGISTERS_AGG_INT_MODE_30 0x230UL +#define USDM_REGISTERS_AGG_INT_MODE_31 0x234UL +#define USDM_REGISTERS_AGG_INT_MODE_30 0x230UL +#define USDM_REGISTERS_AGG_INT_MODE_31 0x234UL +#define USDM_REGISTERS_AGG_INT_MODE_4 0x1c8UL +#define USDM_REGISTERS_AGG_INT_MODE_5 0x1ccUL +#define USDM_REGISTERS_AGG_INT_MODE_6 0x1d0UL +#define USDM_REGISTERS_AGG_INT_MODE_7 0x1d4UL +#define USDM_REGISTERS_AGG_INT_MODE_8 0x1d8UL +#define USDM_REGISTERS_AGG_INT_MODE_9 0x1dcUL +#define USDM_REGISTERS_AGG_INT_T_0 0xb8UL +#define USDM_REGISTERS_AGG_INT_T_1 0xbcUL +#define USDM_REGISTERS_AGG_INT_T_10 0xe0UL +#define USDM_REGISTERS_AGG_INT_T_11 0xe4UL +#define USDM_REGISTERS_AGG_INT_T_12 0xe8UL +#define USDM_REGISTERS_AGG_INT_T_13 0xecUL +#define USDM_REGISTERS_AGG_INT_T_14 0xf0UL +#define USDM_REGISTERS_AGG_INT_T_15 0xf4UL +#define USDM_REGISTERS_AGG_INT_T_16 0xf8UL +#define USDM_REGISTERS_AGG_INT_T_17 0xfcUL +#define USDM_REGISTERS_AGG_INT_T_18 0x100UL +#define USDM_REGISTERS_AGG_INT_T_19 0x104UL +#define USDM_REGISTERS_AGG_INT_T_10 0xe0UL +#define USDM_REGISTERS_AGG_INT_T_11 0xe4UL +#define USDM_REGISTERS_AGG_INT_T_12 0xe8UL +#define USDM_REGISTERS_AGG_INT_T_13 0xecUL +#define USDM_REGISTERS_AGG_INT_T_14 0xf0UL +#define USDM_REGISTERS_AGG_INT_T_15 0xf4UL +#define USDM_REGISTERS_AGG_INT_T_16 0xf8UL +#define USDM_REGISTERS_AGG_INT_T_17 0xfcUL +#define USDM_REGISTERS_AGG_INT_T_18 0x100UL +#define USDM_REGISTERS_AGG_INT_T_19 0x104UL +#define USDM_REGISTERS_AGG_INT_T_2 0xc0UL +#define USDM_REGISTERS_AGG_INT_T_20 0x108UL +#define USDM_REGISTERS_AGG_INT_T_21 0x10cUL +#define USDM_REGISTERS_AGG_INT_T_22 0x110UL +#define USDM_REGISTERS_AGG_INT_T_23 0x114UL +#define USDM_REGISTERS_AGG_INT_T_24 0x118UL +#define USDM_REGISTERS_AGG_INT_T_25 0x11cUL +#define USDM_REGISTERS_AGG_INT_T_26 0x120UL +#define USDM_REGISTERS_AGG_INT_T_27 0x124UL +#define USDM_REGISTERS_AGG_INT_T_28 0x128UL +#define USDM_REGISTERS_AGG_INT_T_29 0x12cUL +#define USDM_REGISTERS_AGG_INT_T_20 0x108UL +#define USDM_REGISTERS_AGG_INT_T_21 0x10cUL +#define USDM_REGISTERS_AGG_INT_T_22 0x110UL +#define USDM_REGISTERS_AGG_INT_T_23 0x114UL +#define USDM_REGISTERS_AGG_INT_T_24 0x118UL +#define USDM_REGISTERS_AGG_INT_T_25 0x11cUL +#define USDM_REGISTERS_AGG_INT_T_26 0x120UL +#define USDM_REGISTERS_AGG_INT_T_27 0x124UL +#define USDM_REGISTERS_AGG_INT_T_28 0x128UL +#define USDM_REGISTERS_AGG_INT_T_29 0x12cUL +#define USDM_REGISTERS_AGG_INT_T_3 0xc4UL +#define USDM_REGISTERS_AGG_INT_T_30 0x130UL +#define USDM_REGISTERS_AGG_INT_T_31 0x134UL +#define USDM_REGISTERS_AGG_INT_T_30 0x130UL +#define USDM_REGISTERS_AGG_INT_T_31 0x134UL +#define USDM_REGISTERS_AGG_INT_T_4 0xc8UL +#define USDM_REGISTERS_AGG_INT_T_5 0xccUL +#define USDM_REGISTERS_AGG_INT_T_6 0xd0UL +#define USDM_REGISTERS_AGG_INT_T_7 0xd4UL +#define USDM_REGISTERS_AGG_INT_T_8 0xd8UL +#define USDM_REGISTERS_AGG_INT_T_9 0xdcUL +#define USDM_REGISTERS_CFC_RSP_START_ADDR 0x8UL +#define USDM_REGISTERS_CMP_COUNTER_MAX0 0x1cUL +#define USDM_REGISTERS_CMP_COUNTER_MAX1 0x20UL +#define USDM_REGISTERS_CMP_COUNTER_MAX2 0x24UL +#define USDM_REGISTERS_CMP_COUNTER_MAX3 0x28UL +#define USDM_REGISTERS_CMP_COUNTER_START_ADDR 0xcUL +#define USDM_REGISTERS_ENABLE_IN1 0x238UL +#define USDM_REGISTERS_ENABLE_IN2 0x23cUL +#define USDM_REGISTERS_ENABLE_OUT1 0x240UL +#define USDM_REGISTERS_ENABLE_OUT2 0x244UL +#define USDM_REGISTERS_NUM_OF_ACK_AFTER_PLACE 0x280UL +#define USDM_REGISTERS_NUM_OF_PKT_END_MSG 0x278UL +#define USDM_REGISTERS_NUM_OF_PXP_ASYNC_REQ 0x27cUL +#define USDM_REGISTERS_NUM_OF_Q0_CMD 0x248UL +#define USDM_REGISTERS_NUM_OF_Q10_CMD 0x270UL +#define USDM_REGISTERS_NUM_OF_Q11_CMD 0x274UL +#define USDM_REGISTERS_NUM_OF_Q1_CMD 0x24cUL +#define USDM_REGISTERS_NUM_OF_Q2_CMD 0x250UL +#define USDM_REGISTERS_NUM_OF_Q3_CMD 0x254UL +#define USDM_REGISTERS_NUM_OF_Q4_CMD 0x258UL +#define USDM_REGISTERS_NUM_OF_Q5_CMD 0x25cUL +#define USDM_REGISTERS_NUM_OF_Q6_CMD 0x260UL +#define USDM_REGISTERS_NUM_OF_Q7_CMD 0x264UL +#define USDM_REGISTERS_NUM_OF_Q8_CMD 0x268UL +#define USDM_REGISTERS_NUM_OF_Q9_CMD 0x26cUL +#define USDM_REGISTERS_PCK_END_MSG_START_ADDR 0x14UL +#define USDM_REGISTERS_Q_COUNTER_START_ADDR 0x10UL +#define USDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY 0x550UL +#define USDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY_SIZE 1 +#define USDM_REGISTERS_SYNC_PARSER_EMPTY 0x558UL +#define USDM_REGISTERS_SYNC_PARSER_EMPTY_SIZE 1 +#define USDM_REGISTERS_SYNC_SYNC_EMPTY 0x560UL +#define USDM_REGISTERS_SYNC_SYNC_EMPTY_SIZE 1 +#define USDM_REGISTERS_TIMER_TICK 0x0UL +#define USEM_REGISTERS_ARB_CYCLE_SIZE 0x34UL +#define USEM_REGISTERS_ARB_ELEMENT0 0x20UL +#define USEM_REGISTERS_ARB_ELEMENT1 0x24UL +#define USEM_REGISTERS_ARB_ELEMENT2 0x28UL +#define USEM_REGISTERS_ARB_ELEMENT3 0x2cUL +#define USEM_REGISTERS_ARB_ELEMENT4 0x30UL +#define USEM_REGISTERS_ENABLE_IN 0xa4UL +#define USEM_REGISTERS_ENABLE_OUT 0xa8UL +#define USEM_REGISTERS_FAST_MEMORY 0x20000UL +#define USEM_REGISTERS_FAST_MEMORY_SIZE 32768 +#define USEM_REGISTERS_FIC0_DISABLE 0x224UL +#define USEM_REGISTERS_FIC0_DISABLE_SIZE 1 +#define USEM_REGISTERS_FIC1_DISABLE 0x234UL +#define USEM_REGISTERS_FIC1_DISABLE_SIZE 1 +#define USEM_REGISTERS_INT_TABLE_TM 0xd4UL +#define USEM_REGISTERS_INT_TABLE 0x400UL +#define USEM_REGISTERS_INT_TABLE_SIZE 256 +#define USEM_REGISTERS_MSG_NUM_FIC0 0x0UL +#define USEM_REGISTERS_MSG_NUM_FIC1 0x4UL +#define USEM_REGISTERS_MSG_NUM_FOC0 0x8UL +#define USEM_REGISTERS_MSG_NUM_FOC1 0xcUL +#define USEM_REGISTERS_MSG_NUM_FOC2 0x10UL +#define USEM_REGISTERS_MSG_NUM_FOC3 0x14UL +#define USEM_REGISTERS_PAS_DISABLE 0x24cUL +#define USEM_REGISTERS_PAS_DISABLE_SIZE 1 +#define USEM_REGISTERS_PASSIVE_BUFFER 0x2000UL +#define USEM_REGISTERS_PASSIVE_BUFFER_SIZE 2048 +#define USEM_REGISTERS_PRAM 0x40000UL +#define USEM_REGISTERS_PRAM_SIZE 65536 +#define USEM_REGISTERS_SLEEP_THREADS_VALID 0x26cUL +#define USEM_REGISTERS_SLEEP_THREADS_VALID_SIZE 1 +#define USEM_REGISTERS_SLOW_EXT_STORE_EMPTY 0x2a0UL +#define USEM_REGISTERS_SLOW_EXT_STORE_EMPTY_SIZE 1 +#define USEM_REGISTERS_THREADS_LIST 0x2e4UL +#define USEM_REGISTERS_THREADS_LIST_SIZE 1 +#define USEM_REGISTERS_TS_0_AS 0x38UL +#define USEM_REGISTERS_TS_10_AS 0x60UL +#define USEM_REGISTERS_TS_11_AS 0x64UL +#define USEM_REGISTERS_TS_12_AS 0x68UL +#define USEM_REGISTERS_TS_13_AS 0x6cUL +#define USEM_REGISTERS_TS_14_AS 0x70UL +#define USEM_REGISTERS_TS_15_AS 0x74UL +#define USEM_REGISTERS_TS_16_AS 0x78UL +#define USEM_REGISTERS_TS_17_AS 0x7cUL +#define USEM_REGISTERS_TS_18_AS 0x80UL +#define USEM_REGISTERS_TS_19_AS 0x84UL +#define USEM_REGISTERS_TS_1_AS 0x3cUL +#define USEM_REGISTERS_TS_2_AS 0x40UL +#define USEM_REGISTERS_TS_3_AS 0x44UL +#define USEM_REGISTERS_TS_4_AS 0x48UL +#define USEM_REGISTERS_TS_5_AS 0x4cUL +#define USEM_REGISTERS_TS_6_AS 0x50UL +#define USEM_REGISTERS_TS_7_AS 0x54UL +#define USEM_REGISTERS_TS_8_AS 0x58UL +#define USEM_REGISTERS_TS_9_AS 0x5cUL +#define XCM_REGISTERS_AUX1_Q 0x134UL +#define XCM_REGISTERS_AUX_CNT_FLG_Q_19 0x1b0UL +#define XCM_REGISTERS_CAM_OCCUP 0x244UL +#define XCM_REGISTERS_CAM_OCCUP_ST 0x400UL +#define XCM_REGISTERS_CAM_OCCUP_ST_SIZE 1 +#define XCM_REGISTERS_CDU_AG_RD_IFEN 0x44UL +#define XCM_REGISTERS_CDU_AG_WR_IFEN 0x40UL +#define XCM_REGISTERS_CDU_SM_RD_IFEN 0x4cUL +#define XCM_REGISTERS_CDU_SM_WR_IFEN 0x48UL +#define XCM_REGISTERS_CFC_INIT_CRD 0x404UL +#define XCM_REGISTERS_CFC_INIT_CRD_SIZE 1 +#define XCM_REGISTERS_CP_WEIGHT 0xdcUL +#define XCM_REGISTERS_CSEM_IFEN 0x28UL +#define XCM_REGISTERS_CSEM_LENGTH_MIS 0x228UL +#define XCM_REGISTERS_CSEM_WEIGHT 0xc4UL +#define XCM_REGISTERS_DORQ_IFEN 0x30UL +#define XCM_REGISTERS_DORQ_LENGTH_MIS 0x230UL +#define XCM_REGISTERS_ERR_EVNT_ID 0xb0UL +#define XCM_REGISTERS_ERR_XCM_HDR 0xacUL +#define XCM_REGISTERS_EXPR_EVNT_ID 0xb4UL +#define XCM_REGISTERS_FIC0_INIT_CRD 0x40cUL +#define XCM_REGISTERS_FIC0_INIT_CRD_SIZE 1 +#define XCM_REGISTERS_FIC1_INIT_CRD 0x410UL +#define XCM_REGISTERS_FIC1_INIT_CRD_SIZE 1 +#define XCM_REGISTERS_GLB_DEL_ACK_MAX_CNT_0 0x118UL +#define XCM_REGISTERS_GLB_DEL_ACK_MAX_CNT_1 0x11cUL +#define XCM_REGISTERS_GLB_DEL_ACK_TMR_VAL_0 0x108UL +#define XCM_REGISTERS_GLB_DEL_ACK_TMR_VAL_1 0x10cUL +#define XCM_REGISTERS_GR_ARB_TYPE 0x20cUL +#define XCM_REGISTERS_GR_LD0_PR 0x214UL +#define XCM_REGISTERS_GR_LD1_PR 0x218UL +#define XCM_REGISTERS_NIG0_IFEN 0x38UL +#define XCM_REGISTERS_NIG0_LENGTH_MIS 0x238UL +#define XCM_REGISTERS_NIG1_IFEN 0x3cUL +#define XCM_REGISTERS_NIG1_LENGTH_MIS 0x23cUL +#define XCM_REGISTERS_NIG1_WEIGHT 0xd8UL +#define XCM_REGISTERS_N_SM_CTX_LD_0 0x60UL +#define XCM_REGISTERS_N_SM_CTX_LD_1 0x64UL +#define XCM_REGISTERS_N_SM_CTX_LD_10 0x88UL +#define XCM_REGISTERS_N_SM_CTX_LD_11 0x8cUL +#define XCM_REGISTERS_N_SM_CTX_LD_12 0x90UL +#define XCM_REGISTERS_N_SM_CTX_LD_13 0x94UL +#define XCM_REGISTERS_N_SM_CTX_LD_14 0x98UL +#define XCM_REGISTERS_N_SM_CTX_LD_15 0x9cUL +#define XCM_REGISTERS_N_SM_CTX_LD_2 0x68UL +#define XCM_REGISTERS_N_SM_CTX_LD_3 0x6cUL +#define XCM_REGISTERS_N_SM_CTX_LD_4 0x70UL +#define XCM_REGISTERS_N_SM_CTX_LD_5 0x74UL +#define XCM_REGISTERS_N_SM_CTX_LD_6 0x78UL +#define XCM_REGISTERS_N_SM_CTX_LD_7 0x7cUL +#define XCM_REGISTERS_PBF_IFEN 0x34UL +#define XCM_REGISTERS_PBF_LENGTH_MIS 0x234UL +#define XCM_REGISTERS_PBF_WEIGHT 0xd0UL +#define XCM_REGISTERS_STOP_EVNT_ID 0xb8UL +#define XCM_REGISTERS_STORM_LENGTH_MIS 0x21cUL +#define XCM_REGISTERS_STORM_WEIGHT 0xbcUL +#define XCM_REGISTERS_STORM_XCM_IFEN 0x10UL +#define XCM_REGISTERS_TM_INIT_CRD 0x41cUL +#define XCM_REGISTERS_TM_INIT_CRD_SIZE 1 +#define XCM_REGISTERS_TM_XCM_HDR 0xa8UL +#define XCM_REGISTERS_TM_XCM_IFEN 0x1cUL +#define XCM_REGISTERS_TSEM_IFEN 0x24UL +#define XCM_REGISTERS_TSEM_LENGTH_MIS 0x224UL +#define XCM_REGISTERS_TSEM_WEIGHT 0xc0UL +#define XCM_REGISTERS_UNA_GT_NXT_Q 0x120UL +#define XCM_REGISTERS_USEM_IFEN 0x2cUL +#define XCM_REGISTERS_USEM_LENGTH_MIS 0x22cUL +#define XCM_REGISTERS_USEM_WEIGHT 0xc8UL +#define XCM_REGISTERS_WU_DA_CNT_CMD00 0x1d4UL +#define XCM_REGISTERS_WU_DA_CNT_CMD01 0x1d8UL +#define XCM_REGISTERS_WU_DA_CNT_CMD10 0x1dcUL +#define XCM_REGISTERS_WU_DA_CNT_CMD11 0x1e0UL +#define XCM_REGISTERS_WU_DA_CNT_UPD_VAL00 0x1e4UL +#define XCM_REGISTERS_WU_DA_CNT_UPD_VAL01 0x1e8UL +#define XCM_REGISTERS_WU_DA_CNT_UPD_VAL10 0x1ecUL +#define XCM_REGISTERS_WU_DA_CNT_UPD_VAL11 0x1f0UL +#define XCM_REGISTERS_WU_DA_SET_TMR_CNT_FLG_CMD00 0x1c4UL +#define XCM_REGISTERS_WU_DA_SET_TMR_CNT_FLG_CMD01 0x1c8UL +#define XCM_REGISTERS_WU_DA_SET_TMR_CNT_FLG_CMD10 0x1ccUL +#define XCM_REGISTERS_WU_DA_SET_TMR_CNT_FLG_CMD11 0x1d0UL +#define XCM_REGISTERS_XCM_CFC_IFEN 0x50UL +#define XCM_REGISTERS_XCM_INT_STS 0x2a8UL +#define XCM_REGISTERS_XCM_INT_STS_CLR 0x2acUL +#define XCM_REGISTERS_XCM_INT_STS_WR 0x2b0UL +#define XCM_REGISTERS_XCM_REG0_SZ 0xf4UL +#define XCM_REGISTERS_XCM_STORM0_IFEN 0x4UL +#define XCM_REGISTERS_XCM_STORM1_IFEN 0x8UL +#define XCM_REGISTERS_XCM_TM_IFEN 0x20UL +#define XCM_REGISTERS_XCM_XQM_IFEN 0xcUL +#define XCM_REGISTERS_XCM_XQM_USE_Q 0xf0UL +#define XCM_REGISTERS_XQM_BYP_ACT_UPD 0xfcUL +#define XCM_REGISTERS_XQM_INIT_CRD 0x420UL +#define XCM_REGISTERS_XQM_INIT_CRD_SIZE 1 +#define XCM_REGISTERS_XQM_P_WEIGHT 0xe4UL +#define XCM_REGISTERS_XQM_XCM_HDR_P 0xa0UL +#define XCM_REGISTERS_XQM_XCM_HDR_S 0xa4UL +#define XCM_REGISTERS_XQM_XCM_IFEN 0x14UL +#define XCM_REGISTERS_XSDM_IFEN 0x18UL +#define XCM_REGISTERS_XSDM_LENGTH_MIS 0x220UL +#define XCM_REGISTERS_XSDM_WEIGHT 0xe0UL +#define XCM_REGISTERS_XX_DESCR_TABLE 0x480UL +#define XCM_REGISTERS_XX_DESCR_TABLE_SIZE 32 +#define XCM_REGISTERS_XX_INIT_CRD 0x424UL +#define XCM_REGISTERS_XX_INIT_CRD_SIZE 1 +#define XCM_REGISTERS_XX_MSG_NUM 0x428UL +#define XCM_REGISTERS_XX_MSG_NUM_SIZE 1 +#define XCM_REGISTERS_XX_OVFL_EVNT_ID 0x58UL +#define XCM_REGISTERS_XX_TABLE 0x500UL +#define XCM_REGISTERS_XX_TABLE_SIZE 18 +#define XSDM_REGISTERS_AGG_INT_EVENT_0 0x38UL +#define XSDM_REGISTERS_AGG_INT_EVENT_1 0x3cUL +#define XSDM_REGISTERS_AGG_INT_EVENT_10 0x60UL +#define XSDM_REGISTERS_AGG_INT_EVENT_11 0x64UL +#define XSDM_REGISTERS_AGG_INT_EVENT_12 0x68UL +#define XSDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL +#define XSDM_REGISTERS_AGG_INT_EVENT_14 0x70UL +#define XSDM_REGISTERS_AGG_INT_EVENT_15 0x74UL +#define XSDM_REGISTERS_AGG_INT_EVENT_16 0x78UL +#define XSDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL +#define XSDM_REGISTERS_AGG_INT_EVENT_18 0x80UL +#define XSDM_REGISTERS_AGG_INT_EVENT_19 0x84UL +#define XSDM_REGISTERS_AGG_INT_EVENT_10 0x60UL +#define XSDM_REGISTERS_AGG_INT_EVENT_11 0x64UL +#define XSDM_REGISTERS_AGG_INT_EVENT_12 0x68UL +#define XSDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL +#define XSDM_REGISTERS_AGG_INT_EVENT_14 0x70UL +#define XSDM_REGISTERS_AGG_INT_EVENT_15 0x74UL +#define XSDM_REGISTERS_AGG_INT_EVENT_16 0x78UL +#define XSDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL +#define XSDM_REGISTERS_AGG_INT_EVENT_18 0x80UL +#define XSDM_REGISTERS_AGG_INT_EVENT_19 0x84UL +#define XSDM_REGISTERS_AGG_INT_EVENT_2 0x40UL +#define XSDM_REGISTERS_AGG_INT_EVENT_20 0x88UL +#define XSDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL +#define XSDM_REGISTERS_AGG_INT_EVENT_22 0x90UL +#define XSDM_REGISTERS_AGG_INT_EVENT_23 0x94UL +#define XSDM_REGISTERS_AGG_INT_EVENT_24 0x98UL +#define XSDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL +#define XSDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL +#define XSDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL +#define XSDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL +#define XSDM_REGISTERS_AGG_INT_EVENT_29 0xacUL +#define XSDM_REGISTERS_AGG_INT_EVENT_20 0x88UL +#define XSDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL +#define XSDM_REGISTERS_AGG_INT_EVENT_22 0x90UL +#define XSDM_REGISTERS_AGG_INT_EVENT_23 0x94UL +#define XSDM_REGISTERS_AGG_INT_EVENT_24 0x98UL +#define XSDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL +#define XSDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL +#define XSDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL +#define XSDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL +#define XSDM_REGISTERS_AGG_INT_EVENT_29 0xacUL +#define XSDM_REGISTERS_AGG_INT_EVENT_3 0x44UL +#define XSDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL +#define XSDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL +#define XSDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL +#define XSDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL +#define XSDM_REGISTERS_AGG_INT_EVENT_4 0x48UL +#define XSDM_REGISTERS_AGG_INT_EVENT_5 0x4cUL +#define XSDM_REGISTERS_AGG_INT_EVENT_6 0x50UL +#define XSDM_REGISTERS_AGG_INT_EVENT_7 0x54UL +#define XSDM_REGISTERS_AGG_INT_EVENT_8 0x58UL +#define XSDM_REGISTERS_AGG_INT_EVENT_9 0x5cUL +#define XSDM_REGISTERS_AGG_INT_FIC_0 0x138UL +#define XSDM_REGISTERS_AGG_INT_FIC_1 0x13cUL +#define XSDM_REGISTERS_AGG_INT_FIC_10 0x160UL +#define XSDM_REGISTERS_AGG_INT_FIC_11 0x164UL +#define XSDM_REGISTERS_AGG_INT_FIC_12 0x168UL +#define XSDM_REGISTERS_AGG_INT_FIC_13 0x16cUL +#define XSDM_REGISTERS_AGG_INT_FIC_14 0x170UL +#define XSDM_REGISTERS_AGG_INT_FIC_15 0x174UL +#define XSDM_REGISTERS_AGG_INT_FIC_16 0x178UL +#define XSDM_REGISTERS_AGG_INT_FIC_17 0x17cUL +#define XSDM_REGISTERS_AGG_INT_FIC_18 0x180UL +#define XSDM_REGISTERS_AGG_INT_FIC_19 0x184UL +#define XSDM_REGISTERS_AGG_INT_FIC_10 0x160UL +#define XSDM_REGISTERS_AGG_INT_FIC_11 0x164UL +#define XSDM_REGISTERS_AGG_INT_FIC_12 0x168UL +#define XSDM_REGISTERS_AGG_INT_FIC_13 0x16cUL +#define XSDM_REGISTERS_AGG_INT_FIC_14 0x170UL +#define XSDM_REGISTERS_AGG_INT_FIC_15 0x174UL +#define XSDM_REGISTERS_AGG_INT_FIC_16 0x178UL +#define XSDM_REGISTERS_AGG_INT_FIC_17 0x17cUL +#define XSDM_REGISTERS_AGG_INT_FIC_18 0x180UL +#define XSDM_REGISTERS_AGG_INT_FIC_19 0x184UL +#define XSDM_REGISTERS_AGG_INT_FIC_2 0x140UL +#define XSDM_REGISTERS_AGG_INT_FIC_20 0x188UL +#define XSDM_REGISTERS_AGG_INT_FIC_21 0x18cUL +#define XSDM_REGISTERS_AGG_INT_FIC_22 0x190UL +#define XSDM_REGISTERS_AGG_INT_FIC_23 0x194UL +#define XSDM_REGISTERS_AGG_INT_FIC_24 0x198UL +#define XSDM_REGISTERS_AGG_INT_FIC_25 0x19cUL +#define XSDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL +#define XSDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL +#define XSDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL +#define XSDM_REGISTERS_AGG_INT_FIC_29 0x1acUL +#define XSDM_REGISTERS_AGG_INT_FIC_20 0x188UL +#define XSDM_REGISTERS_AGG_INT_FIC_21 0x18cUL +#define XSDM_REGISTERS_AGG_INT_FIC_22 0x190UL +#define XSDM_REGISTERS_AGG_INT_FIC_23 0x194UL +#define XSDM_REGISTERS_AGG_INT_FIC_24 0x198UL +#define XSDM_REGISTERS_AGG_INT_FIC_25 0x19cUL +#define XSDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL +#define XSDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL +#define XSDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL +#define XSDM_REGISTERS_AGG_INT_FIC_29 0x1acUL +#define XSDM_REGISTERS_AGG_INT_FIC_3 0x144UL +#define XSDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL +#define XSDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL +#define XSDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL +#define XSDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL +#define XSDM_REGISTERS_AGG_INT_FIC_4 0x148UL +#define XSDM_REGISTERS_AGG_INT_FIC_5 0x14cUL +#define XSDM_REGISTERS_AGG_INT_FIC_6 0x150UL +#define XSDM_REGISTERS_AGG_INT_FIC_7 0x154UL +#define XSDM_REGISTERS_AGG_INT_FIC_8 0x158UL +#define XSDM_REGISTERS_AGG_INT_FIC_9 0x15cUL +#define XSDM_REGISTERS_AGG_INT_MODE_0 0x1b8UL +#define XSDM_REGISTERS_AGG_INT_MODE_1 0x1bcUL +#define XSDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL +#define XSDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL +#define XSDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL +#define XSDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL +#define XSDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL +#define XSDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL +#define XSDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL +#define XSDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL +#define XSDM_REGISTERS_AGG_INT_MODE_18 0x200UL +#define XSDM_REGISTERS_AGG_INT_MODE_19 0x204UL +#define XSDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL +#define XSDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL +#define XSDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL +#define XSDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL +#define XSDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL +#define XSDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL +#define XSDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL +#define XSDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL +#define XSDM_REGISTERS_AGG_INT_MODE_18 0x200UL +#define XSDM_REGISTERS_AGG_INT_MODE_19 0x204UL +#define XSDM_REGISTERS_AGG_INT_MODE_2 0x1c0UL +#define XSDM_REGISTERS_AGG_INT_MODE_20 0x208UL +#define XSDM_REGISTERS_AGG_INT_MODE_21 0x20cUL +#define XSDM_REGISTERS_AGG_INT_MODE_22 0x210UL +#define XSDM_REGISTERS_AGG_INT_MODE_23 0x214UL +#define XSDM_REGISTERS_AGG_INT_MODE_24 0x218UL +#define XSDM_REGISTERS_AGG_INT_MODE_25 0x21cUL +#define XSDM_REGISTERS_AGG_INT_MODE_26 0x220UL +#define XSDM_REGISTERS_AGG_INT_MODE_27 0x224UL +#define XSDM_REGISTERS_AGG_INT_MODE_28 0x228UL +#define XSDM_REGISTERS_AGG_INT_MODE_29 0x22cUL +#define XSDM_REGISTERS_AGG_INT_MODE_20 0x208UL +#define XSDM_REGISTERS_AGG_INT_MODE_21 0x20cUL +#define XSDM_REGISTERS_AGG_INT_MODE_22 0x210UL +#define XSDM_REGISTERS_AGG_INT_MODE_23 0x214UL +#define XSDM_REGISTERS_AGG_INT_MODE_24 0x218UL +#define XSDM_REGISTERS_AGG_INT_MODE_25 0x21cUL +#define XSDM_REGISTERS_AGG_INT_MODE_26 0x220UL +#define XSDM_REGISTERS_AGG_INT_MODE_27 0x224UL +#define XSDM_REGISTERS_AGG_INT_MODE_28 0x228UL +#define XSDM_REGISTERS_AGG_INT_MODE_29 0x22cUL +#define XSDM_REGISTERS_AGG_INT_MODE_3 0x1c4UL +#define XSDM_REGISTERS_AGG_INT_MODE_30 0x230UL +#define XSDM_REGISTERS_AGG_INT_MODE_31 0x234UL +#define XSDM_REGISTERS_AGG_INT_MODE_30 0x230UL +#define XSDM_REGISTERS_AGG_INT_MODE_31 0x234UL +#define XSDM_REGISTERS_AGG_INT_MODE_4 0x1c8UL +#define XSDM_REGISTERS_AGG_INT_MODE_5 0x1ccUL +#define XSDM_REGISTERS_AGG_INT_MODE_6 0x1d0UL +#define XSDM_REGISTERS_AGG_INT_MODE_7 0x1d4UL +#define XSDM_REGISTERS_AGG_INT_MODE_8 0x1d8UL +#define XSDM_REGISTERS_AGG_INT_MODE_9 0x1dcUL +#define XSDM_REGISTERS_AGG_INT_T_0 0xb8UL +#define XSDM_REGISTERS_AGG_INT_T_1 0xbcUL +#define XSDM_REGISTERS_AGG_INT_T_10 0xe0UL +#define XSDM_REGISTERS_AGG_INT_T_11 0xe4UL +#define XSDM_REGISTERS_AGG_INT_T_12 0xe8UL +#define XSDM_REGISTERS_AGG_INT_T_13 0xecUL +#define XSDM_REGISTERS_AGG_INT_T_14 0xf0UL +#define XSDM_REGISTERS_AGG_INT_T_15 0xf4UL +#define XSDM_REGISTERS_AGG_INT_T_16 0xf8UL +#define XSDM_REGISTERS_AGG_INT_T_17 0xfcUL +#define XSDM_REGISTERS_AGG_INT_T_18 0x100UL +#define XSDM_REGISTERS_AGG_INT_T_19 0x104UL +#define XSDM_REGISTERS_AGG_INT_T_10 0xe0UL +#define XSDM_REGISTERS_AGG_INT_T_11 0xe4UL +#define XSDM_REGISTERS_AGG_INT_T_12 0xe8UL +#define XSDM_REGISTERS_AGG_INT_T_13 0xecUL +#define XSDM_REGISTERS_AGG_INT_T_14 0xf0UL +#define XSDM_REGISTERS_AGG_INT_T_15 0xf4UL +#define XSDM_REGISTERS_AGG_INT_T_16 0xf8UL +#define XSDM_REGISTERS_AGG_INT_T_17 0xfcUL +#define XSDM_REGISTERS_AGG_INT_T_18 0x100UL +#define XSDM_REGISTERS_AGG_INT_T_19 0x104UL +#define XSDM_REGISTERS_AGG_INT_T_2 0xc0UL +#define XSDM_REGISTERS_AGG_INT_T_20 0x108UL +#define XSDM_REGISTERS_AGG_INT_T_21 0x10cUL +#define XSDM_REGISTERS_AGG_INT_T_22 0x110UL +#define XSDM_REGISTERS_AGG_INT_T_23 0x114UL +#define XSDM_REGISTERS_AGG_INT_T_24 0x118UL +#define XSDM_REGISTERS_AGG_INT_T_25 0x11cUL +#define XSDM_REGISTERS_AGG_INT_T_26 0x120UL +#define XSDM_REGISTERS_AGG_INT_T_27 0x124UL +#define XSDM_REGISTERS_AGG_INT_T_28 0x128UL +#define XSDM_REGISTERS_AGG_INT_T_29 0x12cUL +#define XSDM_REGISTERS_AGG_INT_T_20 0x108UL +#define XSDM_REGISTERS_AGG_INT_T_21 0x10cUL +#define XSDM_REGISTERS_AGG_INT_T_22 0x110UL +#define XSDM_REGISTERS_AGG_INT_T_23 0x114UL +#define XSDM_REGISTERS_AGG_INT_T_24 0x118UL +#define XSDM_REGISTERS_AGG_INT_T_25 0x11cUL +#define XSDM_REGISTERS_AGG_INT_T_26 0x120UL +#define XSDM_REGISTERS_AGG_INT_T_27 0x124UL +#define XSDM_REGISTERS_AGG_INT_T_28 0x128UL +#define XSDM_REGISTERS_AGG_INT_T_29 0x12cUL +#define XSDM_REGISTERS_AGG_INT_T_3 0xc4UL +#define XSDM_REGISTERS_AGG_INT_T_30 0x130UL +#define XSDM_REGISTERS_AGG_INT_T_31 0x134UL +#define XSDM_REGISTERS_AGG_INT_T_30 0x130UL +#define XSDM_REGISTERS_AGG_INT_T_31 0x134UL +#define XSDM_REGISTERS_AGG_INT_T_4 0xc8UL +#define XSDM_REGISTERS_AGG_INT_T_5 0xccUL +#define XSDM_REGISTERS_AGG_INT_T_6 0xd0UL +#define XSDM_REGISTERS_AGG_INT_T_7 0xd4UL +#define XSDM_REGISTERS_AGG_INT_T_8 0xd8UL +#define XSDM_REGISTERS_AGG_INT_T_9 0xdcUL +#define XSDM_REGISTERS_CFC_RSP_START_ADDR 0x8UL +#define XSDM_REGISTERS_CMP_COUNTER_MAX0 0x1cUL +#define XSDM_REGISTERS_CMP_COUNTER_MAX1 0x20UL +#define XSDM_REGISTERS_CMP_COUNTER_MAX2 0x24UL +#define XSDM_REGISTERS_CMP_COUNTER_MAX3 0x28UL +#define XSDM_REGISTERS_CMP_COUNTER_START_ADDR 0xcUL +#define XSDM_REGISTERS_ENABLE_IN1 0x238UL +#define XSDM_REGISTERS_ENABLE_IN2 0x23cUL +#define XSDM_REGISTERS_ENABLE_OUT1 0x240UL +#define XSDM_REGISTERS_ENABLE_OUT2 0x244UL +#define XSDM_REGISTERS_NUM_OF_ACK_AFTER_PLACE 0x27cUL +#define XSDM_REGISTERS_NUM_OF_PKT_END_MSG 0x274UL +#define XSDM_REGISTERS_NUM_OF_PXP_ASYNC_REQ 0x278UL +#define XSDM_REGISTERS_NUM_OF_Q0_CMD 0x248UL +#define XSDM_REGISTERS_NUM_OF_Q10_CMD 0x26cUL +#define XSDM_REGISTERS_NUM_OF_Q11_CMD 0x270UL +#define XSDM_REGISTERS_NUM_OF_Q1_CMD 0x24cUL +#define XSDM_REGISTERS_NUM_OF_Q3_CMD 0x250UL +#define XSDM_REGISTERS_NUM_OF_Q4_CMD 0x254UL +#define XSDM_REGISTERS_NUM_OF_Q5_CMD 0x258UL +#define XSDM_REGISTERS_NUM_OF_Q6_CMD 0x25cUL +#define XSDM_REGISTERS_NUM_OF_Q7_CMD 0x260UL +#define XSDM_REGISTERS_NUM_OF_Q8_CMD 0x264UL +#define XSDM_REGISTERS_NUM_OF_Q9_CMD 0x268UL +#define XSDM_REGISTERS_Q_COUNTER_START_ADDR 0x10UL +#define XSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY 0x548UL +#define XSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY_SIZE 1 +#define XSDM_REGISTERS_SYNC_PARSER_EMPTY 0x550UL +#define XSDM_REGISTERS_SYNC_PARSER_EMPTY_SIZE 1 +#define XSDM_REGISTERS_SYNC_SYNC_EMPTY 0x558UL +#define XSDM_REGISTERS_SYNC_SYNC_EMPTY_SIZE 1 +#define XSDM_REGISTERS_TIMER_TICK 0x0UL +#define XSEM_REGISTERS_ARB_CYCLE_SIZE 0x34UL +#define XSEM_REGISTERS_ARB_ELEMENT0 0x20UL +#define XSEM_REGISTERS_ARB_ELEMENT1 0x24UL +#define XSEM_REGISTERS_ARB_ELEMENT2 0x28UL +#define XSEM_REGISTERS_ARB_ELEMENT3 0x2cUL +#define XSEM_REGISTERS_ARB_ELEMENT4 0x30UL +#define XSEM_REGISTERS_ENABLE_IN 0xa4UL +#define XSEM_REGISTERS_ENABLE_OUT 0xa8UL +#define XSEM_REGISTERS_FAST_MEMORY 0x20000UL +#define XSEM_REGISTERS_FAST_MEMORY_SIZE 32768 +#define XSEM_REGISTERS_FIC0_DISABLE 0x224UL +#define XSEM_REGISTERS_FIC0_DISABLE_SIZE 1 +#define XSEM_REGISTERS_FIC1_DISABLE 0x234UL +#define XSEM_REGISTERS_FIC1_DISABLE_SIZE 1 +#define XSEM_REGISTERS_INT_TABLE_TM 0xd4UL +#define XSEM_REGISTERS_INT_TABLE 0x400UL +#define XSEM_REGISTERS_INT_TABLE_SIZE 256 +#define XSEM_REGISTERS_MSG_NUM_FIC0 0x0UL +#define XSEM_REGISTERS_MSG_NUM_FIC1 0x4UL +#define XSEM_REGISTERS_MSG_NUM_FOC0 0x8UL +#define XSEM_REGISTERS_MSG_NUM_FOC1 0xcUL +#define XSEM_REGISTERS_MSG_NUM_FOC2 0x10UL +#define XSEM_REGISTERS_MSG_NUM_FOC3 0x14UL +#define XSEM_REGISTERS_PAS_DISABLE 0x24cUL +#define XSEM_REGISTERS_PAS_DISABLE_SIZE 1 +#define XSEM_REGISTERS_PASSIVE_BUFFER 0x2000UL +#define XSEM_REGISTERS_PASSIVE_BUFFER_SIZE 2048 +#define XSEM_REGISTERS_PRAM 0x40000UL +#define XSEM_REGISTERS_PRAM_SIZE 65536 +#define XSEM_REGISTERS_SLEEP_THREADS_VALID 0x26cUL +#define XSEM_REGISTERS_SLEEP_THREADS_VALID_SIZE 1 +#define XSEM_REGISTERS_SLOW_EXT_STORE_EMPTY 0x2a0UL +#define XSEM_REGISTERS_SLOW_EXT_STORE_EMPTY_SIZE 1 +#define XSEM_REGISTERS_THREADS_LIST 0x2e4UL +#define XSEM_REGISTERS_THREADS_LIST_SIZE 1 +#define XSEM_REGISTERS_TS_0_AS 0x38UL +#define XSEM_REGISTERS_TS_10_AS 0x60UL +#define XSEM_REGISTERS_TS_11_AS 0x64UL +#define XSEM_REGISTERS_TS_12_AS 0x68UL +#define XSEM_REGISTERS_TS_13_AS 0x6cUL +#define XSEM_REGISTERS_TS_14_AS 0x70UL +#define XSEM_REGISTERS_TS_15_AS 0x74UL +#define XSEM_REGISTERS_TS_16_AS 0x78UL +#define XSEM_REGISTERS_TS_17_AS 0x7cUL +#define XSEM_REGISTERS_TS_18_AS 0x80UL +#define XSEM_REGISTERS_TS_19_AS 0x84UL +#define XSEM_REGISTERS_TS_1_AS 0x3cUL +#define XSEM_REGISTERS_TS_2_AS 0x40UL +#define XSEM_REGISTERS_TS_3_AS 0x44UL +#define XSEM_REGISTERS_TS_4_AS 0x48UL +#define XSEM_REGISTERS_TS_5_AS 0x4cUL +#define XSEM_REGISTERS_TS_6_AS 0x50UL +#define XSEM_REGISTERS_TS_7_AS 0x54UL +#define XSEM_REGISTERS_TS_8_AS 0x58UL +#define XSEM_REGISTERS_TS_9_AS 0x5cUL +#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3) +#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) +#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3) +#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3) +#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3) +#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3) +#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3) +#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3) +#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3) +#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3) +#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3) +#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3) +#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3) +#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3) +#ifndef EMAC_REG_H +#define EMAC_REG_H +#define EMAC_REG_EMAC_MODE 0x0 +#define EMAC_MODE_RESET (1L<<0) +#define EMAC_MODE_RESET_BITSHIFT 0 +#define EMAC_MODE_HALF_DUPLEX (1L<<1) +#define EMAC_MODE_HALF_DUPLEX_BITSHIFT 1 +#define EMAC_MODE_PORT (0x3L<<2) +#define EMAC_MODE_PORT_BITSHIFT 2 +#define EMAC_MODE_PORT_NONE (0L<<2) +#define EMAC_MODE_PORT_NONE_BITSHIFT 2 +#define EMAC_MODE_PORT_MII (1L<<2) +#define EMAC_MODE_PORT_MII_BITSHIFT 2 +#define EMAC_MODE_PORT_GMII (2L<<2) +#define EMAC_MODE_PORT_GMII_BITSHIFT 2 +#define EMAC_MODE_PORT_MII_10M (3L<<2) +#define EMAC_MODE_PORT_MII_10M_BITSHIFT 2 +#define EMAC_MODE_MAC_LOOP (1L<<4) +#define EMAC_MODE_MAC_LOOP_BITSHIFT 4 +#define EMAC_MODE_25G_MODE (1L<<5) +#define EMAC_MODE_25G_MODE_BITSHIFT 5 +#define EMAC_MODE_TAGGED_MAC_CTL (1L<<7) +#define EMAC_MODE_TAGGED_MAC_CTL_BITSHIFT 7 +#define EMAC_MODE_TX_BURST (1L<<8) +#define EMAC_MODE_TX_BURST_BITSHIFT 8 +#define EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9) +#define EMAC_MODE_MAX_DEFER_DROP_ENA_BITSHIFT 9 +#define EMAC_MODE_EXT_LINK_POL (1L<<10) +#define EMAC_MODE_EXT_LINK_POL_BITSHIFT 10 +#define EMAC_MODE_FORCE_LINK (1L<<11) +#define EMAC_MODE_FORCE_LINK_BITSHIFT 11 +#define EMAC_MODE_MPKT (1L<<18) +#define EMAC_MODE_MPKT_BITSHIFT 18 +#define EMAC_MODE_MPKT_RCVD (1L<<19) +#define EMAC_MODE_MPKT_RCVD_BITSHIFT 19 +#define EMAC_MODE_ACPI_RCVD (1L<<20) +#define EMAC_MODE_ACPI_RCVD_BITSHIFT 20 +#define EMAC_REG_EMAC_STATUS 0x4 +#define EMAC_STATUS_LINK (1L<<11) +#define EMAC_STATUS_LINK_BITSHIFT 11 +#define EMAC_STATUS_LINK_CHANGE (1L<<12) +#define EMAC_STATUS_LINK_CHANGE_BITSHIFT 12 +#define EMAC_STATUS_SERDES_AUTONEG_COMPLETE (1L<<13) +#define EMAC_STATUS_SERDES_AUTONEG_COMPLETE_BITSHIFT 13 +#define EMAC_STATUS_SERDES_AUTONEG_CHANGE (1L<<14) +#define EMAC_STATUS_SERDES_AUTONEG_CHANGE_BITSHIFT 14 +#define EMAC_STATUS_SERDES_NXT_PG_CHANGE (1L<<16) +#define EMAC_STATUS_SERDES_NXT_PG_CHANGE_BITSHIFT 16 +#define EMAC_STATUS_SERDES_RX_CONFIG_IS_0 (1L<<17) +#define EMAC_STATUS_SERDES_RX_CONFIG_IS_0_BITSHIFT 17 +#define EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE (1L<<18) +#define EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE_BITSHIFT 18 +#define EMAC_STATUS_MI_COMPLETE (1L<<22) +#define EMAC_STATUS_MI_COMPLETE_BITSHIFT 22 +#define EMAC_STATUS_MI_INT (1L<<23) +#define EMAC_STATUS_MI_INT_BITSHIFT 23 +#define EMAC_STATUS_AP_ERROR (1L<<24) +#define EMAC_STATUS_AP_ERROR_BITSHIFT 24 +#define EMAC_STATUS_PARITY_ERROR_STATE (1L<<31) +#define EMAC_STATUS_PARITY_ERROR_STATE_BITSHIFT 31 +#define EMAC_REG_EMAC_ATTENTION_ENA 0x8 +#define EMAC_ATTENTION_ENA_LINK (1L<<11) +#define EMAC_ATTENTION_ENA_LINK_BITSHIFT 11 +#define EMAC_ATTENTION_ENA_AUTONEG_CHANGE (1L<<14) +#define EMAC_ATTENTION_ENA_AUTONEG_CHANGE_BITSHIFT 14 +#define EMAC_ATTENTION_ENA_NXT_PG_CHANGE (1L<<16) +#define EMAC_ATTENTION_ENA_NXT_PG_CHANGE_BITSHIFT 16 +#define EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE (1L<<18) +#define EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE_BITSHIFT 18 +#define EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22) +#define EMAC_ATTENTION_ENA_MI_COMPLETE_BITSHIFT 22 +#define EMAC_ATTENTION_ENA_MI_INT (1L<<23) +#define EMAC_ATTENTION_ENA_MI_INT_BITSHIFT 23 +#define EMAC_ATTENTION_ENA_AP_ERROR (1L<<24) +#define EMAC_ATTENTION_ENA_AP_ERROR_BITSHIFT 24 +#define EMAC_REG_EMAC_LED 0xc +#define EMAC_LED_OVERRIDE (1L<<0) +#define EMAC_LED_OVERRIDE_BITSHIFT 0 +#define EMAC_LED_1000MB_OVERRIDE (1L<<1) +#define EMAC_LED_1000MB_OVERRIDE_BITSHIFT 1 +#define EMAC_LED_100MB_OVERRIDE (1L<<2) +#define EMAC_LED_100MB_OVERRIDE_BITSHIFT 2 +#define EMAC_LED_10MB_OVERRIDE (1L<<3) +#define EMAC_LED_10MB_OVERRIDE_BITSHIFT 3 +#define EMAC_LED_TRAFFIC_OVERRIDE (1L<<4) +#define EMAC_LED_TRAFFIC_OVERRIDE_BITSHIFT 4 +#define EMAC_LED_BLNK_TRAFFIC (1L<<5) +#define EMAC_LED_BLNK_TRAFFIC_BITSHIFT 5 +#define EMAC_LED_TRAFFIC (1L<<6) +#define EMAC_LED_TRAFFIC_BITSHIFT 6 +#define EMAC_LED_1000MB (1L<<7) +#define EMAC_LED_1000MB_BITSHIFT 7 +#define EMAC_LED_100MB (1L<<8) +#define EMAC_LED_100MB_BITSHIFT 8 +#define EMAC_LED_10MB (1L<<9) +#define EMAC_LED_10MB_BITSHIFT 9 +#define EMAC_LED_TRAFFIC_STAT (1L<<10) +#define EMAC_LED_TRAFFIC_STAT_BITSHIFT 10 +#define EMAC_LED_2500MB (1L<<11) +#define EMAC_LED_2500MB_BITSHIFT 11 +#define EMAC_LED_2500MB_OVERRIDE (1L<<12) +#define EMAC_LED_2500MB_OVERRIDE_BITSHIFT 12 +#define EMAC_LED_ACTIVITY_SEL (0x3L<<17) +#define EMAC_LED_ACTIVITY_SEL_BITSHIFT 17 +#define EMAC_LED_ACTIVITY_SEL_0 (0L<<17) +#define EMAC_LED_ACTIVITY_SEL_0_BITSHIFT 17 +#define EMAC_LED_ACTIVITY_SEL_1 (1L<<17) +#define EMAC_LED_ACTIVITY_SEL_1_BITSHIFT 17 +#define EMAC_LED_ACTIVITY_SEL_2 (2L<<17) +#define EMAC_LED_ACTIVITY_SEL_2_BITSHIFT 17 +#define EMAC_LED_ACTIVITY_SEL_3 (3L<<17) +#define EMAC_LED_ACTIVITY_SEL_3_BITSHIFT 17 +#define EMAC_LED_BLNK_RATE (0xfffL<<19) +#define EMAC_LED_BLNK_RATE_BITSHIFT 19 +#define EMAC_LED_BLNK_RATE_ENA (1L<<31) +#define EMAC_LED_BLNK_RATE_ENA_BITSHIFT 31 +#define EMAC_REG_EMAC_MAC_MATCH 0x10 +#define EMAC_REG_EMAC_MAC_MATCH_COUNT 32 +#define EMAC_REG_EMAC_UNUSED1 0x90 +#define EMAC_REG_EMAC_UNUSED1_COUNT 2 +#define EMAC_REG_EMAC_BACKOFF_SEED 0x98 +#define EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0) +#define EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED_BITSHIFT 0 +#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c +#define EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0) +#define EMAC_RX_MTU_SIZE_MTU_SIZE_BITSHIFT 0 +#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) +#define EMAC_RX_MTU_SIZE_JUMBO_ENA_BITSHIFT 31 +#define EMAC_REG_EMAC_UNUSED2 0xa0 +#define EMAC_REG_EMAC_UNUSED2_COUNT 3 +#define EMAC_REG_EMAC_MDIO_COMM 0xac +#define EMAC_MDIO_COMM_DATA (0xffffL<<0) +#define EMAC_MDIO_COMM_DATA_BITSHIFT 0 +#define EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16) +#define EMAC_MDIO_COMM_REG_ADDR_BITSHIFT 16 +#define EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21) +#define EMAC_MDIO_COMM_PHY_ADDR_BITSHIFT 21 +#define EMAC_MDIO_COMM_COMMAND (0x3L<<26) +#define EMAC_MDIO_COMM_COMMAND_BITSHIFT 26 +#define EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26) +#define EMAC_MDIO_COMM_COMMAND_UNDEFINED_0_BITSHIFT 26 +#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26) +#define EMAC_MDIO_COMM_COMMAND_ADDRESS_BITSHIFT 26 +#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26) +#define EMAC_MDIO_COMM_COMMAND_WRITE_22_BITSHIFT 26 +#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26) +#define EMAC_MDIO_COMM_COMMAND_WRITE_45_BITSHIFT 26 +#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26) +#define EMAC_MDIO_COMM_COMMAND_READ_22_BITSHIFT 26 +#define EMAC_MDIO_COMM_COMMAND_READ_INC_45 (2L<<26) +#define EMAC_MDIO_COMM_COMMAND_READ_INC_45_BITSHIFT 26 +#define EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26) +#define EMAC_MDIO_COMM_COMMAND_UNDEFINED_3_BITSHIFT 26 +#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26) +#define EMAC_MDIO_COMM_COMMAND_READ_45_BITSHIFT 26 +#define EMAC_MDIO_COMM_FAIL (1L<<28) +#define EMAC_MDIO_COMM_FAIL_BITSHIFT 28 +#define EMAC_MDIO_COMM_START_BUSY (1L<<29) +#define EMAC_MDIO_COMM_START_BUSY_BITSHIFT 29 +#define EMAC_REG_EMAC_MDIO_STATUS 0xb0 +#define EMAC_MDIO_STATUS_LINK (1L<<0) +#define EMAC_MDIO_STATUS_LINK_BITSHIFT 0 +#define EMAC_MDIO_STATUS_10MB (1L<<1) +#define EMAC_MDIO_STATUS_10MB_BITSHIFT 1 +#define EMAC_REG_EMAC_MDIO_MODE 0xb4 +#define EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1) +#define EMAC_MDIO_MODE_SHORT_PREAMBLE_BITSHIFT 1 +#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4) +#define EMAC_MDIO_MODE_AUTO_POLL_BITSHIFT 4 +#define EMAC_MDIO_MODE_BIT_BANG (1L<<8) +#define EMAC_MDIO_MODE_BIT_BANG_BITSHIFT 8 +#define EMAC_MDIO_MODE_MDIO (1L<<9) +#define EMAC_MDIO_MODE_MDIO_BITSHIFT 9 +#define EMAC_MDIO_MODE_MDIO_OE (1L<<10) +#define EMAC_MDIO_MODE_MDIO_OE_BITSHIFT 10 +#define EMAC_MDIO_MODE_MDC (1L<<11) +#define EMAC_MDIO_MODE_MDC_BITSHIFT 11 +#define EMAC_MDIO_MODE_MDINT (1L<<12) +#define EMAC_MDIO_MODE_MDINT_BITSHIFT 12 +#define EMAC_MDIO_MODE_EXT_MDINT (1L<<13) +#define EMAC_MDIO_MODE_EXT_MDINT_BITSHIFT 13 +#define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16) +#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16 +#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31) +#define EMAC_MDIO_MODE_CLAUSE_45_BITSHIFT 31 +#define EMAC_REG_EMAC_MDIO_AUTO_STATUS 0xb8 +#define EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0) +#define EMAC_MDIO_AUTO_STATUS_AUTO_ERR_BITSHIFT 0 +#define EMAC_REG_EMAC_TX_MODE 0xbc +#define EMAC_TX_MODE_RESET (1L<<0) +#define EMAC_TX_MODE_RESET_BITSHIFT 0 +#define EMAC_TX_MODE_CS16_TEST (1L<<2) +#define EMAC_TX_MODE_CS16_TEST_BITSHIFT 2 +#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) +#define EMAC_TX_MODE_EXT_PAUSE_EN_BITSHIFT 3 +#define EMAC_TX_MODE_FLOW_EN (1L<<4) +#define EMAC_TX_MODE_FLOW_EN_BITSHIFT 4 +#define EMAC_TX_MODE_BIG_BACKOFF (1L<<5) +#define EMAC_TX_MODE_BIG_BACKOFF_BITSHIFT 5 +#define EMAC_TX_MODE_LONG_PAUSE (1L<<6) +#define EMAC_TX_MODE_LONG_PAUSE_BITSHIFT 6 +#define EMAC_TX_MODE_LINK_AWARE (1L<<7) +#define EMAC_TX_MODE_LINK_AWARE_BITSHIFT 7 +#define EMAC_REG_EMAC_TX_STATUS 0xc0 +#define EMAC_TX_STATUS_XOFFED (1L<<0) +#define EMAC_TX_STATUS_XOFFED_BITSHIFT 0 +#define EMAC_TX_STATUS_XOFF_SENT (1L<<1) +#define EMAC_TX_STATUS_XOFF_SENT_BITSHIFT 1 +#define EMAC_TX_STATUS_XON_SENT (1L<<2) +#define EMAC_TX_STATUS_XON_SENT_BITSHIFT 2 +#define EMAC_TX_STATUS_LINK_UP (1L<<3) +#define EMAC_TX_STATUS_LINK_UP_BITSHIFT 3
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1.4.2
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