sparc32 MXCC support
RFC 1/1 sparc32 MXCC support
I'm trying to add SuperSparc II MXCC support and need some feedback.
Is there a better way to read and write physical memory in 64bit chunks? I'm not sure what I'm doing is portable between 32/64 and big/little endian.
Index: hw/sun4m.c
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RCS file: /sources/qemu/qemu/hw/sun4m.c,v
retrieving revision 1.55
sun4m.c +1 -1
@@ -327,7 +327,7 @@ static void *sun4m_hw_init(const structfor (i =0 ; i < smp_cpus; i++) { env =cpu_init (); -cpu_sparc_register (env, def); +cpu_sparc_register (env, def, i); envs[i] = env;if (i ==0 ) {qemu_register_reset (main_cpu_reset, env);
Index: linux-user/main.c
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RCS file: /sources/qemu/qemu/linux-user/main.c,v
retrieving revision 1.132
main.c +1 -1
@@ -2139,7 +2139,7 @@ int main(int argc, char **argv)fprintf (stderr,"Unable to find Sparc CPU definition\n" );exit (1 ); } -cpu_sparc_register (env, def); +cpu_sparc_register (env, def,0 ); env->pc = regs->pc; env->npc = regs->npc; env->y = regs->y;
Index: target-sparc/cpu.h
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RCS file: /sources/qemu/qemu/target-sparc/cpu.h,v
retrieving revision 1.53
cpu.h +3 -1
@@ -210,6 +210,8 @@ typedef struct CPUSPARCState {uint64_t dtlb_tte[64 ];#else uint32_t mmuregs[16 ]; +uint64_t mxccdata[4 ]; +uint64_t mxccregs[8 ];#endif /* temporary float registers */ float32 ft0, ft1;
@@ -266,7 +268,7 @@ int cpu_sparc_close(CPUSPARCState *s);int sparc_find_by_name (const unsigned char *name,const sparc_def_t **def);void sparc_cpu_list (FILE *f,int (*cpu_fprintf)(FILE *f,const char *fmt, ...)); -int cpu_sparc_register (CPUSPARCState *env,const sparc_def_t *def); +int cpu_sparc_register (CPUSPARCState *env,const sparc_def_t *def,int cpu);#define GET_PSR (env) (env->version | (env->psr & PSR_ICC) | \ (env->psref? PSR_EF : 0) | \
Index: target-sparc/op_helper.c
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RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v retrieving revision 1.41
op_helper.c +167 -0
191 lines not on this page · raw message
Index: target-sparc/translate.c
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RCS file: /sources/qemu/qemu/target-sparc/translate.c,v retrieving revision 1.74
translate.c +2 -1
@@ -3618,12 +3618,13 @@ void sparc_cpu_list (FILE *f, int (*cpu_ } } -int cpu_sparc_register (CPUSPARCState *env,const sparc_def_t *def) +int cpu_sparc_register (CPUSPARCState *env,const sparc_def_t *def,int cpu) { env->version = def->iu_version; env->fsr = def->fpu_version;#if !defined(TARGET_SPARC64 ) env->mmuregs[0 ] |= def->mmu_version; + env->mxccregs[7 ] = ((cpu +8 ) &0xf ) <<24 ;#endif return 0 ; }
Quoted 4 lines · Robert Reif
I'm trying to add SuperSparc II MXCC support and need some feedback.
Is there a better way to read and write physical memory in 64bit chunks? I'm not sure what I'm doing is portable between 32/64 and big/little endian.
Thank you for your effort. Applying the patch allows NetBSD on SS-10 to boot as far as on SS-5, previously it crashed.
I think the code is portable, but I think changing the register type to uint32_t and using a DPRINTF system like used in for example hw/iommu.c should make the code slightly clearer.
For the memory access, ldl/q_phys/stl/q_phys is used in other block copy routines. For longer blocks or if the address can be unaligned, cpu_physical_memory_read() could be a better choice.
Quoted 1 line
+int
cpu_sparc_register(CPUSPARCState *env, constsparc_def_t*def, int cpu);
unsigned int cpu?
Quoted 1 line
+ printf("ERROR:
helper_ld_asi(asi = %d, size = %d, sign = %d)T0 = %08x: unsupported size\n", asi, size, sign, T0);
If it's an error to access the registers with different size, you should use do_unassigned_access() to report this.
Quoted 10 lines · Blue Swirl
Quoted 6 lines · Robert Reif
I'm trying to add SuperSparc II MXCC support and need some feedback.
Is there a better way to read and write physical memory in 64bit chunks? I'm not sure what I'm doing is portable between 32/64 and big/little endian.
Quoted 7 lines
Thank you for your effort. Applying the patch allows NetBSD on SS-10 to boot as far as on SS-5, previously it crashed.
I think the code is portable, but I think changing the register type to
uint32_tand using a DPRINTF system like used in for examplehw/iommu.cshould make the code slightly clearer.
I don't have access to chip specs but from reading linux and *bsd code it appears that the registers are 64 bits wide but sometimes accessed as 32 bits to get only the bottom 32 bits. Do you mean using two uint32_t for a 64 bit register? How about a union of 2 uint32_t and a uint64_t. Is that portable? Never mind. I just found out there is an ldq_phys and stq_phys. I'll use those.
I looked at DPRINTF but would need a DPRINTF_MMU and DPRINTF_MXCC ... Would that be acceptable?
Quoted 8 lines
For the memory access, ldl/q_phys/stl/q_phys is used in other block copy routines. For longer blocks or if the address can be unaligned,
cpu_physical_memory_read()could be a better choice.
Quoted 7 lines
Quoted 3 lines
+int
cpu_sparc_register(CPUSPARCState *env, constsparc_def_t*def, int cpu);unsigned int cpu?
OK
Quoted 9 lines
Quoted 3 lines
+ printf("ERROR:
helper_ld_asi(asi = %d, size = %d, sign = %d)T0 = %08x: unsupported size\n", asi, size, sign, T0);If it's an error to access the registers with different size, you should use
do_unassigned_access()to report this.
These are more for me to make sure I catch all the necessary accesses without adding unnecessary code. linux 2.4 and netbsd only use the ones I have implemented. openboot uses more and also some undocumented ones which are caught by this but I don't know how to handle them yet. I will use do_unassigned_access where necessary now.
Thanks for the review.