Fix Vista screen clear on AMD

Patch to fix horribly slow screen clear during Vista 32 installation on AMD.

xen/arch/x86/mm/shadow/common.c +2 -1

 #include "private.h"
 
 

@@ -2725,17 +2726,18 @@ shadow_write_p2m_entry(struct vcpu *v, u
     safe_write_pte(p, new);
 
     /* install P2M in monitors for PAE Xen */
-#if CONFIG_PAGING_LEVELS == 3
+#if CONFIG_PAGING_LEVELS >= 3
     if ( level == 3 ) {
         struct vcpu *v;
+#if CONFIG_PAGING_LEVELS == 3

Hi Ben, Gary,

Quoted 3 lines · Ben Guthro

Patch to fix horribly slow screen clear during Vista 32 installation on AMD.

Can you explain what the patch does? It seems to extend the need for extra update_cr3() calls to the 64bit hypervisor case and then cause it never to happen at all.

xen/arch/x86/mm/shadow/common.c line 40

Quoted 9 lines

diff -r 64544443e6d6 xen/arch/x86/mm/shadow/common.c

xen/arch/x86/mm/shadow/common.c +1 -0

@@ -36,6 +36,7 @@
 #include <asm/current.h>
 #include <asm/flushtlb.h>
 #include <asm/shadow.h>
+#include <asm/paging.h>
 

Inside shadow code, it's best to use the shadow_* versions of things. The paging_* ones will just check for being in shadow mode, which we know is true.

Quoted 13 lines

xen/arch/x86/mm/shadow/common.c +2 -1

 #include "private.h"
 

@@ -2725,17 +2726,18 @@ shadow_write_p2m_entry(struct vcpu *v, u
     safe_write_pte(p, new);
 
     /* install P2M in monitors for PAE Xen */
-#if CONFIG_PAGING_LEVELS == 3
+#if CONFIG_PAGING_LEVELS >= 3
     if ( level == 3 ) {
         struct vcpu *v;
+#if CONFIG_PAGING_LEVELS == 3
         /* We have written to the p2m l3: need to sync the per-vcpu

xen/arch/x86/mm/shadow/common.c shadow_write_p2m_entry(struct vcpu *v, u · line 2741

Quoted 10 lines

xen/arch/x86/mm/shadow/common.c +2 -2

          * copies of it in the monitor tables */
         p2m_install_entry_in_monitors(d, (l3_pgentry_t *)p);
+#endif
         /* Also, any vcpus running on shadows of the p2m need to 
          * reload their CR3s so the change propagates to the shadow */
         for_each_vcpu(d, v) {
-            if ( pagetable_get_pfn(v->arch.guest_table) 
-                 == pagetable_get_pfn(d->arch.phys_table) 
+            if ( likely(!paging_mode_translate(d))
 

This test will never be true; if you aren't in paging_mode_translate() you won't be writing p2m entries in the first place.

That said, I think it's probably right to just get rid of the call entirely, since we don't shadow the p2m any more.

Cheers,

Tim.

hmm,

Its certainly possiible that I ported this incorrectly to unstable. I have attached the original patch that applies to 3.1.1 for your review.

Quoted 4 lines · Ben Guthro

hmm,

Its certainly possiible that I ported this incorrectly to unstable. I have attached the original patch that applies to 3.1.1 for your review.

Yep, that's it; there is no equivalent of v->arch.paging.translate_enabled in -unstable any more since I got rid of the shadowing of the p2m and the idea of vcpus that don't need p2m translation.

The symptom was that the Vista bootloader (in protected mode but not paging enabled) was taking a VMEXIT for every access to the VGA framebuffer. The PCI address region had been mapped in the p2m, but that change wasn't being reflected to the shadow. I never tracked down why this only happened for AMD.