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sparc32: make number of per CPU timers match number of CPUs

PATCH Applied Robert Reif 2 participants 3 messages Dec 16, 2007 – Dec 17, 2007

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Robert Reif

author
#0 lore raw

PATCH 1/1 sparc32: make number of per CPU timers match number of CPUs

Only create as many per CPU timers as there are CPUs.

Index: hw/slavio_timer.c
===================================================================
RCS file: /sources/qemu/qemu/hw/slavio_timer.c,v
retrieving revision 1.21

slavio_timer.c +5 -2
diff -p -u -r1.21 slavio_timer.c
@@ -61,6 +61,7 @@ typedef struct SLAVIO_TIMERState {
     struct SLAVIO_TIMERState *master;
     int slave_index;
     // system only
+    unsigned int num_slaves;
     struct SLAVIO_TIMERState *slave[MAX_CPUS];
     uint32_t slave_mode;
 } SLAVIO_TIMERState;

@@ -352,14 +353,16 @@ static SLAVIO_TIMERState *slavio_timer_i
 }
 
 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
-                           qemu_irq *cpu_irqs)
+                           qemu_irq *cpu_irqs, unsigned int num_cpus)
 {
     SLAVIO_TIMERState *master;
     unsigned int i;
 
     master = slavio_timer_init(base + SYS_TIMER_OFFSET, master_irq, NULL, 0);
 
-    for (i = 0; i < MAX_CPUS; i++) {
+    master->num_slaves = num_cpus;
+
+    for (i = 0; i < master->num_slaves; i++) {
         master->slave[i] = slavio_timer_init(base + (target_phys_addr_t)
                                              CPU_TIMER_OFFSET(i),
                                              cpu_irqs[i], master, i);

Index: hw/sun4m.c
===================================================================
RCS file: /sources/qemu/qemu/hw/sun4m.c,v
retrieving revision 1.69

sun4m.c +1 -1
diff -p -u -r1.69 sun4m.c
@@ -436,7 +436,7 @@ static void sun4m_hw_init(const struct h
                         hwdef->nvram_size, 8);
 
     slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
-                          slavio_cpu_irq);
+                          slavio_cpu_irq, smp_cpus);
 
     slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
                               nographic);

Index: hw/sun4m.h
===================================================================
RCS file: /sources/qemu/qemu/hw/sun4m.h,v
retrieving revision 1.4

sun4m.h +1 -1
diff -p -u -r1.4 sun4m.h
@@ -36,7 +36,7 @@ void slavio_irq_info(void *opaque);
 
 /* slavio_timer.c */
 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
-                           qemu_irq *cpu_irqs);
+                           qemu_irq *cpu_irqs, unsigned int num_cpus);
 
 /* slavio_serial.c */
 SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
author
#1 lore raw
Quoted 1 line · Robert Reif

Only create as many per CPU timers as there are CPUs.

This time with the right patch.

Index: hw/slavio_timer.c
===================================================================
RCS file: /sources/qemu/qemu/hw/slavio_timer.c,v
retrieving revision 1.21

slavio_timer.c +7 -4
diff -p -u -r1.21 slavio_timer.c
@@ -61,6 +61,7 @@ typedef struct SLAVIO_TIMERState {
     struct SLAVIO_TIMERState *master;
     int slave_index;
     // system only
+    unsigned int num_slaves;
     struct SLAVIO_TIMERState *slave[MAX_CPUS];
     uint32_t slave_mode;
 } SLAVIO_TIMERState;

@@ -230,7 +231,7 @@ static void slavio_timer_mem_writel(void
         if (s->master == NULL) {
             unsigned int i;
 
-            for (i = 0; i < MAX_CPUS; i++) {
+            for (i = 0; i < s->num_slaves; i++) {
                 if (val & (1 << i)) {
                     qemu_irq_lower(s->slave[i]->irq);
                     s->slave[i]->limit = -1ULL;

@@ -244,7 +245,7 @@ static void slavio_timer_mem_writel(void
                     ptimer_run(s->slave[i]->timer, 0);
                 }
             }
-            s->slave_mode = val & ((1 << MAX_CPUS) - 1);
+            s->slave_mode = val & ((1 << s->num_slaves) - 1);
         } else
             DPRINTF("not system timer\n");
         break;

@@ -352,14 +353,16 @@ static SLAVIO_TIMERState *slavio_timer_i
 }
 
 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
-                           qemu_irq *cpu_irqs)
+                           qemu_irq *cpu_irqs, unsigned int num_cpus)
 {
     SLAVIO_TIMERState *master;
     unsigned int i;
 
     master = slavio_timer_init(base + SYS_TIMER_OFFSET, master_irq, NULL, 0);
 
-    for (i = 0; i < MAX_CPUS; i++) {
+    master->num_slaves = num_cpus;
+
+    for (i = 0; i < master->num_slaves; i++) {
         master->slave[i] = slavio_timer_init(base + (target_phys_addr_t)
                                              CPU_TIMER_OFFSET(i),
                                              cpu_irqs[i], master, i);

Index: hw/sun4m.c
===================================================================
RCS file: /sources/qemu/qemu/hw/sun4m.c,v
retrieving revision 1.69

sun4m.c +1 -1
diff -p -u -r1.69 sun4m.c
@@ -436,7 +436,7 @@ static void sun4m_hw_init(const struct h
                         hwdef->nvram_size, 8);
 
     slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
-                          slavio_cpu_irq);
+                          slavio_cpu_irq, smp_cpus);
 
     slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
                               nographic);

Index: hw/sun4m.h
===================================================================
RCS file: /sources/qemu/qemu/hw/sun4m.h,v
retrieving revision 1.4

sun4m.h +1 -1
diff -p -u -r1.4 sun4m.h
@@ -36,7 +36,7 @@ void slavio_irq_info(void *opaque);
 
 /* slavio_timer.c */
 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
-                           qemu_irq *cpu_irqs);
+                           qemu_irq *cpu_irqs, unsigned int num_cpus);
 
 /* slavio_serial.c */
 SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
Applied
#2 lore raw
Quoted 3 lines · Robert Reif
Quoted 1 line · Robert Reif

Only create as many per CPU timers as there are CPUs.

Thanks, applied. I changed the timer setup a bit so that it doesn't break my SMP tests.