Bochsbios patch
PATCH 9/9 Bochsbios patch
Several ACPI entries were missing from the bios and the new controllers need to be initialized properly.
Furthermore COM2 is not being emulated, so Mac OS X broke trying to initialize it.
The HPET ACPI table parts are optional.
This patch is against the bochsbios. Should this rather be sent to the bochs ML?
Index: acpi-dsdt.dsl
===================================================================
RCS file: /cvsroot/bochs/bochs/bios/acpi-dsdt.dsl,v retrieving revision 1.1
acpi-dsdt.dsl +192 -0
@@ -25,6 +25,93 @@ 0x1 // OEM Revision ) { + OperationRegion (GNVS, SystemMemory, 0x7EEDBC10, 0x0100) + Field (GNVS, AnyAcc, Lock, Preserve) + { + OSYS, 16, + SMIF, 8, + PRM0, 8, + PRM1, 8, + SCIF, 8, + PRM2, 8, + PRM3, 8, + LCKF, 8, + PRM4, 8, + PRM5, 8, + P80D, 32, + LIDS, 8, + PWRS, 8, + DBGS, 8, + Offset (0x14), + ACTT, 8, + PSVT, 8, + TC1V, 8, + TC2V, 8, + TSPV, 8, + CRTT, 8, + DTSE, 8, + DTS1, 8, + DTS2, 8, + DTSF, 8, + BNUM, 8, + B0SC, 8, + B1SC, 8, + B2SC, 8, + B0SS, 8, + B1SS, 8, + B2SS, 8, + Offset (0x28), + APIC, 8, + MPEN, 8, + PPCS, 8, + PPCM, 8, + Offset (0x32), + NATP, 8, + CMAP, 8, + CMBP, 8, + LPTP, 8, + FDCP, 8, + CMCP, 8, + CIRP, 8, + Offset (0x3C), + IGDS, 8, + TLST, 8, + CADL, 8, + PADL, 8, + CSTE, 16, + NSTE, 16, + SSTE, 16, + NDID, 8, + DID1, 32, + DID2, 32, + DID3, 32, + DID4, 32, + DID5, 32, + BDSP, 8, + PTY1, 8, + PTY2, 8, + PSCL, 8, + TVF1, 8, + TVF2, 8, + Offset (0x67), + BLCS, 8, + BRTL, 8, + ALSE, 8, + ALAF, 8, + LLOW, 8, + LHIH, 8, + Offset (0x6E), + EMAE, 8, + EMAP, 16, + EMAL, 16, + Offset (0x74), + MEFE, 8, + Offset (0x82), + GTF0, 56, + GTF2, 56, + IDEM, 8 + } + Scope (\) { /* CMOS memory access */
@@ -47,11 +134,114 @@ { DBGL, 32, } + + /* PIC mode setting */ + Name (PICF, 0x00) + Method (_PIC, 1, NotSerialized) + { + Store(Arg0, PICF) + } + Name (SSDT, Package (0x0C) + { + "CPU0IST ", + 0x7EEB8C10, + 0x0000026C, + "CPU1IST ", + 0x7EEB8F10, + 0x00000087, + "CPU0CST ", + 0x7EEB8910, + 0x000002A0, + "CPU1CST ", + 0x7EEB7F10, + 0x00000085 + }) + Name (CFGD, 0x011B49B1) + Name (\PDC0, 0x80000000) + Name (\PDC1, 0x80000000) + Name (\SDTL, 0x00) } + Scope (\_PR) + { + Processor (CPU0, 0x00, 0x00000680, 0x06) {} + /* Processor (CPU1, 0x01, 0x00000410, 0x06) {} */ + } /* PCI Bus definition */ Scope(\_SB) { + OperationRegion (XXX, SystemIO, 0x300, 0x01) + Method (_INI, 0, NotSerialized) + { + Store (0x1, XXX) + If (CondRefOf (_OSI, Local0)) + { + If (_OSI ("Darwin")) + { + Store (0x2710, OSYS) + } + } + + Store (0x35, SMIF) + } + Device (HPET) + { + Name (_HID, EisaId ("PNP0103")) + Name (_CID, 0x010CD041) + Name (BUF0, ResourceTemplate () + { + IRQNoFlags () + {0} + IRQNoFlags () + {8} + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + _Y16) + }) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Method (_CRS, 0, Serialized) + { + + Return (BUF0) + } + } + + Device (SMC) + { + Name (_HID, EisaId ("APP0001")) + Name (_CID, "smc-napa") + Name (_STA, 0x0B) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, + 0x0300, // Range Minimum + 0x0300, // Range Maximum + 0x01, // Alignment + 0x20, // Length + ) + IRQNoFlags () + {6} + }) + } + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + }) + } + Device(PCI0) { Name (_HID, EisaId ("PNP0A03")) Name (_ADR, 0x00)
@@ -300,6 +492,7 @@ } } +/* Device (COM2) { Name (_HID, EisaId ("PNP0501"))
@@ -327,6 +520,7 @@ Return (BUF0) } } +*/ } /* PIIX4 PM */
Index: rombios.c
===================================================================
RCS file: /cvsroot/bochs/bochs/bios/rombios.c,v
retrieving revision 1.176
rombios.c +8 -0
@@ -9513,6 +9513,14 @@ mov eax, #0x00040000call eax + ;; reset the memory (some boot loaders such as syslinux suppose + ;; that the memory is set to zero) + mov edi, #0x00040000 + mov ecx, #0x40000 / 4 + xor eax, eax + rep + stosd + ;; return to 16 bit protected mode first db 0xea dd rombios32_10
Index: rombios.h
===================================================================
RCS file: /cvsroot/bochs/bochs/bios/rombios.h,v
retrieving revision 1.3
rombios.h +1 -1
@@ -19,7 +19,7 @@// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA /* define it to include QEMU specific code */ -//#define BX_QEMU +#define BX_QEMU #ifndef LEGACY # define BX_ROMBIOS32 1
Index: rombios32.c
===================================================================
RCS file: /cvsroot/bochs/bochs/bios/rombios32.c,v
retrieving revision 1.8
rombios32.c +46 -3
99 lines not on this page · raw message
Quoted 8 lines · Alexander Graf
Several ACPI entries were missing from the bios and the new controllers need to be initialized properly.
Furthermore COM2 is not being emulated, so Mac OS X broke trying to initialize it.
The HPET ACPI table parts are optional.This patch is against the bochsbios. Should this rather be sent to the bochs ML?
Yes please. (Maybe you want to keep this list Cc'ed.)
Thiemo
Quoted 7 lines · Thiemo Seufer
Quoted 6 lines · Alexander Graf
Several ACPI entries were missing from the bios and the new controllers need to be initialized properly.
Furthermore COM2 is not being emulated, so Mac OS X broke trying to initialize it.
The HPET ACPI table parts are optional.
Quoted 9 lines
Quoted 2 lines
This patch is against the bochsbios. Should this rather be sent to the bochs ML?
Yes please. (Maybe you want to keep this list Cc'ed.)
Thiemo
I put this on the official Bochs Patch Tracker.
Alex