MPC8568E-MDS: set up QE pario for UART1
PATCH 1/1 MPC8568E-MDS: set up QE pario for UART1
To use UART1 on the MPC8568E-MDS, QE pario pins PC[0:3] should be set up appropriately.
--- board/mpc8568mds/mpc8568mds.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-)
board/mpc8568mds/mpc8568mds.c +7 -0
@@ -84,6 +84,13 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {1, 31, 2, 0, 3}, /* GTX125 */ {4, 6, 3, 0, 2}, /* MDIO */ {4, 5, 1, 0, 2}, /* MDC */ + +/* UART1 */ + {2, 0, 1, 0, 2}, /* UART_SOUT1 */ + {2, 1, 1, 0, 2}, /* UART_RTS1 */ + {2, 2, 2, 0, 2}, /* UART_CTS1 */ + {2, 3, 2, 0, 2}, /* UART_SIN1 */ + {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ };
Signature · 1 line
1.5.0.6
Andy Fleming
AppliedPATCH 1/1 MPC8568E-MDS: set up QE pario for UART1
applied, thanks!
For both of the 8568 patches, I modified them to apply to the top of tree. Since it was a simple change (mpc8568mds directory was moved to board/freescale/), I did it.
Quoted 39 lines · Anton Vorontsov
To use UART1 on the MPC8568E-MDS, QE pario pins PC[0:3] should be set up appropriately.
Signed-off-by Anton Vorontsov <[email protected]>--- board/mpc8568mds/mpc8568mds.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-)board/mpc8568mds/mpc8568mds.c +7
-1@@ -84,6 +84,13 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {1, 31, 2, 0, 3}, /* GTX125 */ {4, 6, 3, 0, 2}, /* MDIO */ {4, 5, 1, 0, 2}, /* MDC */ + +/* UART1 */ + {2, 0, 1, 0, 2}, /* UART_SOUT1 */ + {2, 1, 1, 0, 2}, /* UART_RTS1 */ + {2, 2, 2, 0, 2}, /* UART_CTS1 */ + {2, 3, 2, 0, 2}, /* UART_SIN1 */ + {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ }; --1.5.0.6
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PATCH 1/1 MPC8568E-MDS: set up QE pario for UART1
In reply to Anton VorontsovQuoted 2 lines · Anton Vorontsov
To use UART1 on the MPC8568E-MDS, QE pario pins PC[0:3] should be set up appropriately.
On 83xx, the pario pins are configured via the DTS. So now we have the DTS method for 83xx, and U-Boot for 85xx. Unless there's a U-Boot QE UART driver that I don't know about, this configuration should be done in the DTS, not here.
Signature · 2 lines
Timur Tabi Linux kernel developer at Freescale
PATCH 1/1 MPC8568E-MDS: set up QE pario for UART1
Quoted 5 lines · Timur Tabi
Quoted 2 lines · Anton Vorontsov
To use UART1 on the MPC8568E-MDS, QE pario pins PC[0:3] should be set up appropriately.
On 83xx, the pario pins are configured via the DTS.
And this is wrong way to do pario setup. This was discussed already, and the argument is "device tree isn't configuration file. fix the firmware, and if needed place temporary fixups into the Linux board file".
By the way, I was disagreeing and arguing about that too. ;-)
See:
http://ozlabs.org/pipermail/linuxppc-dev/2007-August/040601.html
http://ozlabs.org/pipermail/linuxppc-dev/2007-August/040691.html
[and more...]
Though there we're discussing GPIOs, but it is more than applicable to par io configuration, i.e. setting up pins' dedicated functions.
Also see documentation update:
http://ozlabs.org/pipermail/linuxppc-dev/2008-January/049418.html
Quoted 4 lines
So now we have the DTS
method for 83xx, and U-Boot for 85xx. Unless there's a U-Boot QE UART driver that I don't know about, this configuration should be done in the DTS, not here.
UART1 on MPC8568E-MDS is second DUART, not QE UART. Though Second DUART is using QE Par I/O pins.
Thanks,
Signature · 4 lines
Anton Vorontsov email: cbou at mail.ru backup email: ya-cbou at yandex.ru irc://irc.freenode.net/bd2
PATCH 1/1 MPC8568E-MDS: set up QE pario for UART1
Quoted 2 lines · Anton Vorontsov
UART1 on MPC8568E-MDS is second DUART, not QE UART. Though Second DUART is using QE Par I/O pins.
Ok, then I guess the patch is okay.
Signature · 2 lines
Timur Tabi Linux kernel developer at Freescale