Support new Exynos3250 SoC based on Cortex-A7 dual core

This patch add memory mapping for PMU (Power Management Unit) which is used for power control of Exynos3250.

Signed-off-by Chanwoo Choi <[email protected]>

Acked-by Kyungmin Park <[email protected]>

---
Arnd Bergmann suggested that need proper driver instead of static memory mapping. As Chanho Park reply[2], Sachin Kamat already posted the DT support patch[1] for memory mapping for SYSRAM.
[1] http://www.spinics.net/lists/linux-samsung-soc/msg27647.html
[2] https://lkml.org/lkml/2014/4/10/161

So, I'm going to re-implement following patch related to static memory mapping after merged Sachin Kamat patch[1].
ARM: EXYNOS: Add IO mapping for PMU of Exynos3250

Quoted 12 lines · On Tuesday 15 April 2014 10:59:47 Chanwoo Choi wrote:

This patch add memory mapping for PMU (Power Management Unit) which is used for power control of Exynos3250.

Signed-off-by Chanwoo Choi <[email protected]>

Acked-by Kyungmin Park <[email protected]>

---
Arnd Bergmann suggested that need proper driver instead of static memory mapping. As Chanho Park reply[2], Sachin Kamat already posted the DT support patch[1] for memory mapping for SYSRAM.
[1] http://www.spinics.net/lists/linux-samsung-soc/msg27647.html
[2] https://lkml.org/lkml/2014/4/10/161

Quoted 3 lines

So, I'm going to re-implement following patch related to static memory mapping after merged Sachin Kamat patch[1].
ARM: EXYNOS: Add IO mapping for PMU of Exynos3250

I don't think we have a patch for the PMU yet, Sachin was looking at the SYSRAM only.

Hi,

Quoted 13 lines · Arnd Bergmann

Quoted 12 lines · On Tuesday 15 April 2014 10:59:47 Chanwoo Choi wrote:

This patch add memory mapping for PMU (Power Management Unit) which is used for power control of Exynos3250.

Signed-off-by Chanwoo Choi <[email protected]>

Acked-by Kyungmin Park <[email protected]>

---
Arnd Bergmann suggested that need proper driver instead of static memory mapping. As Chanho Park reply[2], Sachin Kamat already posted the DT support patch[1] for memory mapping for SYSRAM.
[1] http://www.spinics.net/lists/linux-samsung-soc/msg27647.html
[2] https://lkml.org/lkml/2014/4/10/161

Quoted 6 lines

Quoted 3 lines

So, I'm going to re-implement following patch related to static memory mapping after merged Sachin Kamat patch[1].
ARM: EXYNOS: Add IO mapping for PMU of Exynos3250

I don't think we have a patch for the PMU yet, Sachin was looking at the SYSRAM only.

You are right. Sachin's patch only included the solution of SYSRAM memory mapping. I set out the plan that I would implment proper driver for PMU memory mapping instead of static method after merged Sachin's patch for SYSRAM.

But,
If you'd like me to implment PMU memory mapping instead of static mapping right now, I'll implement it for PMU such as Sachin's patch on next posting(v3).

Thanks for your review.

Best Regards,
Chanwoo Choi

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Hi,

Quoted 23 lines · Chanwoo Choi

Hi,

Quoted 13 lines · Arnd Bergmann

Quoted 12 lines · On Tuesday 15 April 2014 10:59:47 Chanwoo Choi wrote:

This patch add memory mapping for PMU (Power Management Unit) which is used for power control of Exynos3250.

Signed-off-by Chanwoo Choi <[email protected]>

Acked-by Kyungmin Park <[email protected]>

---
Arnd Bergmann suggested that need proper driver instead of static memory mapping. As Chanho Park reply[2], Sachin Kamat already posted the DT support patch[1] for memory mapping for SYSRAM.
[1] http://www.spinics.net/lists/linux-samsung-soc/msg27647.html
[2] https://lkml.org/lkml/2014/4/10/161

Quoted 6 lines

Quoted 3 lines

So, I'm going to re-implement following patch related to static memory mapping after merged Sachin Kamat patch[1].
ARM: EXYNOS: Add IO mapping for PMU of Exynos3250

I don't think we have a patch for the PMU yet, Sachin was looking at the SYSRAM only.

Quoted 8 lines

You are right. Sachin's patch only included the solution of SYSRAM memory mapping. I set out the plan that I would implment proper driver for PMU memory mapping instead of static method after merged Sachin's patch for SYSRAM.

But,
If you'd like me to implment PMU memory mapping instead of static mapping right now, I'll implement it for PMU such as Sachin's patch on next posting(v3).

I have already posted patch[1] for mapping PMU through DT as part of my PMU series for exynos5260.
You can rebase on the same.

[1] http://www.spinics.net/lists/arm-kernel/msg316013.html

Quoted 4 lines · Arnd Bergmann

On Tuesday 15 April 2014 10:59:47 Chanwoo Choi wrote:

I don't think we have a patch for the PMU yet, Sachin was looking at the SYSRAM only.

You are right. Sachin's patch only included the solution of SYSRAM memory mapping. I set out the plan that I would implment proper driver for PMU memory mapping instead of static method after merged Sachin's patch for SYSRAM.

But,
If you'd like me to implment PMU memory mapping instead of static mapping right now, I'll implement it for PMU such as Sachin's patch on next posting(v3).

Quoted 10 lines · On Tuesday 15 April 2014 17:32:40 Chanwoo Choi wrote:

Quoted 4 lines · Arnd Bergmann

On Tuesday 15 April 2014 10:59:47 Chanwoo Choi wrote:

I don't think we have a patch for the PMU yet, Sachin was looking at the SYSRAM only.

You are right. Sachin's patch only included the solution of SYSRAM memory mapping. I set out the plan that I would implment proper driver for PMU memory mapping instead of static method after merged Sachin's patch for SYSRAM.

Quoted 3 lines

But,
If you'd like me to implment PMU memory mapping instead of static mapping right now, I'll implement it for PMU such as Sachin's patch on next posting(v3).

I don't really want to merge a new SoC type until these are resolved, so it would definitely be better to implement this for v3.

This patch fix the offset of CPU boot address and don't operate smc call of SMC_CMD_CPU1BOOT command for Exynos3250.

Signed-off-by Chanwoo Choi <[email protected]>

Acked-by Kyungmin Park <[email protected]>

---
 arch/arm/mach-exynos/firmware.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

arch/arm/mach-exynos/firmware.c +2 -0

index aa01c42..6205d4f 100644
@@ -30,13 +30,16 @@ static int exynos_do_idle(void)
 
 static int exynos_cpu_boot(int cpu)
 {
+       if (soc_is_exynos3250()) {
+               return 0;

arch/arm/mach-exynos/firmware.c +1 -2

        exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
        return 0;

@@ -46,7 +49,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
 {
        void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
 
-       if (!soc_is_exynos4212())
+       if (!soc_is_exynos4212() && !soc_is_exynos3250())
                boot_reg += 4*cpu;
 
        __raw_writel(boot_addr, boot_reg);
--

1.8.0

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Quoted 24 lines · Chanwoo Choi

This patch fix the offset of CPU boot address and don't operate smc call of SMC_CMD_CPU1BOOT command for Exynos3250.

Signed-off-by Chanwoo Choi <[email protected]>

Acked-by Kyungmin Park <[email protected]>

---
 arch/arm/mach-exynos/firmware.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

arch/arm/mach-exynos/firmware.c +2 -0

index aa01c42..6205d4f 100644
@@ -30,13 +30,16 @@ static int exynos_do_idle(void)
 
 static int exynos_cpu_boot(int cpu)
 {
+       if (soc_is_exynos3250()) {
+               return 0;
        /*
         * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
         * But, Exynos4212 has only one secondary CPU so second parameter
         * isn't used for informing secure firmware about CPU id.
         */

arch/arm/mach-exynos/firmware.c static int exynos_do_idle(void) · line 43

Quoted 5 lines

arch/arm/mach-exynos/firmware.c +2 -1

-       if (soc_is_exynos4212())
+       } else if (soc_is_exynos4212()) {
                cpu = 0;
+       }
 

As you already return in case of Exynos3250, you need not change this. First commit hunk without the opening brace should be sufficient.

This patch fix the offset of CPU boot address and don't operate smc call of SMC_CMD_CPU1BOOT command for Exynos3250.

Signed-off-by Chanwoo Choi <[email protected]>

Acked-by Kyungmin Park <[email protected]>

---
  arch/arm/mach-exynos/firmware.c | 7 +++++--
  1 file changed, 5 insertions(+), 2 deletions(-)

arch/arm/mach-exynos/firmware.c +0 -0

index aa01c42..6205d4f 100644

Hi Chanwoo,

Quoted 15 lines · Chanwoo Choi

This patch fix the offset of CPU boot address and don't operate smc call of SMC_CMD_CPU1BOOT command for Exynos3250.

Signed-off-by Chanwoo Choi <[email protected]>

Acked-by Kyungmin Park <[email protected]>

---
  arch/arm/mach-exynos/firmware.c | 7 +++++--
  1 file changed, 5 insertions(+), 2 deletions(-)

arch/arm/mach-exynos/firmware.c +0 -0

index aa01c42..6205d4f 100644
@@ -30,13 +30,16 @@ static int exynos_do_idle(void)
 

arch/arm/mach-exynos/firmware.c static int exynos_do_idle(void) · line 34

Quoted 4 lines

arch/arm/mach-exynos/firmware.c +2 -0

  static int exynos_cpu_boot(int cpu)
  {
+    if (soc_is_exynos3250()) {
+        return 0;

This is strange. How the firmware knows when to boot the CPU then, if CPU1BOOT command is not called?

This patch decide proper lowpower mode of either a15 or a9 according to own ID from Main ID register.

Signed-off-by Chanwoo Choi <[email protected]>

Acked-by Kyungmin Park <[email protected]>

---
  arch/arm/mach-exynos/hotplug.c | 16 +++++++++++-----
  1 file changed, 11 insertions(+), 5 deletions(-)

arch/arm/mach-exynos/hotplug.c +0 -0

index 5eead53..99e54e0 100644

Hi Chanwoo,

Quoted 19 lines · Chanwoo Choi

This patch decide proper lowpower mode of either a15 or a9 according to own ID
from Main ID register.

Signed-off-by Chanwoo Choi <[email protected]>

Acked-by Kyungmin Park <[email protected]>

---
  arch/arm/mach-exynos/hotplug.c | 16 +++++++++++-----
  1 file changed, 11 insertions(+), 5 deletions(-)

arch/arm/mach-exynos/hotplug.c +0 -0

index 5eead53..99e54e0 100644
@@ -135,16 +135,22 @@ void __ref exynos_cpu_die(unsigned int cpu)
        int primary_part = 0;
 

arch/arm/mach-exynos/hotplug.c void __ref exynos_cpu_die(unsigned int cpu) · line 141

Quoted 7 lines

arch/arm/mach-exynos/hotplug.c +2 -2

        /*
-        * we're ready for shutdown now, so do it.
-        * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
+        * we're ready for shutdown now, so do it. Exynos4 is A9 based
+        * while Exynos5 is A15/Exynos3 is A7; check the CPU part
         * number by reading the Main ID register and then perform the
         * appropriate sequence for entering low power.

If changing this comment anyway, I'd suggest removing particular SoC series from it and also correct writing style. My suggestion is:

/*
* Prepare the CPU for shutting down. The required sequence of
* operations depends on core type. CPUID part number can be used to
* determine the right way.
*/

Best regards,
Tomasz
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From: Tomasz Figa <[email protected]>

This patch add new exynos3250.dtsi to support Exynos3250 SoC based on Cortex-A7 dual core and includes following dt nodes:

- GIC interrupt controller
- Pinctrl to control GPIOs
- Clock controller
- CPU information (Cortex-A7 dual core)
- UART to support serial port
- MCT (Multi Core Timer)
- ADC (Analog Digital Converter)
- I2C/SPI bus
- Power domain
- PMU (Performance Monitoring Unit)
- MSHC (Mobile Storage Host Controller)
- PWM (Pluse Width Modulation)
- AMBA bus

Quoted 5 lines · Chanwoo Choi

From: Tomasz Figa <[email protected]>

This patch add new exynos3250.dtsi to support Exynos3250 SoC based on Cortex-A7 dual core and includes following dt nodes:

Quoted 13 lines

- GIC interrupt controller
- Pinctrl to control GPIOs
- Clock controller
- CPU information (Cortex-A7 dual core)
- UART to support serial port
- MCT (Multi Core Timer)
- ADC (Analog Digital Converter)
- I2C/SPI bus
- Power domain
- PMU (Performance Monitoring Unit)
- MSHC (Mobile Storage Host Controller)
- PWM (Pluse Width Modulation)
- AMBA bus

[...]

Where is the arch timer node?

Hi,

Quoted 20 lines · Marc Zyngier

Quoted 18 lines · Chanwoo Choi

From: Tomasz Figa <[email protected]>

This patch add new exynos3250.dtsi to support Exynos3250 SoC based on Cortex-A7 dual core and includes following dt nodes:

- GIC interrupt controller
- Pinctrl to control GPIOs
- Clock controller
- CPU information (Cortex-A7 dual core)
- UART to support serial port
- MCT (Multi Core Timer)
- ADC (Analog Digital Converter)
- I2C/SPI bus
- Power domain
- PMU (Performance Monitoring Unit)
- MSHC (Mobile Storage Host Controller)
- PWM (Pluse Width Modulation)
- AMBA bus

Quoted 3 lines

[...]

Where is the arch timer node?

Exynos3250 uses MCT (Multi Core Timer) instead of ARM_ARCH_TIMER.
- in drivers/clocksource/exynos_mct.c

Quoted 23 lines · Chanwoo Choi

Hi,

Quoted 20 lines · Marc Zyngier

Quoted 18 lines · Chanwoo Choi

From: Tomasz Figa <[email protected]>

This patch add new exynos3250.dtsi to support Exynos3250 SoC based on Cortex-A7 dual core and includes following dt nodes:

- GIC interrupt controller
- Pinctrl to control GPIOs
- Clock controller
- CPU information (Cortex-A7 dual core)
- UART to support serial port
- MCT (Multi Core Timer)
- ADC (Analog Digital Converter)
- I2C/SPI bus
- Power domain
- PMU (Performance Monitoring Unit)
- MSHC (Mobile Storage Host Controller)
- PWM (Pluse Width Modulation)
- AMBA bus

Quoted 6 lines

Quoted 3 lines

[...]

Where is the arch timer node?

Exynos3250 uses MCT (Multi Core Timer) instead of ARM_ARCH_TIMER.
- in drivers/clocksource/exynos_mct.c

Don't you have a Cortex-A7? If so, you have the arch timer.

Quoted 26 lines · Marc Zyngier

Quoted 25 lines · Chanwoo Choi

Hi,

Quoted 22 lines · Marc Zyngier

Quoted 18 lines · Chanwoo Choi

From: Tomasz Figa <[email protected]>

This patch add new exynos3250.dtsi to support Exynos3250 SoC based on Cortex-A7 dual core and includes following dt nodes:

- GIC interrupt controller
- Pinctrl to control GPIOs
- Clock controller
- CPU information (Cortex-A7 dual core)
- UART to support serial port
- MCT (Multi Core Timer)
- ADC (Analog Digital Converter)
- I2C/SPI bus
- Power domain
- PMU (Performance Monitoring Unit)
- MSHC (Mobile Storage Host Controller)
- PWM (Pluse Width Modulation)
- AMBA bus

[...]

Quoted 6 lines

Quoted 4 lines

Quoted 1 line

Where is the arch timer node?

Exynos3250 uses MCT (Multi Core Timer) instead of ARM_ARCH_TIMER.
- in drivers/clocksource/exynos_mct.c

Don't you have a Cortex-A7? If so, you have the arch timer.

Do you means that 'arch timer" is ARM_ARCH_TIMER?

As I knew, ARM_ARCH_TIMER is clocksource driver for system timer. But, Exynos SoC used MCT clocksource for system timer.

Exynos dts file didn't include arch timer node but only include mct node.

Quoted 27 lines · Chanwoo Choi

Quoted 26 lines · Marc Zyngier

Quoted 25 lines · Chanwoo Choi

Hi,

Quoted 22 lines · Marc Zyngier

Quoted 18 lines · Chanwoo Choi

From: Tomasz Figa <[email protected]>

This patch add new exynos3250.dtsi to support Exynos3250 SoC based on Cortex-A7 dual core and includes following dt nodes:

- GIC interrupt controller
- Pinctrl to control GPIOs
- Clock controller
- CPU information (Cortex-A7 dual core)
- UART to support serial port
- MCT (Multi Core Timer)
- ADC (Analog Digital Converter)
- I2C/SPI bus
- Power domain
- PMU (Performance Monitoring Unit)
- MSHC (Mobile Storage Host Controller)
- PWM (Pluse Width Modulation)
- AMBA bus

[...]

Quoted 8 lines

Quoted 6 lines

Quoted 4 lines

Quoted 1 line

Where is the arch timer node?

Exynos3250 uses MCT (Multi Core Timer) instead of ARM_ARCH_TIMER.
- in drivers/clocksource/exynos_mct.c

Don't you have a Cortex-A7? If so, you have the arch timer.

Do you means that 'arch timer" is ARM_ARCH_TIMER?

Yes.

Quoted 3 lines

As I knew, ARM_ARCH_TIMER is clocksource driver for system timer. But, Exynos SoC used MCT clocksource for system timer.

Quoted 1 line

Exynos dts file didn't include arch timer node but only include mct node.

Well, it is a bug, and a recurrent one. A Cortex-A7 has the arch timers implemented. Always.

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/BABFEBJJ.html

All Cortex-A7 have it, and so do A12, A15, A17, A53, A57.

Hi Marc,

Quoted 42 lines · Marc Zyngier

Quoted 27 lines · Chanwoo Choi

Quoted 26 lines · Marc Zyngier

Quoted 25 lines · Chanwoo Choi

Hi,

Quoted 22 lines · Marc Zyngier

Quoted 18 lines · Chanwoo Choi

From: Tomasz Figa <[email protected]>

This patch add new exynos3250.dtsi to support Exynos3250 SoC based on Cortex-A7 dual core and includes following dt nodes:

- GIC interrupt controller
- Pinctrl to control GPIOs
- Clock controller
- CPU information (Cortex-A7 dual core)
- UART to support serial port
- MCT (Multi Core Timer)
- ADC (Analog Digital Converter)
- I2C/SPI bus
- Power domain
- PMU (Performance Monitoring Unit)
- MSHC (Mobile Storage Host Controller)
- PWM (Pluse Width Modulation)
- AMBA bus

[...]

Quoted 8 lines

Quoted 6 lines

Quoted 4 lines

Quoted 1 line

Where is the arch timer node?

Exynos3250 uses MCT (Multi Core Timer) instead of ARM_ARCH_TIMER.
- in drivers/clocksource/exynos_mct.c

Don't you have a Cortex-A7? If so, you have the arch timer.

Do you means that 'arch timer" is ARM_ARCH_TIMER?

Yes.

Quoted 3 lines

As I knew, ARM_ARCH_TIMER is clocksource driver for system timer. But, Exynos SoC used MCT clocksource for system timer.

Quoted 8 lines

Quoted 1 line

Exynos dts file didn't include arch timer node but only include mct node.

Well, it is a bug, and a recurrent one. A Cortex-A7 has the arch timers implemented. Always.

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/BABFEBJJ.html

All Cortex-A7 have it, and so do A12, A15, A17, A53, A57.

I tested 'arch_timer'(drivers/clocksource/arm_arch_timer.c) on Exynos3250 based on Cortex-A7.

To test arch timer, I used the clocksource of arch_timer for timekeeping instead of clocksource of Exynos MCT. But, I faced with issue. The following function return only same value(zero) as following kernel log:
- arch_counter_get_cntvct() in arch/arm/include/asm/arch_timer.h

Uncompressing Linux... done, booting the kernel.

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Initializing cgroup subsys cpuset
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Initializing cgroup subsys cpuacct
[    0.000000] Linux version 3.15.0-rc1-00020-gf452826-dirty ...
[    0.000000] CPU: ARMv7 Processor ...
...
[    0.000000] Architected cp15 timer(s) running at 24.00MHz (virt).
[    0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 2863311519744ns

...

Could you give me a solution to resolve this issue or a expected cause?

Quoted 73 lines · Chanwoo Choi

Hi Marc,

Quoted 42 lines · Marc Zyngier

Quoted 27 lines · Chanwoo Choi

Quoted 26 lines · Marc Zyngier

Quoted 25 lines · Chanwoo Choi

Hi,

Quoted 22 lines · Marc Zyngier

Quoted 18 lines · Chanwoo Choi

From: Tomasz Figa <[email protected]>

This patch add new exynos3250.dtsi to support Exynos3250 SoC based on Cortex-A7 dual core and includes following dt nodes:

- GIC interrupt controller
- Pinctrl to control GPIOs
- Clock controller
- CPU information (Cortex-A7 dual core)
- UART to support serial port
- MCT (Multi Core Timer)
- ADC (Analog Digital Converter)
- I2C/SPI bus
- Power domain
- PMU (Performance Monitoring Unit)
- MSHC (Mobile Storage Host Controller)
- PWM (Pluse Width Modulation)
- AMBA bus

[...]

Quoted 8 lines

Quoted 6 lines

Quoted 4 lines

Quoted 1 line

Where is the arch timer node?

Exynos3250 uses MCT (Multi Core Timer) instead of ARM_ARCH_TIMER.
- in drivers/clocksource/exynos_mct.c

Don't you have a Cortex-A7? If so, you have the arch timer.

Do you means that 'arch timer" is ARM_ARCH_TIMER?

Yes.

Quoted 3 lines

As I knew, ARM_ARCH_TIMER is clocksource driver for system timer. But, Exynos SoC used MCT clocksource for system timer.

Quoted 8 lines

Quoted 1 line

Exynos dts file didn't include arch timer node but only include mct node.

Well, it is a bug, and a recurrent one. A Cortex-A7 has the arch timers implemented. Always.

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/BABFEBJJ.html

All Cortex-A7 have it, and so do A12, A15, A17, A53, A57.

I tested 'arch_timer'(drivers/clocksource/arm_arch_timer.c) on Exynos3250 based on Cortex-A7.

To test arch timer, I used the clocksource of arch_timer for timekeeping instead of clocksource of Exynos MCT. But, I faced with issue. The following function return only same value(zero) as following kernel log:
- arch_counter_get_cntvct() in arch/arm/include/asm/arch_timer.h

Uncompressing Linux... done, booting the kernel.

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Initializing cgroup subsys cpuset
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Initializing cgroup subsys cpuacct
[    0.000000] Linux version 3.15.0-rc1-00020-gf452826-dirty ...
[    0.000000] CPU: ARMv7 Processor ...
...
[    0.000000] Architected cp15 timer(s) running at 24.00MHz (virt).
[    0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 2863311519744ns

...

Quoted 1 line

Could you give me a solution to resolve this issue or a expected cause?

My guess is that you need to enable some clock for the timer to tick. Ask your HW guys how they have wired this clock.

Also, I cannot help but notice that you are entering your kernel at SVC instead of HYP. I suggest you fix your bootloader/firmware to allow all CPUs to enter the kernel in HYP.

Quoted 73 lines · Chanwoo Choi

Hi Marc,

Quoted 42 lines · Marc Zyngier

Quoted 27 lines · Chanwoo Choi

Quoted 26 lines · Marc Zyngier

Quoted 25 lines · Chanwoo Choi

Hi,

Quoted 22 lines · Marc Zyngier

Quoted 18 lines · Chanwoo Choi

From: Tomasz Figa <[email protected]>

This patch add new exynos3250.dtsi to support Exynos3250 SoC based on Cortex-A7 dual core and includes following dt nodes:

- GIC interrupt controller
- Pinctrl to control GPIOs
- Clock controller
- CPU information (Cortex-A7 dual core)
- UART to support serial port
- MCT (Multi Core Timer)
- ADC (Analog Digital Converter)
- I2C/SPI bus
- Power domain
- PMU (Performance Monitoring Unit)
- MSHC (Mobile Storage Host Controller)
- PWM (Pluse Width Modulation)
- AMBA bus

[...]

Quoted 8 lines

Quoted 6 lines

Quoted 4 lines

Quoted 1 line

Where is the arch timer node?

Exynos3250 uses MCT (Multi Core Timer) instead of ARM_ARCH_TIMER.
- in drivers/clocksource/exynos_mct.c

Don't you have a Cortex-A7? If so, you have the arch timer.

Do you means that 'arch timer" is ARM_ARCH_TIMER?

Yes.

Quoted 3 lines

As I knew, ARM_ARCH_TIMER is clocksource driver for system timer. But, Exynos SoC used MCT clocksource for system timer.

Quoted 8 lines

Quoted 1 line

Exynos dts file didn't include arch timer node but only include mct node.

Well, it is a bug, and a recurrent one. A Cortex-A7 has the arch timers implemented. Always.

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/BABFEBJJ.html

All Cortex-A7 have it, and so do A12, A15, A17, A53, A57.

I tested 'arch_timer'(drivers/clocksource/arm_arch_timer.c) on Exynos3250 based on Cortex-A7.

To test arch timer, I used the clocksource of arch_timer for timekeeping instead of clocksource of Exynos MCT. But, I faced with issue. The following function return only same value(zero) as following kernel log:
- arch_counter_get_cntvct() in arch/arm/include/asm/arch_timer.h

Uncompressing Linux... done, booting the kernel.

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Initializing cgroup subsys cpuset
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Initializing cgroup subsys cpuacct
[    0.000000] Linux version 3.15.0-rc1-00020-gf452826-dirty ...
[    0.000000] CPU: ARMv7 Processor ...
...
[    0.000000] Architected cp15 timer(s) running at 24.00MHz (virt).
[    0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 2863311519744ns

...

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Could you give me a solution to resolve this issue or a expected cause?

My guess is that you need to enable some clock for the timer to tick. Ask your HW guys how they have wired this clock.

Also, I cannot help but notice that you are entering your kernel at SVC instead of HYP. I suggest you fix your bootloader/firmware to allow all CPUs to enter the kernel in HYP.