Malta: Fix reading the PCI clock frequency on big-endian

The JMPRS register on Malta boards keeps a 32-bit CPU-endian value. The readw() function assumes that the value it reads is a little-endian 16-bit number. Therefore, using readw() to obtain the value of the JMPRS register is a mistake. This error leads to incorrect reading of the PCI clock frequency on big-endian during board start-up.

Change readw() to __raw_readl().

This was tested by injecting a call to printk() and verifying that the value of the jmpr variable was consistent with current setting of the JP4 "PCI CLK" jumper.

---
 arch/mips/mips-boards/malta/malta_setup.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

index 9a2636e..bc43a5c 100644
@@ -149,7 +149,7 @@ void __init plat_mem_setup(void)
 	/* Check PCI clock */
 	{
 		unsigned int __iomem *jmpr_p = (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
-		int jmpr = (readw(jmpr_p) >> 2) & 0x07;
+		int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
 		static const int pciclocks[] __initdata = {
 			33, 20, 25, 30, 12, 16, 37, 10
 		};

1.5.3