Set ips dividor to 1/3 of csb clock.

PATCH New Grzegorz Bernacki 2 participants 2 messages Jan 16, 2008 – Feb 7, 2008 1 message not in the archive

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Grzegorz Bernacki

author

2008-01-16 16:18 UTC #1 lore raw

PATCH v2 1/1 Set ips dividor to 1/3 of csb clock.

Previous setting cause ips clock to be out of spec. This bug was found by John Rigby from Freescale.

Signed-off-by Grzegorz Bernacki <[email protected]>

include/mpc512x.h +1 -1

index a06b5c6..b51cf78 100644
@@ -185,7 +185,7 @@
 
 /* SCFR1 System Clock Frequency Register 1
  */
-#define SCFR1_IPS_DIV			0x2
+#define SCFR1_IPS_DIV			0x3
 #define SCFR1_IPS_DIV_MASK		0x03800000
 #define SCFR1_IPS_DIV_SHIFT		23

Signature · 1 line

1.5.2.2

Wolfgang Denk

Applied

2008-02-07 00:03 UTC #2 lore raw

PATCH v2 1/1 Set ips dividor to 1/3 of csb clock.

Quoted 4 lines · In message <[email protected]> you wrote:

Previous setting cause ips clock to be out of spec. This bug was found by John Rigby from Freescale.
Signed-off-by Grzegorz Bernacki <[email protected]>

Applied, thanks.