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RFC: qemu acpi hotplug

PATCH Glauber de Oliveira Costa 2 participants 2 messages Jan 16, 2008 – Jan 19, 2008 1 message not in the archive KVM

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#0 lore raw

When it's more close to inclusion, I'd also post it to main qemu list. But right now, I'm just aiming at a first round around this draft.

The attached patch is enough to make the notifications DEVICE_CHECK and EJECT reach the kernel. As far as I understand, some userspace black magic that keeps changing its scroll is needed to really put the processors logically off/on after the notify (acpi code itself will never call cpu_up/down)

Just let me tell you what you think.

Quoted 1 line

From c45432c0cec8241dbcd6ed6cf38c953b17a6f826 Mon Sep 17 00:00:00 2001

From: Glauber de Oliveira Costa <[email protected]>
Date: Wed, 16 Jan 2008 18:43:11 -0200
Subject: [PATCH] RFC: qemu cpu hotplug

---
 bios/acpi-dsdt.dsl    |   87 +++++++++++++++++++++++++++++-----
 bios/rombios32.c      |    2 +
 qemu/hw/acpi.c        |  125 +++++++++++++++++++++++++++++++++++++++++++++++++
 qemu/hw/pc.c          |    4 +-
 qemu/monitor.c        |    9 ++++
 qemu/pc-bios/bios.bin |  Bin
 6 files changed, 214 insertions(+), 13 deletions(-)
bios/acpi-dsdt.dsl +75 -12
index df255ce..497b866 100755
@@ -27,18 +27,35 @@ DefinitionBlock (
 {
     Scope (_PR)
     {
-        Processor (CPU0, 0x00, 0x0000b010, 0x06) {}
-        Processor (CPU1, 0x01, 0x0000b010, 0x06) {}
-        Processor (CPU2, 0x02, 0x0000b010, 0x06) {}
-        Processor (CPU3, 0x03, 0x0000b010, 0x06) {}
-        Processor (CPU4, 0x04, 0x0000b010, 0x06) {}
-        Processor (CPU5, 0x05, 0x0000b010, 0x06) {}
-        Processor (CPU6, 0x06, 0x0000b010, 0x06) {}
-        Processor (CPU7, 0x07, 0x0000b010, 0x06) {}
-        Processor (CPU8, 0x08, 0x0000b010, 0x06) {}
-        Processor (CPU9, 0x09, 0x0000b010, 0x06) {}
-        Processor (CPUA, 0x0a, 0x0000b010, 0x06) {}
-        Processor (CPUB, 0x0b, 0x0000b010, 0x06) {}
+	OperationRegion( PRO, SystemIO, 0xaf00, 0x02)
+	Field (PRO, ByteAcc, NoLock, WriteAsZeros)
+	{
+		PR0U, 1,
+		PR1U, 1,
+		PR2U, 1,
+		PR3U, 1,
+		PR4U, 1,
+		PADU, 3,
+
+		PR0D, 1,
+		PR1D, 1,
+		PR2D, 1,
+		PR3D, 1,
+		PR4D, 1,
+		PADD, 3,
+	}
+        Processor (CPU0, 0x00, 0x0000b010, 0x06) { Method (_STA) { Return(0x1)} }
+        Processor (CPU1, 0x01, 0x0000b010, 0x06) { Method (_STA) { Return(0x1)} }
+        Processor (CPU2, 0x02, 0x0000b010, 0x06) { Method (_STA) { Return(0x1)} }
+        Processor (CPU3, 0x03, 0x0000b010, 0x06) { Method (_STA) { Return(0x1)} }
+        Processor (CPU4, 0x04, 0x0000b010, 0x06) { Method (_STA) { Return(0x1)} } 
+        Processor (CPU5, 0x05, 0x0000b010, 0x06) { Method (_STA) { Return(0x1)} }
+        Processor (CPU6, 0x06, 0x0000b010, 0x06) { Method (_STA) { Return(0x1)} }
+        Processor (CPU7, 0x07, 0x0000b010, 0x06) { Method (_STA) { Return(0x1)} }
+        Processor (CPU8, 0x08, 0x0000b010, 0x06) { Method (_STA) { Return(0x1)} }
+        Processor (CPU9, 0x09, 0x0000b010, 0x06) { Method (_STA) { Return(0x1)} }
+        Processor (CPUA, 0x0a, 0x0000b010, 0x06) { Method (_STA) { Return(0x1)} }
+        Processor (CPUB, 0x0b, 0x0000b010, 0x06) { Method (_STA) { Return(0x1)} }
         Processor (CPUC, 0x0c, 0x0000b010, 0x06) {}
         Processor (CPUD, 0x0d, 0x0000b010, 0x06) {}
         Processor (CPUE, 0x0e, 0x0000b010, 0x06) {}
@@ -559,6 +576,51 @@ DefinitionBlock (
                 }
         }
     }
+    Scope(\_GPE)
+    {
+       Method(_L00) {  
+	  Return(0x01)
+       }
+       Method(_L01) { 
+         If (\_PR.PR1U) {
+	  Notify(\_PR.CPU1, 1)
+	 }
+	 If (\_PR.PR1D){
+	  Notify(\_PR.CPU1, 3) 
+	 }
+	 Return(0x01)
+       }
+
+       Method(_L02) { 
+         If (\_PR.PR2U) {
+	  Notify(\_PR.CPU2, 1)
+	 }
+	 If (\_PR.PR2D){
+	  Notify(\_PR.CPU2, 3) 
+	 }
+	 Return(0x01)
+       }
+
+       Method(_L03) { 
+         If (\_PR.PR3U) {
+	  Notify(\_PR.CPU3, 1)
+	 }
+	 If (\_PR.PR3D){
+	  Notify(\_PR.CPU3, 3) 
+	 }
+	 Return(0x01)
+       }
+
+       Method(_L04) { 
+         If (\_PR.PR4U) {
+	  Notify(\_PR.CPU4, 1)
+	 }
+	 IF (\_PR.PR4D) {
+	  Notify(\_PR.CPU4, 3) 
+	 }
+	 Return(0x01)
+       }
+    }
 
     /* S5 = power off state */
     Name (_S5, Package (4) {
@@ -567,4 +629,5 @@ DefinitionBlock (
         0x00, // reserved
         0x00, // reserved
     })
+
 }
bios/rombios32.c +2 -0
index 967c119..4580462 100755
@@ -1329,6 +1329,8 @@ void acpi_bios_init(void)
     fadt->pm_tmr_len = 4;
     fadt->plvl2_lat = cpu_to_le16(0x0fff); // C2 state not supported
     fadt->plvl3_lat = cpu_to_le16(0x0fff); // C3 state not supported
+    fadt->gpe0_blk = cpu_to_le32(0xafe0);
+    fadt->gpe0_blk_len = 4;
     /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC */
     fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6));
     acpi_build_table_header((struct acpi_table_header *)fadt, "FACP", 
qemu/hw/acpi.c +125 -0

128 lines not on this page · raw message

qemu/hw/pc.c +3 -1
index 3972ab4..5ce28ab 100644
@@ -1029,7 +1029,9 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
         }
     }
 
-#define USE_HYPERCALL
+    qemu_system_hot_add_init();
+
+#undef USE_HYPERCALL
 #ifdef USE_HYPERCALL
     pci_hypercall_init(pci_bus);
 #endif
qemu/monitor.c +9 -0
index e03c473..effb696 100644
@@ -346,6 +346,14 @@ static void do_cpu_set(int index)
         term_printf("Invalid CPU index\n");
 }
 
+static void do_cpu_set_nr(int value)
+{
+    if ((value < 1) || (value > 32)) /* second condition is possibly bogus. OS dependant */
+       term_printf("value out of range\n");
+    qemu_system_cpu_hot_add(value);
+
+}
+
 static void do_info_jit(void)
 {
     dump_exec_info(NULL, monitor_fprintf);
@@ -1339,6 +1347,7 @@ static term_cmd_t term_cmds[] = {
       "", "cancel the current VM migration" },
     { "migrate_set_speed", "s", do_migrate_set_speed,
       "value", "set maximum speed (in bytes) for migrations" },
+    { "cpu_set", "i", do_cpu_set_nr, "value", "number of cpus in the guest" },
     { NULL, NULL, },
 };
 
qemu/pc-bios/bios.bin binary +0 -0
index 7462753c0462e6fc863c0669664d363788e08ff3..7599b8d8956141d3355616c12bad85ac3ee112ae 100644
GIT binary patch
Signature · 1 line
1.5.0.6

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#2 lore raw
Quoted 10 lines · Glauber de Oliveira Costa

When it's more close to inclusion, I'd also post it to main qemu list. But right now, I'm just aiming at a first round around this draft.

The attached patch is enough to make the notifications DEVICE_CHECK and EJECT reach the kernel. As far as I understand, some userspace black magic that keeps changing its scroll is needed to really put the processors logically off/on after the notify (acpi code itself will never call cpu_up/down)

Just let me tell you what you think.

You aren't the only hypervisor developer to encounter this:

http://www.gossamer-threads.com/lists/linux/kernel/866461?do=post_view_threaded

The patch looks good. One thing we might change is to use just one gpe as a "something processor related has changed" and look up some other pio word to see exactly what, that may be simpler with larger numbers of processors (maybe).

Signature · 7 lines
Any sufficiently difficult bug is indistinguishable from a feature.


-------------------------------------------------------------------------
This SF.net email is sponsored by: Microsoft
Defy all challenges. Microsoft(R) Visual Studio 2008.
http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/